Cascaded Hybrid Seven Level Inverter with Different Modulation Techniques for Asynchronous Motor

Transcription

1 International Journal of Science, Engineering and Technology Research (IJSETR), Volume 3, Issue 11, November 214 Cascaded Hybrid Seven Level Inverter with Different Modulation Techniques for Asynchronous Motor Ankur Chourasiya, Poonam Chouksey, Nayna Bhargava, S. P. Phulambrikar Abstract- This paper presents a asymmetric cascaded hybrid 7 level multilevel inverter using different switching techniques i.e. phase disposition pulse width modulation, degree modulated pulse generator and hybrid mixed switching technique. This paper presents comparison between motor output and THD of Asymmetrical Cascaded hybrid 7 level Multilevel Inverter (MLI) using different modulation techniques. These control s is applied to 7 level Asymmetrical Cascaded hybrid Multilevel Inverter (CHMLI). Different topologies of multilevel inverter have been reported in the literature, but this work mainly focuses on the asymmetrical cascaded hybrid multilevel inverter circuit with reduced number of switches and input DC sources. THD and motor output are analyzed in FFT window. The results are observed by MATLAB/SIMULINK software. keywords- Asymmetrical CHMLI, Mixed switching, Degree modulated pulse generator, PDPWM. 1. INTRODUCTION Inverter is a device that converts electrical power from DC to AC form using electronic circuits. Generally simple inverter gives 2 or 3 level output voltage.the inverters with number of voltage level equal to three or above that are known as multilevel inverter.mli are capable of producing high power high voltage as the unequal voltage sources of of MLI allows to reach high voltage wiyh low harmonics without the use of transformer.mli is a latest alternative to implement low frequency based inverter with low output voltage distortion.basic Multilevel topologies are of 3 types shown in below: Diode clamped inverter Flying capacitor inverter Cascaded Figure 1.1 Multilevel inverter topologies 2. CASCADED H-BRIDGE MLI Cascaded H-Bridge (CHB) configuration has recently become very popular in high-power AC supplies and adjustable-speed drive applications. A cascade multilevel inverter consists of a series of H-bridge (single-phase full bridge) inverter units in each of its three phases. Each H- bridge unit has its personal dc source, which for an induction motor would be a battery unit, fuel cell or solar cell. Each SDC (separate D.C. source) is associated with a single-phase full-bridge inverter. The ac terminal voltage of different level inverters is connected in series. Through different combinations of the four switches, S1,S2,S3 & S4, each converter level can generate three different voltage outputs, +Vdc, -Vdc and zero. The AC outputs of different full-bridge converters in the same phase are connected in series such that the synthesized voltage waveform is the sum of the individual converter outputs, Note that the number of output-phase voltage levels is defined in different way from those of the two previous converters (i.e. flying capacitor and diode clamped). In 2897

2 International Journal of Science, Engineering and Technology Research (IJSETR), Volume 3, Issue 11, November 214 these topologies the number of output-phase voltage levels is defined by m= 2N+1, where N is the number of DC sources A seven-level cascaded converter, for example, consists of three DC sources and three full bridge converters are Minimum harmonic distortion can be obtained by controlling the conducting angles at different converters levels. Each H- bridge unit generates a quasi-square waveform by phase shifting its positive and negative phase legs switching timings. Every switching devices always conduct for 18 or half cycle regardless of the pulse width of a quasi-square wave. These switching methods make all of the switching devices current stress equal. In the motoring mode a power flows from the batteries through the cascade inverter to the motor. Figure 2.4 shows the basic block of cascade H-bridge Multi-level inverter and its associated switching instants. As shown it consists of a DC source and. The switching states for four power devices are constant i.e., When S1 is on, S2 cannot be on and vice versa, similarly with S3 or S H-BRIDGE MLI USING HYBRID MIXED SWITCHING SCHEME seven level hybrid cascaded multilevel inverter with a mixed pulse width modulation method is designed by reducing a number of switches. A simulation diagram using a mixed switching of Seven-level HMLI with asynchronous motor are shown in a figure 3.1 using MATLAB/SIMULINK. In the charging mode, the cascade converters act as rectifiers, and power flows from the charger (ac source) to the batteries. The cascade converters can also act as rectifiers to help recover the kinetic energy of the vehicle if regenerative braking is used. The cascade inverter can also be used in parallel HEV configurations. This new converter can avoid extra clamping diodes or voltage balancing capacitors. The combination of the 18 conducting method and the pattern-swapping make the cascade inverter s voltage and current stresses the same and battery voltage balanced. Figure-3.1 Seven-level HMLI using hybrid mixed switching simulation diagram with asynchronous motor Figure 2.1 Block of a h-bridge Multi-level inverter The simulation block diagram has seven level cascaded hybrid multilevel inverter with asynchronous motor is 2898

3 International Journal of Science, Engineering and Technology Research (IJSETR), Volume 3, Issue 11, November 214 shown in Fig-3.1 These are combination two types inverter: first one is H-bridge inverter and other is two conventional inverter. The conventional inverter is acting as the main inverter and H bridge inverter is acting as the auxiliary inverter HYBRID MIXED SWITCHING SCHEME Table:5.1. Pulse Generation Formula in seven level HMLI. multilevel inverter with unequal voltage sources are utilize to generate same number of voltage level per phase. The MLI consist of full bridge cell for maximum voltage and half bridge cell for intermediate voltage. When MLI fed an induction motor drive system, to reduce harmonics losses and saving energy. In topology we have generated 7 level voltage as V, 1V,2V and 3V. A simulation diagram using degree modulated pulse generator (DMPG) switching of Seven-level HMLI with asynchronous motor are shown in a figure 3.2 using MATLAB/SIMULINK. These pulses are given for eight switches. Two conventional inverter has a S 1, S 2, S 3, S 4 and H-bridge inverter has four pulse Sa 3, Sa 4, Sa 5, Sa 6. By using these modulation technique to have controlled seven level output voltage Then seven level output voltage of Hybrid multilevel inverter is produce in asynchronous motor drives & parameters of the motor are analysis in a output figure H-BRIDGE MLI USING DEGREE MODULATED PULSE GENERATOR (DMPG) SWITCHING SCHEME Figure Using degree modulated pulse generator (DMPG) switching of Seven-level HMLI with asynchronous motor In seven levels H bridge MLI total eight switches and two batteries are uses to control the output voltage. IN 2899

4 International Journal of Science, Engineering and Technology Research (IJSETR), Volume 3, Issue 11, November DEGREE MODULATED PULSE GENERATOR (DMPG) SWITCHING SCHEME Figure 3.3.1: Seven-level HMLI with asynchronous motor using phase disposition (PD) PWM switching Figure 3.2.2: Simulink model for Gate driver circuit of 7 levels HMLI PHASE DISPOSITION (PD) PWM SWITCHING SCHEME The switching technique here used is degree modulated pulse generated to identification and reference angle generation. We have generated a switching pulse to obtain staircase output voltage which resembles nearly equal to sine wave. For different switching angles the power circuit behaves defiantly producing different waveform. To obtain equal step firing a 7 level output is divided into equal segment. 3.3 H-BRIDGE MLI USING PHASE DISPOSITION (PD) PWM SWITCHING SCHEME. The simulation circuit for asymmetric cascaded 7 level with induction motor is shown in fig CHMLI 7 level has two unequal magnitude DC sources and 8 power switches are used. A simulation diagram using phase disposition (PD) PWM switching of Seven-level HMLI with asynchronous motor are shown in a figure 3.3 using MATLAB/SIMULINK. Figure Reference and carrier waveform for PD Seven-level HMLI 29

5 Mag (% of Fundamental) VOLTAGE AMPLITUDE Magnitude in Voltage(V) International Journal of Science, Engineering and Technology Research (IJSETR), Volume 3, Issue 11, November SIMULATION RESULTS 4 Output voltage wave forms in Seven Level HMLI TIME (Seconds) Figure-4.1 Output voltage waveform for Seven-level HMLI using hybrid mixed switching Show the above figure-4.1 MATLAB simulation result for a seven level inverter with hybrid mixed switching. Multilevel carrier based pulse width modulation methods are used in these inverter topologies. Fig 4.3: Motor output of seven-level HMLI using hybrid mixed switching Output voltage of Seven-level HMLI using degree modulated pulse generator (DMPG) switching 3 Fundamental (5Hz) = 265.7, THD= 1.59% Harmonic order TIME(SEC) Figure 4.4: Output voltage of Seven-level HMLI using degree modulated pulse generator (DMPG) switching Figure-4.2 FFT analysis for Seven-level HMLI using hybrid mixed switching Show the above figure MATLAB simulation result for a seven level inverter with equal step firing using degree modulation switching 291

6 Mag (% of Fundamental) Mag (% of Fundamental) VOLTAGE AMPLITUDE International Journal of Science, Engineering and Technology Research (IJSETR), Volume 3, Issue 11, November 214 Fundamental (5Hz) = 257.5, THD= 26.22% 4 Output voltage waveform for Seven-level HMLI using degree modulated pulse generator (DMPG) switching Frequency (Hz) Figure-4.5 FFT analysis for Seven-level HMLI using degree modulated pulse generator (DMPG) switching TIME (SEC) Figure-4.7 Output voltage waveform for Seven-level HMLI using phase disposition (PD) PWM switching The output voltage waveform of 7 level CHMLI with capacitor start run motor induction motor is shown in fig 4.7 Fundamental (5Hz) = 288.2, THD= 4.65% Frequency (Hz) Figure-4.6: Motor output of seven-level HMLI using degree modulated pulse generator (DMPG) switching Figure-4.8 FFT analysis for Seven-level HMLI using phase disposition (PD) PWM switching 292

7 International Journal of Science, Engineering and Technology Research (IJSETR), Volume 3, Issue 11, November 214 Table no. 4: Variation of Induction Motor Parameters HMLI using switching mixed switching degree modulated phase disposition Main winding current (Amp) Rotor speed ( rad /sec) Electromagnetic Torque (Nm) All simulation results are shown in above table no. 3 and table no. 4 respectively. Figure-4.9: Motor output of seven-level HMLI using phase disposition (PD) PWM switching Table no. 3: Steady state value for Induction Motor HMLI using switching mixed switching degree modulate d phase dispositio n Time to reached Steady state value of Main winding current Time to reached Steady state value of Rotor Speed Time to reached Steady state value of Electromagneti c Torque THD.25 sec.25 sec.25sec %.2 sec..25 sec.2 sec 22.89%.2 sec..2 sec..2 sec. 9.76% 5. CONCLUSION The paper deals with a comparison of cascaded 7 level multilevel inverters for Asynchronous motor using different modulation techniques i.e. phase disposition pulse width modulation, degree modulated pulse generator and hybrid mixed switching technique. Indeed, asymmetrical 7 level multilevel inverter have been compared in order to find an optimum motor speed, torque and main winding current with lower switching losses, Total harmonic distortion and optimized output voltage quality. The asymmetric cascaded 7 level inverter gives optimum motor output and reduced THD using pulse width modulation technique. The steady state condition of motor output has reached earlier in case of asymmetrical cascaded 7 level inverter using pulse width modulation (phase disposition) as compared to other two techniques. 6. REFERENCES 1. Ankur Chourasiya, S.S Thakur, S. P. Phulambrikar, Harmonic Reduction in New PWM Switching Scheme of Hybrid Multilevel Inverter International Journal of Engineering Research & Technology (IJERT) ISSN: Vol. 3 Issue 8, August Nayna Bhargava, Sanjeev Gupta, S. P. Phulambrikar Analysis of Asymmetric Cascaded 7 level and 9 level Multilevel Inverter for Asynchronous Motor International Journal of Engineering Research & Technology (IJERT) ISSN: Vol. 3,Issue 8,August Poonam Chouksey, S. P. Phulambrikar, Sanjeev Gupta Design of Efficient Novel Multilevel Inverter By Reducing Harmonics With Reduces Number of Batteries and Switches International Journal of Engineering Research & Technology (IJERT) ISSN: Vol. 3,Issue 8,August

8 International Journal of Science, Engineering and Technology Research (IJSETR), Volume 3, Issue 11, November Ayoub Kavousi, Behrooz Vahidi, Reza Salehi, Mohammad Kazem Bakhshizadeh senior IEEEmember," Application of the Bee Algorithm for Selective Harmonic Elimination Strategy in Multilevel Inverters" IEEE Transactions On Power Electronics, Vol. 27, No. 4, April Jose Rodriguez, Jih-sheng lai, Fan zheng peng, senior member IEEE,"Multilevel inverter: A survey oftopologies, controls, and applications"ieeetransactions on industrial electronics, vol. 49,no.4,aug Haiwen Liu, Leon M, Surin Khomfoi,"Hybrid cascaded multilevel inverter with PWM control Method" /8,28IEEE. 7. Surin Khomfoi, Nattapat Praisuwanna, LeonM.Tolbert, "A hybrid multilevel inverter application For renewable energy resources including a recofiguration technique" /1/21 IEEE 8.S.Khomofi, AChatrchai,"A 5-level cascaded hybrid multilevel inverter for interfacing with renewableenergy resoures,"proceedings of the 29 electricalengineering /electronics,computer telecommunications,and information technology, Chonburi May 6-9,29,pp M. Thirumalai, V. Prakash, "Design and Implementation of Hybrid Multilevel Inverter for High Output Efficiency," International Conference on Smart Structures & System (ICSSS-213), March 28-29, 213, Chennai, India. 1. Rashid, M. H, 24. Power electronics: Circuits, devices and applications. Third Edition, Prentice Hall. 12. J. Rodriguez, J. S. Lai, and F. Z. Peng, Multilevel Inverters: A survey of topologies, controls and applications, Industrial Electronics, IEEE Trans. Ind. Electronics, Volume 49, no. 4, pp , Ebrahim Babaei, 28, A Cascaded Multilevel Converter Topology with Reduced number of Switches IEEE Transactions on power electronics, Vol. 23, No Bharath. K, R. J. Satputaley, Single phase Asymmetrical Cascaded Multilevel Inverter Design for Induction Motor, ASAR International Conference, ISBN: K. Radha Sree, Sivapathi, Vardhaman. V, and Dr. R. Seyezhai, Asymmetric Cascaded Multilevel Inverter for Electric Vehicles, IEEE- ICAESM P. Satheesh Kumar, Dr S. P. Natrajan, Dr. Alamelu Nachiappan, Dr. B. Shanthi, Performance Evaluation of Nine Level Modified CHB Multilevel Inverter for Various PWM Strategies, IJMER, Vol. 3. Issue. 5, Sept-Oct. 213 pp Rashmy Deepak,Dr. Y R manjunatha, Dr. B R Lakshikantha, " Novel Multilevel Inverter with Reduced Number of Switches and Batteries," IEEE Ankur chourasiya - received the B.E.degree in Electronics and communication. From the Peoples collage of research and technology, Bhopal (M.P.) India, in and M.Tech pursuing From Samrat ashok technical institute Vidisha (m.p.) India, done M Tech thesis on Harmonic Reduced In New PWM Switching Scheme of Hybrid Multilevel Inverter paper publish on Harmonic Reduction in New PWM Switching Scheme of Hybrid Multilevel Inverter International Journal of Engineering Research & Technology (IJERT) ISSN: Vol. 3 Issue 8, August 214.and Five level hybrid Cascaded multilevel inverter Harmonic reduced in PWM switching International journal for scientific research & development (IJSRD) ISSN: volume 2,issue $, in oct 214. Poonam Chouksey recrived the B.E. degree in Electrical engineering From Indira Gandhi Engineering collage Sager, M.P. India in 28 to 212.& Master of Engineering pursuing from samrat ashok technological institute, vidisha, M.P. india. done M.E. thesis topic on Design of Efficient Novel Multilevel Inverter By Reducing Harmonics With Reduces Number of Batteries and Switches and paper published on Design of Efficient Novel Multilevel Inverter By Reducing Harmonics With Reduces Number of Batteries and Switches International Journal of Engineering Research & Technology (IJERT) ISSN: Vol. 3,Issue 8,August Nayna Bhargava received B.E. degree in Electrical engineering from Lakshmi Narain College Of Technology Bhopal, MP. India in 26 to 21 & Master Of Engineering pursuing from Samrat Ashok Technological Institute, Vidisha, M.P. India. done M.E. thesis topic on Analysis of Asymmetric Cascaded 7 level and 9 level Multilevel Inverter for Asynchronous Motor and paper published on Analysis of Asymmetric Cascaded 7 level and 9 level Multilevel Inverter for Asynchronous Motor International Journal of Engineering Research & Technology (IJERT) ISSN: Vol. 3,Issue 8,August Sudhir phulambrikar,,be, M.TEC. having more then 3 years teaching experience. Has published several papers in conferences, national and international, He is currently working on head of electrical engineering department of Samrat ashok technological institute Vidisha (m.p.) 18 Ghoni Ruzlaini, Abdalla N. Ahmed, "Analysis And Mathematical Modelling Of Space Vector Modulated Direct Controlled Matrix Converter", JATIT. 294