LTM4601HV 12A 28V IN DC/DC µmodule Regulator with PLL, Output Tracking and Margining APPLICATIONS TYPICAL APPLICATION

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1 FEATURES n Complete Switch Mode Power Supply n Wide Input Voltage Range:.5V to 28V n 12A DC Typical, 1A Peak Output Current n.6v to 5V Output Voltage n Output Voltage Tracking and Margining n Parallel Multiple µmodule Regulators for Current Sharing n Differential Remote Sensing for Precision Regulation n PLL Frequency Synchronization n ±1.5% Regulation n Current Foldback Protection (Disabled at StartUp) n RoHS Compliant with PbFree Finish, Gold Finish LGA (e) or SAC 35 BGA (e1) n Ultrafast Transient Response n Current Mode Control n Up to 95% Efficiency at 5, 3.3 n Programmable SoftStart n Output Overvoltage Protection n Small Footprint, Low Profile (15mm 15mm 2.82mm) Surface Mount LGA and (15mm 15mm 3.2mm) BGA Packages APPLICATIONS n Telecom and Networking Equipment n Servers n Industrial Equipment n Point of Load Regulation LTM61HV 12A 28 DC/DC µmodule Regulator with PLL, Output Tracking and Margining DESCRIPTION The LTM 61HV is a complete 12A stepdown switch mode DC/DC power supply with onboard switching controller, MOSFETs, inductor and all support components. The µmodule regulator is housed in small surface mount 15mm 15mm 2.82mm LGA and 15mm 15mm 3.2mm BGA packages. Operating over an input voltage range of.5v to 28V, the LTM61HV supports an output voltage range of.6v to 5V as well as output voltage tracking and margining. The high efficiency design delivers 12A continuous current (1A peak). Only bulk input and output capacitors are needed to complete the design. The low profile and light weight package easily mounts in unused space on the back side of PC boards for high density point of load regulation. The µmodule regulator can be synchronized with an external clock for reducing undesirable frequency harmonics and allows PolyPhase operation for high load currents. A high switching frequency and adaptive ontime current mode architecture deliver a very fast transient response to line and load changes without sacrificing stability. An onboard differential remote sense amplifier can be used to accurately regulate an output voltage independent of load current. L, LT, LTC, LTM, Linear Technology, the Linear logo, µmodule and PolyPhase are registered trademarks and LTpowerCAD is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents including , 58755, , 6366, , , TYPICAL APPLICATION 2.5V/12A Power Supply with.5v to 28V Input Efficiency and Power Loss vs Load Current.5V TO 28V C IN ON/OFF R1 392k 5% MARGIN RUN INTV CC DRV CC MPGM SGND PLLIN TRACK/SS LTM61HV MARG MARG1 _LCL DIFF V OSNS V OSNS f SET CLOCK SYNC TRACK/SS CONTROL 1pF MARGIN CONTROL R SET 19.1k 61HV TA1a 2.5V 12A C OUT EFFICIENCY (%) EFFICIENCY 2 12 POWER LOSS LOAD CURRENT (A) POWER LOSS (W) 61HV TA1b 1

2 ABSOLUTE MAXIMUM RATINGS (Note 1) INTV CC, DRV CC, _LCL, ( 3.3V with Remote Sense Amp)....3V to 6V PLLIN, TRACK/SS, MPGM, MARG, MARG1,, f SET....3V to INTV CC.3V RUN....3V to 5V,....3V to 2.7V....3V to 28V,....3V to INTV CC.3V Operating Temperature Range (Note 2)... C to 85 C Junction Temperature C Storage Temperature Range C to 125 C PIN CONFIGURATION TOP VIEW INTVCC PLLIN TRACK/SS RUN MPGM TOP VIEW INTVCC PLLIN TRACK/SS RUN MPGM f SET f SET MARG MARG MARG1 MARG1 DRV CC DRV CC SGND SGND DIFF _LCL DIFF _LCL LGA PACKAGE 118LEAD (15mm 15mm 2.82mm) T JMAX = 125 C, θ JA = 15 C/W, θ JC = 6 C/W, θ JA DERIVED FROM 95mm 76mm PCB WITH LAYERS WEIGHT = 1.7g BGA PACKAGE 118LEAD (15mm 15mm 3.2mm) T JMAX = 125 C, θ JA = 15.5 C/W, θ JC = 6.5 C/W, θ JA DERIVED FROM 95mm 76mm PCB WITH LAYERS WEIGHT = 1.9g ORDER INFORMATION LEAD FREE FINISH TRAY PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTM61HVEV#PBF LTM61HVEV#PBF LTM61HVV 118Lead (15mm 15mm 2.82mm) LGA C to 85 C LTM61HVIV#PBF LTM61HVIV#PBF LTM61HVV 118Lead (15mm 15mm 2.82mm) LGA C to 85 C LTM61HVEY#PBF LTM61HVEY#PBF LTM61HVY 118Lead (15mm 15mm 3.2mm) BGA C to 85 C LTM61HVIY#PBF LTM61HVIY#PBF LTM61HVY 118Lead (15mm 15mm 3.2mm) BGA C to 85 C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. For more information on lead free part marking, go to: This product is only offered in trays. For more information go to: 2

3 ELECTRICAL CHARACTERISTICS LTM61HV The l denotes the specifications which apply over the C to 85 C temperature range (Note 2), otherwise specifications are at T A = 25 C, = 12V, per typical application (front page) configuration, R SET =.2k. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS (DC) Input DC Voltage l.5 28 V (DC) Output Voltage (With Remote Sense Amp) Input Specifications C IN = 1µF 3, C OUT = 2µF, R SET =.2k = 12V, = 1.5V, I OUT = l V (UVLO) Undervoltage Lockout Threshold I OUT = A 3.2 V I INRUSH(VIN) Input Inrush Current at Startup I OUT = A. = 1.5V = 5V = 12V I Q(VIN,NO LOAD) Input Supply Bias Current = 12V, No Switching = 12V, = 1.5V, Switching Continuous = 5V, No Switching = 5V, = 1.5V, Switching Continuous Shutdown, RUN =, VIN = 12V I S(VIN) Input Supply Current = 12V, = 1.5V, I OUT = 12A = 12V, = 3.3V, I OUT = 12A = 5V, = 1.5V, I OUT = 12A INTV CC = 12V, RUN > 2V No Load V Output Specifications I OUTDC Output Continuous Current Range = 12V, = 1.5V (Note 5) 12 A Δ(LINE) Line Regulation Accuracy = 1.5V, I OUT = A, from.5v to 28V l.3 % Load Regulation Accuracy V = 1.5V, I = A to 12A, with RSA (Note 5) Δ(LOAD) OUT OUT = 5V = 12V (AC) Output Ripple Voltage I OUT = A, C OUT = 2 1µF X5R Ceramic = 12V, = 1.5V = 5V, = 1.5V f S Output Ripple Voltage Frequency I OUT = 5A, = 12V, = 1.5V 85 khz Δ(START) TurnOn Overshoot C OUT = 2µF, = 1.5V, I OUT = A, TRACK/SS = 1nF = 12V = 5V t START TurnOn Time C OUT = 2µF, = 1.5V, TRACK/SS = Open, I OUT = 1A Resistive Load = 12V = 5V ΔLS Peak Deviation for Dynamic Load Load: % to 5% to % of Full Load, C OUT = 2 22µF Ceramic, 7µF V Sanyo POSCAP = 12V = 5V t SETTLE Settling Time for Dynamic Load Step Load: % to 5%, or 5% to % of Full Load = 12V 25 µs I OUTPK Output Current Limit C OUT = 2µF Ceramic = 12V, = 1.5V = 5V, = 1.5V l l A A ma ma ma ma µa A A A % % mv PP mv PP mv mv ms ms mv mv A A 3

4 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the C to 85 C temperature range (Note 2), otherwise specifications are at T A = 25 C, = 12V, per typical application (front page) configuration, R SET =.2k. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Remote Sense Amp (Note 3) V OSNS, V OSNS Common Mode Input Voltage Range = 12V, RUN > 2V INTV CC 1 V CM Range DIFF Output Voltage Range = 12V, DIFF Load = 1k INTV CC 1 V Range V OS Input Offset Voltage Magnitude 1.25 mv A V Differential Gain 1 V/V GBP Gain Bandwidth Product 3 MHz SR Slew Rate 2 V/µs R IN Input Resistance V OSNS to GND 2 kw CMRR Common Mode Rejection Mode 1 db Control Stage Error Amplifier Input Voltage I OUT = A, = 1.5V l V Accuracy V RUN RUN Pin On/Off Threshold V I TRACK/SS SoftStart Charging Current V TRACK/SS = V µa t ON(MIN) Minimum On Time (Note ) 5 1 ns t OFF(MIN) Minimum Off Time (Note ) 25 ns R PLLIN PLLIN Input Resistance 5 kω I DRVCC Current into DRV CC Pin = 1.5V, I OUT = 1A, DRV CC = 5V ma R FBHI Resistor Between _LCL and kω V MPGM Margin Reference Voltage 1.18 V V MARG, MARG, MARG1 Voltage Thresholds 1. V V MARG1 Output ΔH Upper Threshold Rising % ΔL Lower Threshold Falling % Δ(HYS) Hysteresis Returning 1.5 % Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LTM61HV is tested under pulsed load conditions such that T J T A. The LTM61HVE is guaranteed to meet performance specifications from C to 85 C. Specifications over the C to 85 C operating temperature range are assured by design, characterization and correlation with statistical process controls. The LTM61HVI is guaranteed over the C to 85 C temperature range. Note 3: Remote sense amplifier recommended for 3.3V output. Note : 1% tested at wafer level only. Note 5: See output current derating curves for different, and T A.

5 TYPICAL PERFORMANCE CHARACTERISTICS (See Figures 19 and 2 for all curves) EFFICIENCY (%) Efficiency vs Load Current with LOAD CURRENT (A) 15 EFFICIENCY (%) Efficiency vs Load Current with LOAD CURRENT (A) 15 EFFICIENCY (%) Efficiency vs Load Current with LOAD CURRENT (A) HV G1 61HV G2 61HV G3 1.2V Transient Response 1.5V Transient Response 1.8V Transient Response 5mV/DIV 5mV/DIV 5mV/DIV A TO 6A LOAD STEP A TO 6A LOAD STEP A TO 6A LOAD STEP 2µs/DIV 1.2V AT 6A/µs LOAD STEP C OUT = 3 22µF CERAMICS 7µF V SANYO POSCAP C3 = 1pF 61HV G 2µs/DIV 1.5V AT 6A/µs LOAD STEP C OUT = 3 22µF CERAMICS 7µF V SANYO POSCAP C3 = 1pF 61HV G5 2µs/DIV 1.8V AT 6A/µs LOAD STEP C OUT = 3 22µF CERAMICS 7µF V SANYO POSCAP C3 = 1pF 61HV G6 2.5V Transient Response 3.3V Transient Response 5mV/DIV 5mV/DIV A TO 6A LOAD STEP A TO 6A LOAD STEP 2µs/DIV 2.5V AT 6A/µs LOAD STEP C OUT = 3 22µF CERAMICS 7µF V SANYO POSCAP C3 = 1pF 61HV G7 2µs/DIV 3.3V AT 6A/µs LOAD STEP C OUT = 3 22µF CERAMICS 7µF V SANYO POSCAP C3 = 1pF 61 G8 5

6 TYPICAL PERFORMANCE CHARACTERISTICS (See Figures 19 and 2 for all curves) StartUp, I OUT = A StartUp, I OUT = 12A (Resistive Load).5V/DIV.5V/DIV I IN.5A/DIV I IN 1A/DIV 5ms/DIV = 12V = 1.5V C OUT = 7µF, 3 22µF SOFTSTART = 1nF 61HV G9 2ms/DIV = 12V = 1.5V C OUT = 7µF, 3 22µF SOFTSTART = 1nF 61HV G1 OUTPUT VOLTAGE (V) to StepDown Ratio INPUT VOLTAGE (V) 3.3PUT WITH 13k FROM TO I ON 5PUT WITH 1k RESISTOR ADDED FROM f SET TO GND 5PUT WITH NO RESISTOR ADDED FROM f SET TO GND 2.5PUT 1.8PUT 1.5PUT 1.2PUT TRACK/SS.5V/DIV.5V/DIV 1V/DIV Track, I OUT = 12A 2ms/DIV = 12V = 1.5V C OUT = 7µF, 3 22µF SOFTSTART = 1nF 61HV G12 61HV G11 ShortCircuit Protection, I OUT = A ShortCircuit Protection, I OUT = 12A.5V/DIV.5V/DIV I IN 1A/DIV I IN 1A/DIV = 12V 5µs/DIV = 1.5V C OUT = 7µF, 3 22µF SOFTSTART = 1nF 61HV G13 = 12V 5µs/DIV = 1.5V C OUT = 7µF, 3 22µF SOFTSTART = 1nF 61HV G1 6

7 PIN FUNCTIONS (See Package Description for Pin Assignment) (Bank 1): Power Input Pins. Apply input voltage between these pins and pins. Recommend placing input decoupling capacitance directly between pins and pins. (Bank 3): Power Output Pins. Apply output load between these pins and pins. Recommend placing output decoupling capacitance directly between these pins and pins. See Figure 17. (Bank 2): Power ground pins for both input and output returns. V OSNS (Pin M12): ( ) Input to the Remote Sense Amplifier. This pin connects to the ground remote sense point. The remote sense amplifier is used for 3.3V. Tie to INTV CC if not used. V OSNS (Pin J12): () Input to the Remote Sense Amplifier. This pin connects to the output remote sense point. The remote sense amplifier is used for 3.3V. Tie to ground if not used. DIFF (Pin K12): Output of the Remote Sense Amplifier. This pin connects to the _LCL pin. Leave floating if remote sense amplifier is not used. DRV CC (Pin E12): This pin normally connects to INTV CC for powering the internal MOSFET drivers. This pin can be biased up to 6V from an external supply with about 5mA capability, or an external circuit as shown in Figure 18. This improves efficiency at the higher input voltages by reducing power dissipation in the module. INTV CC (Pin A7): This pin is for additional decoupling of the 5V internal regulator. PLLIN (Pin A8): External Clock Synchronization Input to the Phase Detector. This pin is internally terminated to SGND with a 5k resistor. Apply a clock with a high level above 2V and below INTV CC. See the Applications Information section. LTM61HV TRACK/SS (Pin A9): Output Voltage Tracking and Soft Start Pin. When the module is configured as a master output, then a softstart capacitor is placed on this pin to ground to control the master ramp rate. A softstart capacitor can be used for softstart turn on of a stand alone regulator. Slave operation is performed by putting a resistor divider from the master output to ground, and connecting the center point of the divider to this pin. See the Applications Information section. MPGM (Pin A12): Programmable Margining Input. A resistor from this pin to ground sets a current that is equal to 1.18V/R. This current multiplied by 1kΩ will equal a value in millivolts that is a percentage of the.6v reference voltage. See Applications Information. To parallel LTM61HVs, each requires an individual MPGM resistor. Do not tie MPGM pins together. f SET (Pin B12): Frequency Set Internally to 85kHz. An external resistor can be placed from this pin to ground to increase frequency. See the Applications Information section for frequency adjustment. (Pin F12): The Negative Input of the Error Amplifier. Internally, this pin is connected to _LCL pin with a 6.k precision resistor. Different output voltages can be programmed with an additional resistor between and SGND pins. See the Applications Information section. MARG (Pin C12): This pin is the LSB logic input for the margining function. Together with the MARG1 pin it will determine if margin high, margin low or no margin state is applied. The pin has an internal pulldown resistor of 5k. See the Applications Information section. MARG1 (Pin D12): This pin is the MSB logic input for the margining function. Together with the MARG pin it will determine if margin high, margin low or no margin state is applied. The pin has an internal pulldown resistor of 5k. See the Applications Information section. 7

8 PIN FUNCTIONS (See Package Description for Pin Assignment) SGND (Pin H12): Signal Ground. This pin connects to at output capacitor point. See Figure 17. (Pin A11): Current Control Threshold and Error Amplifier Compensation Point. The current comparator threshold increases with this control voltage. The voltage ranges from V to 2.V with.7v corresponding to zero sense voltage (zero current). (Pin G12): Output Voltage Power Good Indicator. Opendrain logic output that is pulled to ground when the output voltage is not within ±1% of the regulation point, after a 25µs power bad mask timer expires. RUN (Pin A1): Run Control Pin. A voltage above 1.9V will turn on the module, and when below 1V, will turn off the module. A programmable UVLO function can be accomplished by connecting to a resistor divider from to ground. See Figure 1. This pin has a 5.1V Zener to ground. Maximum pin voltage is 5V. Limit current into the RUN pin to less than 1mA. _LCL (Pin L12): connects directly to this pin to bypass the remote sense amplifier, or DIFF connects to this pin when remote sense amplifier is used. 8

9 SIMPLIFIED BLOCK DIAGRAM UVLO FUNCTION VIN R1 R2 >1.9V = ON <1V = OFF MAX = 5V _LCL RUN 1M 5.1V ZENER 1.5µF.5V TO 28V C IN 6.k SGND MARG1 MARG INTERNAL POWER CONTROL Q1.7µH 22µF 2.5V 12A R SET 19.1k f SET 39.2k 5k 5k 2.2Ω Q2 C OUT C SS MPGM TRACK/SS PLLIN INTV CC.7µF 5k 1k INTV CC 1k 1k 1k DRV CC DIFF 61HV F1 = SGND = Figure 1. Simplified LTM61HV Block Diagram DECOUPLING REQUIREMENTS T A = 25 C, = 12V. Use Figure 1 configuration. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS C IN External Input Capacitor Requirement I OUT = 12A, 3 1µF Ceramics 2 3 µf ( =.5V to 28V, = 2.5V) C OUT External Output Capacitor Requirement ( =.5V to 28V, = 2.5V) I OUT = 12A 1 2 µf 9

10 OPERATION Power Module Description The LTM61HV is a standalone nonisolated switching mode DC/DC power supply. It can deliver up to 12A of DC output current with some external input and output capacitors. This module provides a precisely regulated output voltage programmable via one external resistor from.6v DC to 5.V DC over a.5v to 28V wide input voltage. The typical application schematics are shown in Figures 19 and 2. The LTM61HV has an integrated constant ontime current mode regulator, ultralow R DS(ON) FETs with fast switching speed and integrated Schottky diodes. The typical switching frequency is 85kHz at full load. With current mode control and internal feedback loop compensation, the LTM61HV module has sufficient stability margins and good transient performance under a wide range of operating conditions and with a wide range of output capacitors, even all ceramic output capacitors. Current mode control provides cyclebycycle fast current limit. Besides, foldback current limiting is provided in an overcurrent condition while drops. Internal overvoltage and undervoltage comparators pull the opendrain output low if the output feedback voltage exits a ±1% window around the regulation point. Furthermore, in an overvoltage condition, internal top FET Q1 is turned off and bottom FET Q2 is turned on and held on until the overvoltage condition clears. Pulling the RUN pin below 1V forces the controller into its shutdown state, turning off both Q1 and Q2. At low load current, the module works in continuous current mode by default to achieve minimum output voltage ripple. When DRV CC pin is connected to INTV CC an integrated 5V linear regulator powers the internal gate drivers. If a 5V external bias supply is applied on the DRV CC pin, then an efficiency improvement will occur due to the reduced power loss in the internal linear regulator. This is especially true at the high end of the input voltage range. The LTM61HV has a very accurate differential remote sense amplifier with very low offset. This provides for very accurate output voltage sensing at the load. The MPGM pin, MARG pin and MARG1 pin are used to support voltage margining, where the percentage of margin is programmed by the MPGM pin, and MARG and MARG1 select margining. The PLLIN pin provides frequency synchronization of the device to an external clock. The TRACK/SS pin is used for power supply tracking and softstart programming. 1

11 APPLICATIONS INFORMATION The typical LTM61HV application circuits are shown in Figures 19 and 2. External component selection is primarily determined by the maximum load current and output voltage. Refer to Table 2 for specific external capacitor requirements for a particular application. to StepDown Ratios There are restrictions in the maximum to step down ratio that can be achieved for a given input voltage. These constraints are shown in the Typical Performance Characteristics curves labeled to StepDown Ratio. Note that additional thermal derating may apply. See the Thermal Considerations and Output Current Derating section of this data sheet. Output Voltage Programming and Margining The PWM controller has an internal.6v reference voltage. As shown in the Block Diagram, a 1M and a 6.k.5% internal feedback resistor connects and pins together. The _LCL pin is connected between the 1M and the 6.k resistor. The 1M resistor is used to protect against an output overvoltage condition if the _LCL pin is not connected to the output, or if the remote sense amplifier output is not connected to _LCL. In these cases, the output voltage will default to.6v. Adding a resistor R SET from the pin to SGND pin programs the output voltage: =.6V 6.k R SET R SET or equivalently: R SET = 6.k.6V 1 Table 1. R SET Standard 1% Resistor Values vs R SET (kω) (V) Open The MPGM pin programs a current that when multiplied by an internal 1k resistor sets up the.6v reference ± offset for margining. A 1.18V reference divided by the RPGM resistor on the MPGM pin programs the current. Calculate (MARGIN) : (MARGIN) = % 1 where % is the percentage of you want to margin, and (MARGIN) is the margin quantity in volts: R PGM =.6V 1.18V (MARGIN) 1k where R PGM is the resistor value to place on the MPGM pin to ground. The margining voltage, (MARGIN), will be added or subtracted from the nominal output voltage as determined by the state of the MARG and MARG1 pins. See the truth table below: MARG1 MARG MODE LOW LOW NO MARGIN LOW HIGH MARGIN UP HIGH LOW MARGIN DOWN HIGH HIGH NO MARGIN Input Capacitors LTM61HV module should be connected to a low AC impedance DC source. Input capacitors are required to be placed adjacent to the module. In Figure 2, the 1µF ceramic input capacitors are selected for their ability to handle the large RMS current into the converter. An input bulk capacitor of 1µF is optional. This 1µF capacitor is only needed if the input source impedance is compromised by long inductive leads or traces. For a buck converter, the switching dutycycle can be estimated as: D = 11

12 APPLICATIONS INFORMATION Without considering the inductor ripple current, the RMS current of the input capacitor can be estimated as: I CIN(RMS) = I OUT(MAX) η% D ( 1 D ) In the above equation, η% is the estimated efficiency of the power module. C IN can be a switcherrated electrolytic aluminum capacitor, OSCON capacitor or high value ceramic capacitor. Note the capacitor ripple current ratings are often based on temperature and hours of life. This makes it advisable to properly derate the input capacitor, or choose a capacitor rated at a higher temperature than required. Always contact the capacitor manufacturer for derating requirements. In Figures 19 and 2, the 1µF ceramic capacitors are together used as a high frequency input decoupling capacitor. In a typical 12A output application, three very low ESR, X5R or X7R, 1µF ceramic capacitors are recommended. These decoupling capacitors should be placed directly adjacent to the module input pins in the PCB layout to minimize the trace inductance and high frequency AC noise. Each 1µF ceramic is typically good for 2A to 3A of RMS ripple current. Refer to your ceramics capacitor catalog for the RMS current ratings. Multiphase operation with multiple LTM61HV devices in parallel will lower the effective input RMS ripple current due to the interleaving operation of the regulators. Application Note 77 provides a detailed explanation. Refer to Figure 2 for the input capacitor ripple current reduction as a function of the number of phases. The figure provides a ratio of RMS ripple current to DC load current as function of duty cycle and the number of paralleled phases. Pick the corresponding duty cycle and the number of phases to arrive at the correct ripple current value. For example, the 2phase parallel LTM61HV design provides 2A at 2.5V output from a 12V input. The duty cycle is DC = 2.5V/12V =.21. The 2phase curve has a ratio of ~.25 for a duty cycle of.21. This.25 ratio of RMS ripple current to a DC load current of 2A equals ~6A of input RMS ripple current for the external input capacitors. Output Capacitors The LTM61HV is designed for low output ripple voltage. The bulk output capacitors defined as C OUT are chosen with low enough effective series resistance (ESR) to meet the output voltage ripple and transient requirements. C OUT can be a low ESR tantalum capacitor, a low ESR polymer capacitor or a ceramic capacitor. The typical capacitance is 2µF if all ceramic output capacitors are used. Additional output filtering may be required by the system designer if further reduction of output ripple or dynamic transient spike is required. Table 2 shows a matrix of different output voltages and output capacitors to minimize the voltage droop and overshoot during a 5A/µs transient. The table optimizes total equivalent ESR and total bulk capacitance to maximize transient performance. RMS INPUT RIPPLE CURRENT DC LOAD CURRENT PHASE 2PHASE 3PHASE PHASE 6PHASE 12PHASE DUTY CYCLE ( / ) 61HV F2 Figure 2. Normalized Input RMS Ripple Current vs Duty Cycle for One to Six Modules (Phases) 12

13 APPLICATIONS INFORMATION Multiphase operation with multiple LTM61HV devices in parallel will lower the effective output ripple current due to the interleaving operation of the regulators. For example, each LTM61HV s inductor current in a 12V to 2.5V multiphase design can be read from the Inductor IL (A) DUTY CYCLE ( / ) 61HV F3 2.5PUT 5PUT 1.8PUT 1.5PUT 1.2PUT 3.3PUT WITH 13k ADDED FROM TO f SET 5PUT WITH 1k ADDED FROM f SET TO GND Figure 3. Inductor Ripple Current vs Duty Cycle Ripple Current vs Duty Cycle graph (Figure 3). The large ripple current at low duty cycle and high output voltage can be reduced by adding an external resistor from f SET to ground which increases the frequency. If the duty cycle is DC = 2.5V/12V =.21, the inductor ripple current for 2.5V output at 21% duty cycle is ~6A in Figure 3. Figure provides a ratio of peaktopeak output ripple current to the inductor current as a function of duty cycle and the number of paralleled phases. Pick the corresponding duty cycle and the number of phases to arrive at the correct output ripple current ratio value. If a 2phase operation is chosen at a duty cycle of 21%, then.6 is the ratio. This.6 ratio of output ripple current to inductor ripple of 6A equals 3.6A of effective output ripple current. Refer to Application Note 77 for a detailed explanation of output ripple current reduction as a function of paralleled phases. The output ripple voltage has two components that are related to the amount of bulk capacitance and effective series resistance (ESR) of the output bulk capacitance. 1. PEAKTOPEAK OUTPUT RIPPLE CURRENT DIr RATIO = PHASE 2PHASE 3PHASE PHASE 6PHASE DUTY CYCLE (V O / ) Figure. Normalized Output Ripple Current vs Duty Cycle, Dlr = V O T/L I, Dlr = Each Phase s Inductor Current 61HV F 13

14 APPLICATIONS INFORMATION Therefore, the output ripple voltage can be calculated with the known effective output ripple current. The equation: Δ(PP) (ΔI L /(8 f m C OUT ) ESR ΔI L ), where f is frequency and m is the number of parallel phases. This calculation process can be easily accomplished by using LTpowerCAD. Fault Conditions: Current Limit and Overcurrent Foldback LTM61HV has a current mode controller, which inherently limits the cyclebycycle inductor current not only in steadystate operation, but also in response to transients. To further limit current in the event of an overload condition, the LTM61HV provides foldback current limiting. If the output voltage falls by more than 5%, then the maximum output current is progressively lowered to about one sixth of its full current limit value. The current limit returns to its nominal value once and have returned to their nominal values. SoftStart and Tracking The TRACK/SS pin provides a means to either softstart the regulator or track it to a different power supply. A capacitor on this pin will program the ramp rate of the output voltage. A 1.5µA current source will charge up the external softstart capacitor to 8% of the.6v internal voltage reference plus or minus any margin delta. This will control the ramp of the internal reference and the output voltage. The total softstart time can be calculated as: t SOFTSTART =.8 (.6V ± (MARGIN) ) C SS 1.5µA Output Voltage Tracking Output voltage tracking can be programmed externally using the TRACK/SS pin. The output can be tracked up and down with another regulator. The master regulator s output is divided down with an external resistor divider that is the same as the slave regulator s feedback divider. Figure 5 shows an example of coincident tracking. Ratiometric modes of tracking can be achieved by selecting different resistor values to change the output tracking ratio. The master output must be greater than the slave output for the tracking to work. Figure 6 shows the coincident output tracking characteristics. C IN TRACK CONTROL 1k PLLIN TRACK/SS MPGM RUN MARG MARG1 LTM61HV INTV CC _LCL DRV CC DIFF V OSNS V OSNS SGND f SET R SET.2k Figure 5. Coincident Tracking Schematic MASTER OUTPUT 61HV F5 MASTER OUTPUT R2 6.k R1.2k SLAVE OUTPUT C OUT When the RUN pin falls below 1.5V, then the TRACK/SS pin is reset to allow for proper softstart control when the regulator is enabled again. Current foldback and forced continuous mode are disabled during the softstart process. The softstart function can also be used to control the output ramp up time, so that another regulator can be easily tracked to it. OUTPUT VOLTAGE TIME SLAVE OUTPUT 61HV F6 Figure 6. Coincident Output Tracking Characteristics 1

15 APPLICATIONS INFORMATION Run Enable The RUN pin is used to enable the power module. The pin has an internal 5.1V Zener to ground. The pin can be driven with a logic input not to exceed 5V. The RUN pin can also be used as an undervoltage lock out (UVLO) function by connecting a resistor divider from the input supply to the RUN pin: V UVLO = R1R2 1.5V R2 See Figure 1, Simplified Block Diagram. Power Good The pin is an opendrain pin that can be used to monitor valid output voltage regulation. This pin monitors a ±1% window around the regulation point and tracks with margining. Pin This pin is the external compensation pin. The module has already been internally compensated for most output voltages. Table 2 is provided for most application requirements. LTpowerCAD is available for other control loop optimization. PLLIN The power module has a phaselocked loop comprised of an internal voltage controlled oscillator and a phase detector. This allows the internal top MOSFET turnon to be locked to the rising edge of the external clock. The frequency range is ±3% around the operating frequency of 85kHz. A pulse detection circuit is used to detect a clock on the PLLIN pin to turn on the phaselocked loop. The pulse width of the clock has to be at least ns and at least 2V in amplitude. The PLLIN pin must be driven from a low impedance source such as a logic gate located close to the pin. During the startup of the regulator, the phaselocked loop function is disabled. INTV CC and DRV CC Connection An internal low dropout regulator produces an internal 5V supply that powers the control circuitry and DRV CC for driving the internal power MOSFETs. Therefore, if the system does not have a 5V power rail, the LTM61HV can be directly powered by. The gate driver current through the LDO is about 2mA. The internal LDO power dissipation can be calculated as: P LDO_LOSS = 2mA ( 5V) The LTM61HV also provides the external gate driver voltage pin DRV CC. If there is a 5V rail in the system, it is recommended to connect DRV CC pin to the external 5V rail. This is especially true for higher input voltages. Do not apply more than 6V to the DRV CC pin. A 5V output can be used to power the DRV CC pin with an external circuit as shown in Figure 18. Parallel Operation of the Module The LTM61HV device is an inherently current mode controlled device. Parallel modules will have very good current sharing. This will balance the thermals on the design. The voltage feedback equation changes with the variable N as modules are paralleled: 6.k =.6V N R SET R SET or equivalently: R SET = 6.k N.6V 1 where N is the number of paralleled modules. Figure 21 shows two LTM61HV modules used in a parallel design. An LTM61HV device can be used without the remote sense amplifier. 15

16 APPLICATIONS INFORMATION Thermal Considerations and Output Current Derating The power loss curves in Figures 7 and 8 can be used in coordination with the load current derating curves in Figures 9 to 16 for calculating an approximate θ JA for the module with various heat sinking methods. Thermal models are derived from several temperature measurements at the bench and thermal modeling analysis. Thermal Application Note 13 provides a detailed explanation of the analysis for the thermal models and the derating curves. Tables 3 and provide a summary of the equivalent θ JA for the noted conditions. These equivalent θ JA parameters are correlated to the measured values, and are improved with air flow. The case temperature is maintained at 1 C or below for the derating curves. The maximum case temperature of 1 C is to allow for a rise of about 13 C to 25 C inside the µmodule with a thermal resistance θ JC from junction to case between 6 C/W to 9 C/W. This will maintain the maximum junction temperature inside the µmodule below 125 C. Safety Considerations The LTM61HV modules do not provide isolation from to. There is no internal fuse. If required, a slow blow fuse with a rating twice the maximum input current needs to be provided to protect each unit from catastrophic failure POWER LOSS (W) POWER LOSS (W) LOAD CURRENT (A) LOAD CURRENT (A) HV F7 Figure Power Loss 61HV F8 Figure Power Loss MAXIMUM LOAD CURRENT (A) , 1.5 LFM 5, 1.5 2LFM 5, 1.5 LFM AMBIENT TEMPERATURE ( C) 1 MAXIMUM LOAD CURRENT (A) , 1.5 LFM 5, 1.5 2LFM 5, 1.5 LFM AMBIENT TEMPERATURE ( C) 1 61HV F9 61HV F1 Figure 9. No Heat Sink 5 Figure 1. BGA Heat Sink 5 16

17 APPLICATIONS INFORMATION MAXIMUM LOAD CURRENT (A) , 1.5 LFM 12, 1.5 2LFM 12, 1.5 LFM AMBIENT TEMPERATURE ( C) 1 MAXIMUM LOAD CURRENT (A) , 1.5 LFM 12, 1.5 2LFM 12, 1.5 LFM AMBIENT TEMPERATURE ( C) 1 61HV F11 61HV F12 Figure 11. No Heat Sink 12 Figure 12. BGA Heat Sink MAXIMUM LOAD CURRENT (A) LFM 2LFM LFM 6 8 AMBIENT TEMPERATURE ( C) 1 MAXIMUM LOAD CURRENT (A) LFM 2LFM LFM 6 8 AMBIENT TEMPERATURE ( C) 1 61HV F13 61HV F1 Figure , 3.3, No Heat Sink Figure 1. 12, 3.3, BGA Heat Sink MAXIMUM LOAD CURRENT (A) , 1.5 LFM 2, 1.5 2LFM 2, 1.5 LFM 6 8 AMBIENT TEMPERATURE ( C) 1 MAXIMUM LOAD CURRENT (A) , 1.5 LFM 2, 1.5 2LFM 2, 1.5 LFM 6 8 AMBIENT TEMPERATURE ( C) 1 61HV F15 61HV F16 Figure 15. 2, 1.5, No Heat Sink Figure 16. 2, 1.5, BGA Heat Sink 17

18 APPLICATIONS INFORMATION Table 2. Output Voltage Response Versus Component Matrix* (Refer to Figures 19 and 2), A to 6A Load Step TYPICAL MEASURED VALUES C OUT1 VENDORS PART NUMBER C OUT2 VENDORS PART NUMBER TDK C532X5RJ17MZ (1µF, ) SANYO POSCAP 6TPE33MIL (33µF, ) TAIYO YUDEN JMK32BJ17MUT (1µF, ) SANYO POSCAP 2R5TPE7M9 (7µF, 2.5V) TAIYO YUDEN JMK316BJ226MLT51 (22µF, ) SANYO POSCAP TPE7MCL (7µF, V) (V) C IN (CERAMIC) C IN (BULK) C OUT1 (CERAMIC) C OUT2 (BULK) C C3 (V) DROOP (mv) PEAK TO PEAK (mv) RECOVERY TIME (µs) LOAD STEP (A/µs) µF 35V 15µF 35V 3 22µF 7µF V NONE 7pF µF 35V 15µF 35V 1 1µF 7µF 2.5V NONE 1pF µF 35V 15µF 35V 2 1µF 33µF NONE 22pF µF 35V 15µF 35V 1µF NONE NONE 1pF µF 35V 15µF 35V 3 22µF 7µF V NONE 1pF µF 35V 15µF 35V 1 1µF 7µF 2.5V NONE 1pF µF 35V 15µF 35V 2 1µF 33µF NONE 22pF µF 35V 15µF 35V 1µF NONE NONE 1pF µF 35V 15µF 35V 3 22µF 7µF V NONE 1pF µF 35V 15µF 35V 1 1µF 7µF 2.5V NONE 33pF µF 35V 15µF 35V 2 1µF 33µF NONE 1pF µF 35V 15µF 35V 1µF NONE NONE 1pF µF 35V 15µF 35V 3 22µF 7µF V NONE 1pF µF 35V 15µF 35V 1 1µF 7µF 2.5V NONE 33pF µF 35V 15µF 35V 2 1µF 33µF NONE 1pF µF 35V 15µF 35V 1µF NONE NONE 1pF µF 35V 15µF 35V 3 22µF 7µF V NONE 7pF µF 35V 15µF 35V 1 1µF 7µF 2.5V NONE 1pF µF 35V 15µF 35V 2 1µF 33µF NONE 1pF µF 35V 15µF 35V 1µF NONE NONE 1pF µF 35V 15µF 35V 3 22µF 7µF V NONE 1pF µF 35V 15µF 35V 1 1µF 7µF 2.5V NONE 1pF µF 35V 15µF 35V 2 1µF 33µF NONE 1pF µF 35V 15µF 35V 1µF NONE NONE 1pF µF 35V 15µF 35V 1 1µF 7µF V NONE 1pF µF 35V 15µF 35V 2 1µF 33µF NONE 22pF µF 35V 15µF 35V 3 22µF 7µF V NONE NONE µF 35V 15µF 35V 1µF NONE NONE 1pF µF 35V 15µF 35V 1 1µF 7µF V NONE 1pF µF 35V 15µF 35V 3 22µF 7µF V NONE NONE µF 35V 15µF 35V 2 1µF 33µF NONE 22pF µF 35V 15µF 35V 1µF NONE NONE 22pF µF 35V 15µF 35V 2 1µF 33µF NONE 1pF µF 35V 15µF 35V 1 1µF 7µF V NONE 1pF µF 35V 15µF 35V 3 22µF 7µF V NONE 1pF µF 35V 15µF 35V 1µF NONE NONE 1pF µF 35V 15µF 35V 1 1µF 7µF V NONE 1pF µF 35V 15µF 35V 3 22µF 7µF V NONE 15pF µF 35V 15µF 35V 2 1µF 33µF NONE 1pF µF 35V 15µF 35V 1µF NONE NONE 1pF µF 35V 15µF 35V 1µF NONE NONE 22pF µF 35V 15µF 35V 1µF NONE NONE 22pF * X7R is recommended for extended temperature range. R SET (kω) 18

19 APPLICATIONS INFORMATION Table V Output at 12A DERATING CURVE (V) POWER LOSS CURVE AIR FLOW (LFM) HEAT SINK q JA ( C/W) LGA q JA ( C/W) BGA Figures 9, 11, 15 5, 12, 2 Figure 7 None Figures 9, 11, 15 5, 12, 2 Figure 7 2 None Figures 9, 11, 15 5, 12, 2 Figure 7 None Figures 1, 12, 16 5, 12, 2 Figure 7 BGA Heat Sink Figures 1, 12, 16 5, 12, 2 Figure 7 2 BGA Heat Sink Figures 1, 12, 16 5, 12, 2 Figure 7 BGA Heat Sink Table. 3.3V Output at 12A DERATING CURVE (V) POWER LOSS CURVE AIR FLOW (LFM) HEAT SINK q JA ( C/W) LGA q JA ( C/W) BGA Figure Figure 8 None Figure Figure 8 2 None Figure Figure 8 None Figure 1 12 Figure 8 BGA Heat Sink Figure 1 12 Figure 8 2 BGA Heat Sink Figure 1 12 Figure 8 BGA Heat Sink Heat Sink Manufacturer Aavid Thermalloy Part No: 3752B3G Phone:

20 APPLICATIONS INFORMATION Layout Checklist/Example The high integration of LTM61HV makes the PCB board layout very simple and easy. However, to optimize its electrical and thermal performance, some layout considerations are still necessary. Use large PCB copper areas for high current path, including, and. It helps to minimize the PCB conduction loss and thermal stress. Place high frequency ceramic input and output capacitors next to the, and pins to minimize high frequency noise. Place a dedicated power ground layer underneath the unit. Refer frequency synchronization source to power ground. To minimize the via conduction loss and reduce module thermal stress, use multiple vias for interconnection between top layer and other power layers. Do not put vias directly on pads unless they are capped. Use a separated SGND copper area for components connected to signal pins. Connect the SGND to underneath the unit. Figure 17 gives a good example of the recommended layout. GND 2 C OUT C IN C IN C OUT 61HV F17 Figure 17. Recommended Layout (LGA and BGA PCB Layouts Are Identical with the Exception of Circle Pads for BGA. See Package Description.) SIGNAL GND Frequency Adjustment The LTM61HV is designed to typically operate at 85kHz across most input conditions. The f SET pin is normally left open. The switching frequency has been optimized for maintaining constant output ripple noise over most operating ranges. The 85kHz switching frequency and the ns minimum off time can limit operation at higher duty cycles like 5V to 3.3V, and produce excessive inductor ripple currents for lower duty cycle applications like 28V to 5V. The 5 and 3.3 drop out curves are modified by adding an external resistor on the f SET pin to allow for lower input voltage operation, or higher input voltage operation. Example for 5V Output LTM61HV minimum ontime = 1ns t ON = (( 1pF)/I fset ), for >.8V use.8v LTM61HV minimum offtime = ns t OFF = t t ON, where t = 1/Frequency Duty Cycle = t ON /t or / Equations for setting frequency: I fset = ( /(3 R fset )), for 28V operation, I fset = 238µA, t ON = ((.8 1pF)/I fset ), t ON = 22ns, where the internal R fset is 39.2k. Frequency = ( /( t ON )) = (5V/(28 22ns)) ~ 88kHz. The inductor ripple current begins to get high at the higher input voltages due to a larger voltage across the inductor. This is noted in the Typical Inductor Ripple Current vs Duty Cycle graph (Figure 3) where I L 1A at 2% duty cycle. The inductor ripple current can be lowered at the higher input voltages by adding an external resistor from f SET to ground to increase the switching frequency. A 7A ripple current is chosen, and the total peak current is equal to 1/2 of the 7A ripple current plus the output current. The 5V output current is limited to 8A, so the total peak current is less than 11.5A. This is below the 1A peak specified value. A 1k resistor is placed from f SET to ground, and the parallel combination of 1k and 39.2k equates to 28k. The I fset calculation with 28k and 28V input voltage equals 333µA. This equates to a t ON of 1ns. This will increase the switching frequency from ~88kHz to ~1.2MHz for the 28V to 5V conversion.

21 APPLICATIONS INFORMATION The minimum ontime is above 1ns at 28V input. Since the switching frequency is approximately constant over input and output conditions, then the lower input voltage range is limited to 1V for the 1.2MHz operation due to the ns minimum offtime. Equation: t ON = ( / ) (1/Frequency) equates to a ns ontime, and a ns offtime. The to StepDown Ratio Curve reflects an operating range of 1V to 28V for 1.2MHz operation with a 1k resistor to ground as shown in Figure 18, and an 8V to 16V operation for f SET floating. These modifications are made to provide wider input voltage ranges for the 5V output designs while limiting the inductor ripple current, and maintaining the ns minimum offtime. Example for 3.3V Output LTM61HV minimum ontime = 1ns t ON = (( 1pF)/I fset ) LTM61HV minimum offtime = ns t OFF = t t ON, where t = 1/Frequency Duty Cycle (DC) = t ON /t or / Equations for setting frequency: I fset = ( /(3 R fset )), for 28V operation, I fset = 238µA, t ON = ((3.3 1pF)/I fset ), t ON = 138.7ns, where the internal R fset is 39.2k. Frequency = ( /( t ON )) = (3.3V/( ns)) ~ 85kHz. The minimum ontime and minimum offtime are within specification at 139ns and 137ns. The.5V minimum input for converting 3.3V output will not meet the minimum offtime specification of ns. t ON = 868ns, Frequency = 85kHz, t OFF = 315ns. Solution Lower the switching frequency at lower input voltages to allow for higher duty cycles, and meet the ns minimum offtime at.5v input voltage. The offtime should be about 5ns, which includes a 1ns guard band. The duty cycle for (3.3V/.5V) = ~73%. Frequency = (1 DC)/t OFF or (1.73)/5ns = 5kHz. The switching frequency needs to be lowered to 5kHz at.5v input. t ON = DC/ frequency, or 1.35µs. The f SET pin voltage compliance is 1/3 of, and the I fset current equates to 38µA with the internal 39.2k. The I fset current needs to be 2µA for 5kHz operation. As shown in Figure 19, a resistor can be placed from to f SET to lower the effective I fset current out of the f SET pin to 2µA. The f SET pin is.5v/3 =1.5V and = 3.3V, therefore 13k will source 1µA into the f SET node and lower the I fset current to 2µA. This enables the 5kHz operation and the.5v to 28V input operation for down converting to 3.3V output. The frequency will scale from 5kHz to 1.1 MHz over this input range. This provides for an effective output current of 8A over the input range. 1V TO 28V C2 1µF 35V R2 1k 5% MARGIN R1 392k 1% C1 1µF 35V R 1k PLLIN TRACK/SS MPGM RUN MARG MARG1 LTM61HV INTV CC _LCL DRV CC DIFF V OSNS V OSNS SGND f SET R fset 1k TRACK/SS CONTROL REVIEW TEMPERATURE DERATING CURVE R SET 8.25k C3 1µF SANYO POSCAP 5V 8A 22µF REFER TO TABLE 2 IMPROVE EFFICIENCY FOR 12PUT SOT323 MARGIN CONTROL DUAL CMSSH3C3 61HV F18 Figure 18. 5V at 8A Design Without Differential Amplifier 21

22 APPLICATIONS INFORMATION.5V TO 16V C2 1µF 25V 3 R2 1k R 1k R1 392k PLLIN TRACK/SS MPGM RUN MARG MARG1 LTM61HV INTV CC _LCL DRV CC DIFF V OSNS V OSNS SGND f SET TRACK/SS CONTROL REVIEW TEMPERATURE DERATING CURVE R fset 13k R SET 13.3k 3.3V 1A C3 1µF SANYO POSCAP 22µF 5% MARGIN MARGIN CONTROL 61HV F19 Figure V at 1A Design CLOCK SYNC 22V TO 28V C IN BULK OPT R2 1k C IN 1µF 35V 3 CER R 1k ON/OFF R1 392k 5% MARGIN PLLIN TRACK/SS MPGM RUN MARG MARG1 LTM61HV INTV CC _LCL DRV CC DIFF V OSNS V OSNS SGND f SET C5.1µF REVIEW TEMPERATURE DERATING CURVE MARGIN CONTROL R fset 175k C3 1pF 61HV F2 R SET.2k C OUT1 1µF REFER TO TABLE 2 FOR DIFFERENT OUTPUT VOLTAGE 1.5V 1A C OUT2 7µF Figure 2. Typical 22V to 28V, 1.5V at 1A Design, 5kHz 22

23 APPLICATIONS INFORMATION C1.1µF 118k 1% LTC6981 V OUT1 6 GND OUT2 5 SET MOD 2PHASE OSCILLATOR 6V TO 28V C5* 1µF 35V C2 1µF 35V 2 R2 1k R1 392k R 1k 5% MARGIN CLOCK SYNC PHASE PLLIN TRACK/SS C6 22pF MPGM RUN MARG MARG1 LTM61HV INTV CC _LCL DRV CC DIFF V OSNS V OSNS SGND f SET R SET 6.65k MARGIN CONTROL TRACK/SS CONTROL 6.k N R SET =.6V R SET N = NUMBER OF PHASES C3 22µF C 7µF REFER TO TABLE 2 1pF 3.3V 2A CLOCK SYNC 18 PHASE TRACK/SS CONTROL C7.33µF C8 1µF 35V 2 392k PLLIN TRACK/SS MPGM RUN MARG MARG1 LTM61HV INTV CC _LCL DRV CC DIFF SGND f SET C3 22µF REFER TO TABLE 2 C 7µF 61HV F21 *C5 OPTIONAL TO REDUCE ANY LC RINGING. NOT NEEDED FOR LOW INDUCTANCE PLANE CONNECTION Figure 21. 2Phase Parallel, 3.3V at 2A Design 23

24 TYPICAL APPLICATIONS R1 118k C8.1µF LTC6981 2PHASE OSCILLATOR V OUT1 GND OUT2 PHASE SET MOD 18 PHASE 3.3V 3.3V 6V TO 28V C1 1µF 35V R3 1k R2 392k R 1k RUN INTV CC DRV CC MPGM f SET TRACK/SS C3.15µF SGND LTM61HV PLLIN _LCL DIFF MARG MARG1 R1 13.3k MARGIN CONTROL C2 1µF 1 3.3V C 1A 15µF 3.3V TRACK R16 6.k R k R7 1k C5 1µF 35V R8 1k R6 392k RUN INTV CC DRV CC MPGM f SET TRACK/SS SGND LTM61HV PLLIN _LCL DIFF MARG MARG1 R5 19.1k MARGIN CONTROL C6 1µF 2 2.5V C7 1A 15µF 61HV F22 Figure 22. Dual Outputs (3.3V and 2.5V) with Coincident Tracking R1 182k C8.1µF LTC6981 2PHASE OSCILLATOR V OUT1 GND OUT2 PHASE SET MOD 18 PHASE 3.3V 3.3V 6V TO 28V C1 1µF 35V R3 1k R2 392k R 1k RUN INTV CC DRV CC MPGM f SET TRACK/SS C3.15µF SGND LTM61HV PLLIN _LCL DIFF MARG MARG1 C8 7pF R1 3.1k MARGIN CONTROL C2 1µF 1 1.8V C 1A 22µF 3.3V TRACK R16 6.k R15.2k R7 1k C5 1µF 35V R8 1k R6 392k RUN INTV CC DRV CC MPGM f SET TRACK/SS SGND LTM61HV PLLIN _LCL DIFF MARG MARG1 C9 7pF R5.2k MARGIN CONTROL C6 1µF 2 1.5V C7 1A 22µF 61HV F23 Figure 23. Dual Outputs (1.8V and 1.5V) with Coincident Tracking 2

25 PACKAGE DESCRIPTION Please refer to for the most recent package drawings. PIN A1 CORNER PACKAGE TOP VIEW SUGGESTED PCB LAYOUT TOP VIEW X Y aaa Z SUBSTRATE DETAIL B Øb (118 PLACES) DETAIL A DETAIL A SEE NOTES 3 PACKAGE BOTTOM VIEW NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y1.5M ALL DIMENSIONS ARE IN MILLIMETERS 3 BALL DESIGNATION PER JESD MS28 AND JEP95 DETAILS OF PIN #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE PIN #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE 5. PRIMARY DATUM Z IS SEATING PLANE 6. SOLDER BALL OSITION IS 96.5% Sn/3.% Ag/.5% Cu LTMXXXXXX µmodule ONENT PIN A1 TRAY PIN 1 BEVEL PACKAGE IN TRAY LOADING ORIENTATION BGA REV A PIN 1 aaa Z // bbb Z.63 ±.25 Ø 118x E D BGA Package 118Lead (15mm 15mm 3.2mm) (Reference LTC DWG # Rev A) A A2 A1 ccc Z MOLD CAP b1 ddd eee M Z X Y M Z DETAIL B PACKAGE SIDE VIEW SYMBOL A A1 A2 b b1 G aaa bbb ccc ddd eee D E e F MIN DIMENSIONS NOM MAX TOTAL NUMBER OF BALLS: 118 NOTES Z M L K J H G F E D C B A b F e b e G

26 PACKAGE DESCRIPTION Please refer to for the most recent package drawings. PIN A1 CORNER PACKAGE TOP VIEW SUGGESTED PCB LAYOUT TOP VIEW D X Y aaa Z DETAIL A SEE NOTES 3 PACKAGE BOTTOM VIEW NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y1.5M ALL DIMENSIONS ARE IN MILLIMETERS 3 BALL DESIGNATION PER JESD MS28 AND JEP95 DETAILS OF PIN #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE PIN #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE 5. PRIMARY DATUM Z IS SEATING PLANE LTMXXXXXX µmodule ONENT PIN A1 TRAY PIN 1 BEVEL PACKAGE IN TRAY LOADING ORIENTATION LGA REV A C(.3) PAD 1 aaa Z ±.25 Ø 118x E LGA Package 118Lead (15mm 15mm 2.82mm) (Reference LTC DWG # Rev A) A MOLD CAP SUBSTRATE H2 H1.63 ±.25 SQ. 118x DETAIL B PACKAGE SIDE VIEW DETAIL A M L K J H G F E D C B A b F e b e G bbb Z Z DETAIL B eee S X Y SYMBOL G H1 H2 aaa bbb eee A b D E e F MIN DIMENSIONS NOM MAX TOTAL NUMBER OF LGA PADS: 118 NOTES 26

27 PACKAGE DESCRIPTION Table 5. Pin Assignment (Arranged by Pin Number) PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION A1 B1 C1 D1 E1 F1 A2 B2 C2 D2 E2 F2 A3 B3 C3 D3 E3 F3 A B C D E F A5 B5 C5 D5 E5 F5 A6 B6 C6 D6 E6 F6 A7 INTV CC B7 C7 D7 E7 F7 A8 PLLIN B8 C8 D8 E8 F8 A9 TRACK/SS B9 C9 D9 E9 F9 A1 RUN B1 C1 D1 E1 F1 A11 B11 C11 D11 E11 F11 A12 MPGM B12 f SET C12 MARG D12 MARG1 E12 DRV CC F12 PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION G1 H1 J1 K1 L1 M1 G2 H2 J2 K2 L2 M2 G3 H3 J3 K3 L3 M3 G H J K L M G5 H5 J5 K5 L5 M5 G6 H6 J6 K6 L6 M6 G7 H7 J7 K7 L7 M7 G8 H8 J8 K8 L8 M8 G9 H9 J9 K9 L9 M9 G1 H1 J1 K1 L1 M1 G11 H11 J11 K11 L11 M11 G12 H12 SGND J12 K12 DIFF L12 _LCL M12 27

28 PACKAGE DESCRIPTION Table 6. Pin Assignment (Arranged by Pin Function) A1 A2 A3 A A5 A6 B1 B2 B3 B B5 B6 C1 C2 C3 C C5 C6 PIN NAME D1 D2 D3 D D5 D6 E1 E2 E3 E E5 E6 E7 F1 F2 F3 F F5 F6 F7 F8 F9 G1 G2 G3 G G5 G6 G7 G8 G9 H1 H2 H3 H H5 H6 H7 H8 H9 PIN NAME J1 J2 J3 J J5 J6 J7 J8 J9 J1 K1 K2 K3 K K5 K6 K7 K8 K9 K1 K11 L1 L2 L3 L L5 L6 L7 L8 L9 L1 L11 M1 M2 M3 M M5 M6 M7 M8 M9 M1 M11 PIN NAME PIN NAME A7 A8 A9 A1 A11 A12 INTV CC PLLIN TRACK/SS RUN MPGM B12 f SET C12 MARG D12 MARG1 E12 DRV CC F12 G12 H12 SGND J12 V OSNS K12 DIFF L12 _LCL M12 V OSNS B7 B8 B9 B1 B11 C7 C8 C9 C1 C11 D7 D8 D9 D1 D11 E8 E9 E1 E11 F1 F11 G1 G11 H1 H11 PIN NAME J11 28

29 REVISION HISTORY (Revision history begins at Rev B) REV DATE DESCRIPTION PAGE NUMBER B 3/12 Revised entire data sheet to include the BGA package. 1 3 Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 29

30 PACKAGE PHOTOS 15mm 2.82mm 15mm 3.2mm 15mm 15mm RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTM628 LTM627 LTM611 LTM613 LTM61AHV LTM61A LTM827 LTM832 LTM861 26V, Dual 8A, DC/DC StepDown μmodule Regulator 2V, 15A DC/DC StepDown μmodule Regulator 1.5(MIN), 15A DC/DC StepDown μmodule Regulator 8A EN5522 Class B DC/DC StepDown μmodule Regulator 28V, 12A DC/DC StepDown μmodule Regulator 2V, 12A DC/DC StepDown μmodule Regulator 6V, A DC/DC StepDown μmodule Regulator 36V, 2A EN5522 Class B DC/DC StepDown μmodule Regulator 32V, 2A StepDown μmodule Battery Charger with Programmable Input Current Limit.5V 26.5V,.6V 5V, Remote Sense Amplifier, Internal Temperature Sensing Output, 15mm 15mm.32mm LGA.5V 2V,.6V 5V, PLL Input, Tracking, Remote Sense Amplifier, 15mm 15mm.32mm LGA 1.5V 5.5V,.8V 5V, PLL Input, Remote Sense Amplifier, Tracking, 15mm 15mm.32mm LGA 5V 36V, 3.3V 15V, PLL Input, Tracking and Margining, 15mm 15mm.32mm LGA.5V 28V,.6V 5V, PLL Input, Remote Sense Amplifier, Tracking and Margining, 15mm 15mm 2.82mm LGA or 15mm 15mm 3.2mm BGA.5V 2V,.6V 5V, PLL Input, Remote Sense Amplifier, Tracking and Margining, 15mm 15mm 2.82mm LGA or 15mm 15mm 3.2mm BGA.5V 6V, 2.5V 2V, CLK Input, 15mm 15mm.32mm LGA 3.6V 36V,.8V 1V, Synchronizable, 9mm 15mm 2.82mm LGA or 9mm 15mm 3.2mm BGA Compatible with Single Cell or Dual Cell LiIon or LiPoly Battery Stacks (.1V,.2V, 8.2V, or 8.V),.95V 32V, C/1 or Adjustable Timer Charge Termination, NTC Resistor Monitor Input, 9mm 15mm.32mm LGA 3 Linear Technology Corporation 163 McCarthy Blvd., Milpitas, CA (8) 3219 l FAX: (8) 357 l This product contains technology licensed from Silicon Semiconductor Corporation. LT 312 REV B PRINTED IN USA LINEAR TECHNOLOGY CORPORATION 27