150mA USB LDO Regulators with ±15kV TVS and µp Reset

Transcription

1 9-35; Rev ; / 5mA USB LDO Regulators with ±5k TS General Description The MAX55/MAX5/MAX57 are low-dropout (LDO), micropower linear voltage regulators with an integrated microprocessor (µp) reset circuit for use with USB peripheral devices. Each device is available with a fixed + output voltage and can deliver up to 5mA load current. Each device features ±5k transient voltage suppression (TS) as well as precision.5kω data-line termination resistors for USB digital signals making them ideal for use with USB peripherals. The MAX55/MAX5/MAX57 include an internal reset circuit that enables the USB microcontroller ms after the LDO regulator output voltage reaches regulation. Reset outputs are available in push-pull (active-low or active-high) and open-drain (active-low) options. The MAX55/MAX5/MAX57 are optimized for use with a µf ceramic output capacitor. Each device includes thermal shutdown protection, output short-circuit protection, and output to input reverse leakage protection. These devices also include an active-low manual reset input. The MAX55 features an open-drain reset output, the MAX5 features an active-low push-pull reset output, and the MAX57 features an active-high push-pull reset output. Each device is available in a space-saving -pin µmax package. USB Peripherals Hand-Held Instruments Applications Features Integrated ±5k Transient oltage Suppressors for D+ and D- Data Lines Pin Selectable Internal D+ and D- Termination Resistors (.5kΩ ±5%) Integrated Microprocessor Reset Circuit with ms (min) Timeout Output with ±3% Accuracy 5µA Quiescent Current at Full Load Small µf Output Capacitor Output to Input Reverse Leakage Protection Thermal and Short-Circuit Protection -Pin µmax Package PART Ordering Information TEMP RANGE PIN- PACKAGE MAX55_CUB* C to +7 C µmax MAX5_CUB* C to +7 C µmax RESET OUTPUT Op en- D r ai n Low Push-Pull Low Push-Pull MAX57_CUB* C to +7 C µmax High *Insert A for a 7.5% reset threshold and B for a.5% reset threshold. MAX55/MAX5/MAX57 Typical Operating Circuit Pin Configuration USB PORT BUS D+ D- GND C IN µf CERAMIC SELR ENR 5 IN OUT C OUT µf USB CONTROLLER CC MAX55 MAX5 MAX57 D+ RESET RST D- (RESET) MR D+ D- GND GND TOP IEW IN D+ GND D- SELR 3 5 MAX55 MAX5 MAX OUT GND MR RESET/(RESET) ENR 7Ω µmax 7Ω () FOR MAX57 ONLY. ( ) FOR MAX57 ONLY Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at , or visit Maxim s website at

2 5mA USB LDO Regulators with ±5k TS MAX55/MAX5/MAX57 ABSOLUTE MAXIMUM RATINGS IN to GND to + D+, D- to GND to + MR to GND to ( +.3) RESET, RESET to GND, Push-Pull to ( +.3) RESET to GND, Open-Drain to + OUT, SELR, ENR to GND to + Maximum Current to Any Pin (except IN, OUT, D+, D-)...± ma Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS Short-Circuit Duration...Indefinite Continuous Power Dissipation (T A = +7 C) -Pin µmax (derate 5.mW/ C above +7 C)...mW Thermal Resistance (θ JA )...8 C/W Operating Temperature Range... C to +7 C Junction Temperature...+5 C Storage Temperature Range...-5 C to +5 C Lead Temperature (soldering, s)...+3 C ( IN = +5, I OUT =, C OUT =.µf, T A = C to +7 C, unless otherwise noted. Typical specifications are at T A = +5 C.) (Note ) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Input oltage Range IN I LOAD = ma. 5.5 Supply Current I GND Measured at GND 5 5 µa REGULATOR Guaranteed Output Current I OUT 5 ma Output oltage IN =. to 5.5, I OUT = to ma I LOAD = ma 3 Dropout oltage (Note ) DO I LOAD = 5mA 3 Output Current Limit IN = ma Input Reverse Leakage Current IN =, = 5.5 µa Startup Response Time Rising edge of IN to R L = 5Ω Thermal Shutdown Temperature T JSHDN Thermal Shutdown Hysteresis T JSHD N RESET CIRCUIT m 5 µs MAX5_ACUB Reset Threshold (Note 3) TH MAX5_BCUB o C o C Reset Timeout Period t RP 3 ms to Reset Delay t RD 75 µs IL. x MR Input oltage.8 x IH MR Minimum Input Pulse Width µs MR Glitch Rejection ns MR to Reset Delay 5 ns MR Pullup Resistance to OUT 5 5 kω SELR Input oltage IL Connects R TERM to D- IH Connects R TERM to D+.8 x. x

3 5mA USB LDO Regulators with ±5k TS ELECTRICAL CHARACTERISTICS (continued) ( IN = +5, I OUT =, C OUT =.µf, T A = C to +7 C, unless otherwise noted. Typical specifications are at T A = +5 C.) (Note ) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS SELR Input Current SELR = GND or OUT - µa ENR Input oltage IL R TERM enabled.8 x IH R TERM disabled ENR Input Current ENR = GND or OUT - µa Open-Drain RESET Output Low oltage (MAX55) Open-Drain Reset Output Leakage Current (MAX55) Push-Pull RESET Output oltage (MAX5) Push-Pull RESET Output oltage (MAX57). x >., I SINK = 5µA, reset asserted.3 OL >.7, I SINK = 3.mA, reset asserted. I LKG Reset not asserted -.. µa OL OH OL OH =., I SINK = 5µA, reset asserted.3 OUT > TH(MIN), I SINK = 3.mA, reset asserted > TH(MAX), I SOURCE = 5µA, reset not asserted > TH(MAX), I SINK = 3.mA, reset not asserted =., I SOURCE = 5µA, reset asserted USB OPTIONS AND TRANSIENT SUPPRESSION D+/D- R TERM Impedance ENR = GND, SELR = GND or OUT Ω D+/D- Input Leakage Current ENR = = - µa D+ to D- Capacitance D+, D- Capacitance to GND.8 x.8 x MHz, mp-p signal ENR = OUT 5.5 applied at D+ and D-, = Unpowered MHz, mp-p signal ENR = OUT applied at D+ and D-, = Unpowered 7 ESD Trigger oltage d/dt < /ns, D+ or D- > Surge Trigger oltage d/dt < /µs, D+ or D- > Clamping oltage A, pulse width = ns to µs Surge Current, pulse width = ns to µs ± A D+/D- to GND ESD Human Body Model MIL-STD-883 ± Contact Discharge IEC-- (EN--) ±8 Air Discharge IEC-- (EN--) ±5.. pf pf k MAX55/MAX5/MAX57 Note : All devices are % tested at T A = +5 C. Limits over temperature are guaranteed by characterization and not production tested. Note : Dropout voltage is defined as IN - when is % below the value of for IN = +. Note 3: Specification is guaranteed to ±σ limit. 3

4 5mA USB LDO Regulators with ±5k TS MAX55/MAX5/MAX57 ( IN = +5, I OUT =, C OUT =.µf, unless otherwise noted.) GROUND-PIN CURRENT (µa) GROUND-PIN CURRENT vs. SUPPLY OLTAGE I OUT = 5mA I OUT = SUPPLY OLTAGE () PSRR (db) MAX55-7 toc PULSE DURATION (µs) POWER-SUPPLY REJECTION RATIO vs. FREQUENCY -55 C OUT = µf -.. FREQUENCY (khz) MAX55-7 toc MAXIMUM PULSE DURATION vs. RESET THRESHOLD OERDRIE RESET OCCURS ABOE THIS LINE RESET THRESHOLD OERDRIE, TH - (m) Typical Operating Characteristics OUTPUT OLTAGE () MAX55-7 toc DROPOUT OLTAGE (m) DROPOUT OLTAGE vs. LOAD CURRENT LOAD CURRENT (ma) OUTPUT OLTAGE vs. SUPPLY OLTAGE I OUT = I OUT = 5mA SUPPLY OLTAGE () MAX55-7 toc5 MAX55-7 toc3 5 5 REGION OF STABLE C OUT ESR vs. LOAD CURRENT MAX55-7 toc OUTPUT NOISE MAX55-7 toc7 COUT ESR (Ω) 75 5 C OUT = µf C OUT =.7µF OUT m/div 5 STABLE REGION BELOW THE CURE LOAD CURRENT (ma) µs/div

5 5mA USB LDO Regulators with ±5k TS Typical Operating Characteristics (continued) ( IN = +5, I OUT =, C OUT =.µf, unless otherwise noted.) IN 5/div 5/div RESET 5/div TURN-ON/TURN-OFF RESPONSE MAX55-7 toc8 I LOAD ma 5m/div 5m/div 5ms/div R L = kω IN 5/div /div LOAD-TRANSIENT RESPONSE MAX55-7 tocb C OUT = µf C OUT =.7µF STARTUP RESPONSE ms/div MAX55-7 toc9 R L = kω 5.5 IN m/div.75 5m/div ma I LOAD 5m/div 5m/div LOAD-TRANSIENT RESPONSE.ms/div LINE-TRANSIENT RESPONSE MAX55-7 toca I OUT = ma C OUT = IµF MAX55-7 toca C OUT =.µf C OUT =.µf MAX55/MAX5/MAX57.ms/div µs/div 5.5 LINE-TRANSIENT RESPONSE MAX55-7 tocb TS PEAK POWER vs. PULSE WIDTH MAX55-7 toc IN m/div.75 5m/div PEAK POWER (W) µs/div I OUT = ma C OUT = µf D+ OR D- WITH RESPECT TO GROUND.. PULSE WIDTH (µs) 5

6 5mA USB LDO Regulators with ±5k TS MAX55/MAX5/MAX57 PIN NAME DESCRIPTION IN D+ 3, 9 GND D- 5 SELR ENR 7 RESET RESET 8 MR Pin Description Regulator Input. Supply voltage ranges from +. to Bypass with a µf ceramic capacitor to ground. D+ ESD/Transient Suppression Input. Connect directly to USB port D+ data input. SELR high and ENR low connects D+ to OUT through a.5kω resistor. Ground. This pin also functions as a heatsink. Solder to large pads or the circuit board ground plane to maximize thermal dissipation. D- ESD/Transient Suppression Input. Connect directly to USB port D- data input. SELR low and ENR low connects D- to OUT through a.5kω resistor. USB Full-Speed/Low-Speed Termination Resistor Select. Logic high connects the termination resistor to D+ for full-speed peripherals. Logic low connects the termination resistor to D- for lowspeed peripherals. An internal.5kω resistor connects to OUT when ENR is low. USB Termination Resistor Enable. When reset is not asserted, ENR low enables the termination resistor connection. ENR high or a reset disables the termination resistor connection. Active-Low Reset Output. RESET remains low while is below the reset threshold or while MR is held low. RESET remains low for the duration of the reset timeout period after the reset conditions are terminated. (MAX55/MAX5 ONLY) Active-High Reset Output. RESET remains high while is below the reset threshold or while MR is held low. RESET remains high for the duration of the reset timeout period after the reset conditions are terminated. (MAX57 ONLY) Active-Low Manual Reset Input. A logic low forces a reset. Reset remains asserted for the duration of the reset timeout period after MR transitions from low to high. Leave unconnected or connect to OUT if not used. MR has an internal pullup resistor of 5kΩ to OUT. OUT oltage Regulator Output. Fixed +. Sources up to 5mA. Bypass with a µf (min) capacitor for full rated performance.

7 5mA USB LDO Regulators with ±5k TS IN. to 5.5 GND D+ REERSE CURRENT PROTECTION OUT MAX55 MAX5 MAX57 REF TS.3 CURRENT LIMIT PROTECTION FULL SPEED.5kΩ LDO ERROR AMP THERMAL PROTECTION RESET COMPARATOR USB TERMINATION DRIER ESD/ SURGE PROTECTION LOW SPEED.5kΩ ms RESET TIMEOUT TS 5kΩ OUT OUT RESET/(RESET) MR D- MAX55/MAX5/MAX57 SELR ENR GND ( ) FOR MAX57 ONLY. Figure. Functional Diagram Detailed Description The MAX55/MAX5/MAX57 are USB application-specific, low-dropout, low-quiescent current linear regulators with an integrated µp reset circuit (see Figure ). The devices drive loads up to 5mA and are available with a fixed output voltage of +. Features include.5kω D+ and D- termination resistors and ±5k transient voltage suppression (TS) in accordance with IEC-- (EN--) Air Discharge Method and MILSTD883C- Method 35- making the MAX55/MAX5/MAX57 ideal for use with USB peripheral devices. The internal reset circuit monitors the regulator output voltage and asserts a reset signal when the output is typically -7.5% out of regulation for MAX5_ACUB and -.5% out of regulation for MAX5_BCUB. Reset Circuit The reset supervisor circuit is fully integrated in the MAX55/MAX5/MAX57, and uses the same reference voltage as the regulator. Two supply tolerance reset thresholds, typically -7.5% and -.5%, are available for each type of device. 7.5% reset: Reset does not assert until the regulator output voltage is at least -3.% out of tolerance and always asserts before the regulator output voltage is -.5% out of tolerance..5% reset: Reset does not assert until the regulator output voltage is at least -8.8% out of tolerance and always asserts before the regulator output voltage is -.7% out of tolerance. Reset Output The MAX55/MAX5/MAX57 µp supervisory circuits assert a reset during power-up, power-down, and 7

8 5mA USB LDO Regulators with ±5k TS MAX55/MAX5/MAX57 brownout conditions. Reset is guaranteed to be logic high or low depending on the device chosen (see Ordering Information). RESET or RESET asserts when is below the reset threshold and remains asserted for at least ms minimum after rises above the reset threshold. RESET or RESET also asserts when MR is pulled low. SELR and ENR When reset is not asserted a logic high to SELR connects a.5kω termination resistor from D+ to OUT for full speed USB peripherals and a logic low connects a.5kω termination resistor from D- to OUT for low-speed peripherals. Logic low on ENR enables the selected termination resistor connection and logic high disables the selected termination resistor connection. An asserted reset always disconnects the termination resistors. D+ and D- D+ and D- include transient voltage suppressors rated at ±5k (see USB ±5k Transient oltage Suppression section). The proprietary TS shunt circuit passes no data through the MAX55/MAX5/MAX57, thereby eliminating delays associated with series protection circuits. D+ and D- have only µa of leakage current and a typical input capacitance of pf at MHz. Manual Reset Input Many µp-based products require manual reset capability, allowing the operator, a test technician, or external logic circuitry to initiate a reset. A logic low on MR asserts a reset while the regulator output voltage is still within tolerance. Reset remains asserted while MR is low and for the reset timeout period (ms minimum) after MR returns high. The MR input has an internal pullup of 5kΩ (typ) to OUT. Drive this input with TTL/CMOS logic levels or with open-drain/collector outputs. Connect a normally open momentary switch from MR to GND to create a manual reset function; external debounce circuitry is not required. If MR is driven from long cables or the device is used in a noisy environment, connect a.µf capacitor from MR to GND to provide additional noise immunity. For proper operation, ensure that the voltage on MR is not greater than a diode drop above. Output to Input Reverse Leakage Protection An internal circuit monitors the input and output voltages. When the output voltage is greater than the input voltage, the internal pass transistor and parasitic diodes turn off, and OUT powers the device. There is no leakage path from OUT to IN. Therefore, the output can be powered from an auxiliary supply such as a backup battery without any need for additional blocking diodes. Current Limit The MAX55/MAX5/MAX57 include a current limiter that monitors and controls the pass transistor s gate voltage, limiting the output current to 35mA (typ). For design purposes, consider the current limit to be ma (min) to ma (max). The output can be shorted to ground for an indefinite period without damaging the part. Thermal Protection When the junction temperature exceeds T J = + C, an internal thermal sensor signals the shutdown logic, turning off the pass transistor and allowing the IC to cool. The thermal sensor turns the pass transistor on again after the IC s junction temperature decreases by C, resulting in a pulsed output during continuous thermal overload conditions. Thermal overload protection is designed to protect the MAX55/MAX5/ MAX57 in the event of fault conditions. For continuous operation, do not exceed the absolute maximum junction temperature rating of T J = +5 C. Operating Region and Power Dissipation The MAX55/MAX5/MAX57 s maximum power dissipation depends on the thermal resistance of the case and circuit board, the temperature difference between the die junction and the ambient air, and the rate of airflow. The power dissipation across the device is P = I OUT ( IN - ). The maximum power dissipation is: P MAX = (T J - T A ) / (Θ JA ) where T J - T A is the temperature difference between the die junction and the surrounding air, Θ JA is the thermal resistance of the package from junction to ambient. The MAX55/MAX5/MAX57 s ground pin (GND) performs the dual function of providing an electrical connection to the system ground and channeling heat away. Connect GND to the system ground using a large pad or ground plane. For optimum performance, minimize trace inductance to D+, D-, and GND. Applications Information Capacitor Selection and Regulator Stability For stable operation over the full temperature range and with load currents up to 5mA, use a µf (min) output capacitor. To reduce noise and improve load transient response, stability, and power-supply rejection, use large output capacitor values such as µf. 8

9 5mA USB LDO Regulators with ±5k TS Note that some ceramic dielectrics exhibit large capacitance and ESR variation with temperature. With dielectrics such as Z5U and Y5, it may be necessary to use.µf or more to ensure stability at temperatures below - C. With X7R or X5R dielectrics, µf should be sufficient at all operating temperatures. Also, for high-esr tantalum capacitors,.µf or more may be needed to maintain stability. A graph of the Region of Stable C OUT ESR vs. Load Current is shown in the Typical Operating Characteristics. To improve power-supply rejection and transient response use a µf capacitor between IN and GND. Negative-Going OUT Transients These devices are relatively immune to short-duration, negative-going transients. The Typical Operating Characteristics section shows a graph of the Maximum Pulse Duration vs. Reset Threshold Overdrive for which reset is not asserted. The graph was produced using negative going output transients starting at and ending below the reset threshold by the magnitude indicated (Reset Threshold Overdrive). The graph shows the maximum pulse width that a negative going transient can typically have without triggering a reset pulse. As the amplitude of the transient increases (i.e., goes further below the reset threshold), the maximum allowable pulse width decreases. Typically, a transient that goes only m below the reset threshold and lasts for 75µs will not trigger a reset pulse. USB ±5k Transient oltage Suppression The universal serial bus (USB) simplifies interconnectivity between peripheral devices and personal computers. USBs offer high-speed data communication rates (up to Mbps) using only two lines (D+ and D-). CMOS based USB peripherals that utilize deep submicron technologies are more susceptible to electrostatic discharge (ESD) failure due to shorter channel lengths, shallower drain/source junctions, and lightly doped drain structures. The MAX55/MAX5/MAX57 incorporate a proprietary transient voltage suppression (TS) circuit for use with submicron devices. The TS design complies with IEC--- level (EN--) ±5k Air Discharge and ±8k Contact Discharge as well as MIL STD 883C-Method 35- level 3. The TS circuit handles up to A of surge current. The TS/ESD structure is directly coupled to the output of the LDO regulator. TS Surge Test Information Figure shows the test circuit used to generate the 8/µs short circuit waveform of Figure 3. Figures, 5, and show the actual surge current I/ characteristics with various capacitive loads. ESD Performance The MAX55/MAX5/MAX57 are characterized to the following limits on D+, D-, and IN: ±5k using the Human Body Model ±8k using the Contact Discharge Method specified in IEC -- (EN--) ±5k using the Air-Gap Discharge Method specified in IEC -- (EN--). Note that in order to achieve the above ESD levels on IN, a ceramic µf ceramic capacitor should be connected from IN to GND. ESD Test Conditions ESD performance depends on several conditions. Contact Maxim for a reliability report that documents test setup, methodology, and results. Human Body Model Figure 7 shows the Human Body Model, and Figure 8 shows the current waveform it generates when discharged into low impedance. This model consists of a pf capacitor charged to the ESD voltage of interest, which is then discharged into the test device through a.5kω resistor. ESD Transmission Line Pulsing Figure 9 shows the test circuit used for transmission line pulsing conditions. The ns pulsewidth has a rise time of ns. Figure shows the Current vs. oltage characteristics for various output capacitance values. MAX55/MAX5/MAX57 9

10 5mA USB LDO Regulators with ±5k TS MAX55/MAX5/MAX57 kω JENNINGS RELAY RF3D-S HIGH OLTAGE µf k 8µH Figure. Surge Current Test Circut CURRENT (A) 8 C OUT = D+ OR D- TO GND 8/µs PULSE WIDTH Ω D+/D- TS DEICE UNDER TEST.µF LEAKAGE RELAY AMPERES I P % 5% CURRENT (A) 8 8µs t µs t 8/µs PULSE WIDTH C OUT = µf D+ OR D- TO GND TIME Figure 3. Test Circuit Surge Current Waveform (Short-Circuit Load) 8 8 OLTAGE () Figure. Surge Current I/ Characteristic (C OUT = ) 8 8 OLTAGE () Figure 5. Surge Current I/ Characteristic (C OUT = µf) 8/µs PULSE WIDTH CURRENT (A) 8 C OUT = µf D+ OR D- TO GND 8 8 OLTAGE () Figure. Surge Current I/ Characteristic (C OUT = µf)

11 5mA USB LDO Regulators with ±5k TS HIGH- OLTAGE DC SOURCE IN R C MΩ CHARGE-CURRENT LIMIT RESISTOR Cs pf MΩ R D 5Ω DISCHARGE RESISTANCE STORAGE CAPACITOR Figure 7. Human Body ESD Test Model DEICE SCOPE L Zo = 5Ω DEICE UNDER TEST R L AMPERES I P % 9% 3.8% % CURRENT (A) t RL D+ OR D- TO GND C OUT = ns PULSE WIDTH TIME t DL CURRENT WAEFORM Figure 8. Human Body Model Current Waveform Ir PEAK-TO-PEAK RINGING (NOT DRAWN TO SCALE) MAX55/MAX5/MAX57 8 OLTAGE () Figure. Transmission Line Pulsing I/ Characteristic (C OUT = ) t RISE = ns 7 t pw = ns CURRENT (A) 5 3 D+ OR D- TO GND C OUT = µf ns PULSE WIDTH Figure 9. Transmission Line Pulsing Setup for ESD I/ Characteristics 8 OLTAGE () Figure. Transmission Line Pulsing I/ Characteristic (C OUT = µf)

12 5mA USB LDO Regulators with ±5k TS MAX55/MAX5/MAX57 CURRENT (A) D+ OR D- TO GND C OUT = µf ns PULSE WIDTH 8 OLTAGE () Figure. Transmission Line Pulsing I/ Characteristic (C OUT = µf) TRANSISTOR COUNT: 89 PROCESS: BiCMOS Chip Information

13 5mA USB LDO Regulators with ±5k TS Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to A e ÿ.5±..±. TOP IEW D D b FRONT IEW A X S H A GAGE PLANE α BOTTOM IEW E E SIDE IEW L L DIM A A MIN -. MAX.3. MIN -.5 MAX..5 A D D E E H L L b e c S α c INCHES MILLIMETERS REF.9 REF BSC.5 BSC REF.98 REF LUMAX.EPS MAX55/MAX5/MAX57 PROPRIETARY INFORMATION TITLE: PACKAGE OUTLINE, L umax/usop APPROAL DOCUMENT CONTROL NO. RE. - I Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, San Gabriel Drive, Sunnyvale, CA Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.