LD7531 6/25/2008. Green-Mode PWM Controller with Frequency Trembling and Integrated Protections. Features. General Description.

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1 REV: 00 LD7531 6/25/2008 Green-Mode PWM Controller with Frequency Trembling and Integrated Protections General Description The LD7531 is built-in with several functions, protection and EMI-improved solution in a SOT-26/ DIP-8 package. It takes less components counts or circuit space, especially ideal for those total solutions of low cost. The implemented functions include low startup current, green-mode power-saving operation, leading-edge blanking of the current sensing and internal slope compensation. And the LD7531 features more protections like OLP (Over Load Protection) and OVP (Over Voltage Protection) to prevent the circuit damage from the abnormal conditions. Furthermore, the frequency trembling function is to reduce the noise level and thus helps the power circuit designers to easily deal with the EMI filter design by using minimum component cost and developing time. Features High-Voltage CMOS Process with Excellent ESD protection Very Low Startup Current (<20μA) Current Mode Control Non-audible-noise Green Mode Control UVLO (Under Voltage Lockout) LEB (Leading-Edge Blanking) on CS Pin Programmable Switching Frequency Internal Trembling (±4KHz) Internal Slope Compensation OVP (Over Voltage Protection) on Vcc Pin OLP (Over Load Protection) 300mA Driving Capability Applications Switching AC/DC Adaptor and Battery Charger Open Frame Switching Power Supply Typical Application AC input EMI Filter VCC 32V 16.0V /10.0V LD7531 UVLO OUT RT 100K Ohm COMP FM OSC Divider Control Logic photocoupler CS TL431 GND 1

2 Pin Configuration DIP-8 (TOP VIEW) SOT-26 (TOP VIEW) GND COMP NC RT OUT VCC CS TOP MARK YYWW## WP 31 Y GND COMP RT OUT VCC NC CS YY, Y : Year code (D: 2004, E: ) WW, W: Week code P : LD75.. (Product family code) ## : Production code Y The PB free package is identified in embossed font while green package in regular print Ordering Information Part number Package TOP MARK Shipping LD7531 GL SOT-26 Green Package YWP/ /tape & reel LD7531 GN DIP-8 Green Package LD7531GN 3600 /tube /Carton LD7531 PL SOT-26 PB Free YWP/ /tape & reel LD7531 PN DIP-8 PB Free LD7531PN 3600 /tube /Carton Note: The LD7531 is ROHS compliant/ Green package. Pin Descriptions PIN (DIP-8) PIN (SOT-26) NAME 8 1 GND Ground 7 2 COMP FUNCTION Voltage feedback pin (same as the COMP pin in UC384X), By connecting a photo-coupler to close the control loop and achieve the regulation. This pin is to program the switching frequency. By connecting a resistor 5 3 RT to ground to set the switching frequency. 4 4 CS Current sense pin, connect to sense the MOSFET current 2 5 VCC Supply voltage pin 1 6 OUT Gate drive output to drive the external MOSFET 2

3 Block Diagram 3

4 Absolute Maximum Ratings Supply Voltage VCC 30V COMP, RT, CS -0.3 ~7V OUT -0.3 ~Vcc+0.3 Maximum Junction Temperature 150 C Operating Ambient Temperature -40 C to 85 C Operating Junction Temperature -40 C to 125 C Storage Temperature Range -65 C to 150 C Package Thermal Resistance (SOT-26) 250 C/W Package Thermal Resistance (DIP-8) 100 C/W Power Dissipation (SOT-26, at Ambient Temperature = 85 C) 250mW Power Dissipation (DIP-8, at Ambient Temperature = 85 C) 650mW Lead temperature (Soldering, 10sec) 260 C ESD Voltage Protection, Human Body Model 3.0 KV ESD Voltage Protection, Machine Model 300 V Gate Output Current 300mA Caution: Stresses beyond the ratings specified in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Recommended Operating Conditions Item Min. Max. Unit Supply Voltage Vcc V RT Value KΩ Start-up resistor Value MΩ 4

5 Electrical Characteristics (T A = +25 o C unless otherwise stated, V CC =15.0V) PARAMETER CONDITIONS MIN TYP MAX UNITS Supply Voltage (Vcc Pin) Startup Current μa V COMP =0V ma Operating Current V COMP =3V 3.0 ma (with 1nF load on OUT pin) Protection tripped (OLP) 0.45 ma Protection tripped (OVP) 0.5 ma UVLO (off) V UVLO (on) V OVP Level V Voltage Feedback (Comp Pin) Short Circuit Current V COMP =0V ma Open Loop Voltage COMP pin open 5.9 V Green Mode Threshold VCOMP 2.35 V Current Sensing (CS Pin) Maximum Input Voltage, Vcs(off) V Leading Edge Blanking Time 190 ns Input impedance 1 MΩ Delay to Output 100 ns Oscillator for Switching Frequency Frequency RT=100KΩ KHz Green Mode Frequency Fs=65kHz 21 KHz Trembling Frequency ± 4.0 KHz Temp. Stability (-40 C ~105 C) 5 % Voltage Stability (VCC=11V-25V) 1 % Gate Drive Output (OUT Pin) Output Low Level VCC=15V, Io=20mA 1 V Output High Level VCC=15V, Io=20mA 8 V Rising Time Load Capacitance=1000pF ns Falling Time Load Capacitance=1000pF ns OLP (Over Load Protection) OLP Trip Level Vcomp (OLP) 5.0 V OLP Delay Time Fs=65kHz 50 ms * RT value is in proportion to OLP delay time. 5

6 Typical Performance Characteristics UVLO (on) (V) UVLO (off) (V) Fig. 1 UVLO (on) vs. Temperature Fig. 2 UVLO (off ) vs. Temperature Frequency (KHz) Green Mode Frequency (KHz) Fig. 3 Frequency vs. Temperature Fig. 4 Green Mode Frequency vs. Temperature 25 Frequency (KHz) Green Mode Frequency (KHz) Vcc (V) Vcc (V) Fig. 5 Frequency vs. Vcc Fig. 6 Green Mode Frequency vs. Vcc 6

7 Max Duty (%) VCS (off) (V) Fig. 7 Max Duty vs. Temperature s te Fig. 8 V CS (off) vs. Temperature Istartup (μa) 9 6 VCC OVP (V) Fig. 9 Startup Current (Istartup) vs. Temperature Fig. 10 VCC OVP vs. Temperature VCOMP (V) OLP (V) Fig. 11 V COMP open loop voltage vs. Temperature Fig. 12 OLP-Trip Level vs. Temperature 7

8 Application Information Operation Overview The LD7531 meets the green-power requirement and is intended for the use in those modern switching power suppliers and adaptors which demand higher power efficiency and power-saving. It integrated more functions to reduce the external components counts and the size. Its major features are described as below. Under Voltage Lockout (UVLO) An UVLO comparator is implemented in it to detect the voltage on the VCC pin. It would assure the supply voltage enough to turn on the LD7531 PWM controller and further to drive the power MOSFET. As shown in Fig. 13, a hysteresis is built in to prevent the shutdown from the voltage dip during startup. The turn-on and turn-off threshold level are set at 16.0V and 10.0V, respectively. further to deliver the gate drive signal, the supply current is provided from the auxiliary winding of the transformer. Lower startup current requirement on the PWM controller will help to increase the value of R1 and then reduce the power consumption on R1. By using CMOS process and the special circuit design, the maximum startup current of LD7531 is only 20μA. If a higher resistance value of the R1 is chosen, it usually takes more time to start up. To carefully select the value of R1 and C1 will optimize the power consumption and startup time. Vcc UVLO(on) UVLO(off) t I(Vcc) operating current (~ ma) startup current (~ua) Fig. 13 Startup Current and Startup Circuit The typical startup circuit to generate the LD7531 Vcc is shown in Fig. 14. During the startup transient, the Vcc is lower than the UVLO threshold thus there is no gate pulse produced from LD7531 to drive power MOSFET. Therefore, the current through R1 will provide the startup current and to charge the capacitor C1. Whenever the Vcc voltage is high enough to turn on the LD7531 and t Fig. 14 Current Sensing and Leading-edge Blanking The typical current mode of PWM controller feedbacks both current signal and voltage signal to close the control loop and achieve regulation. As shown in Fig. 15, the LD7531 detects the primary MOSFET current from the CS pin, which is not only for the peak current mode control but also for the pulse-by-pulse current limit. The maximum voltage threshold of the current sensing pin is set at 0.85V. 8

9 From above, the MOSFET peak current can be obtained from below. 0.85V I PEAK(MAX) = RS Vin Cbulk R1 D1 C1 Voltage Feedback Loop The voltage feedback signal is provided from the TL431 at the secondary side through the photo-coupler to the COMP pin of the LD7531. Similar to UC3842, the LD7531 would carry 2 diodes voltage offset at the stage to feed the voltage divider at the ratio of 1/3, that is, 1 V ( PWM ) = (VCOMP 2VF ) COMPARATOR 3 A pull-high resistor is embedded internally and can be eliminated externally. VCC LD7531 OUT Comp GND CS Rs Fig. 15 A 190nS leading-edge blanking (LEB) time is included in the input of CS pin to prevent the false-trigger from the current spike. In the low power application, if the total pulse width of the turn-on spikes is less than 190nS and the negative spike on the CS pin doesn t exceed -0.3V, it could eliminated the R-C filter (as shown in the figure16). However, the total pulse width of the turn-on spike is decided by the output power, circuit design and PCB layout. It is strongly recommended to adopt a smaller R-C filter (as shown in figure 17) for higher power application to avoid the CS pin being damaged by the negative turn-on spike. Fig. 16 Output Stage and Maximum Duty-Cycle An output stage of a CMOS buffer, with typical 500mA driving capability, is incorporated to drive a power MOSFET directly. And the maximum duty-cycle of LD7531 is limited to 75% to avoid the transformer saturation. 9

10 Dual-Oscillator Green-Mode Operation There are many different topologies has been implemented in different chips for the green-mode or power saving requirements such as burst-mode control, skipping-cycle mode, variable off-time control etc. The basic operation theory of all these approaches intended to reduce the switching cycles under light-load or no-load condition either by skipping some switching pulses or reduce the switching frequency. By using this dual-oscillator control, the green-mode frequency can be well controlled and further to avoid the generation of audible noise. Fig. 17 Oscillator and Switching Frequency The switching frequency of LD7531 is programmed as an external resistor on RT to provide the optimized operations by considering the EMI performance, thermal treatment, component sizes and transformer design. Internal Slope Compensation In the conventional application, the problem of the stability is a critical issue for current mode controlling, when it operates in higher than 50% of the duty-cycle. As UC384X, It takes slope compensation from injecting the ramp signal of the RT/CT pin through a coupling capacitor. It therefore requires no extra design for the LD7531 since it has integrated it already. OVP (Over Voltage Protection) on Vcc The V GS ratings of the nowadays power MOSFETs are often limited up to max. 30V. To prevent the V GS from the fault condition, LD7531 is implemented an OVP function on Vcc. Whenever the Vcc voltage is higher than the OVP threshold voltage, the output gate drive circuit will be shutdown simultaneously thus to stop the switching of the power MOSFET until the next UVLO(on). The Vcc OVP function in LD7531 is an auto-recovery type protection. If the OVP condition, usually caused by the feedback loop opened, is not released, the Vcc will tripped the OVP level again and re-shutdown the output. The Vcc is working as a hiccup mode. The Figure 18 shows its operation. On the other hand, if the OVP condition is removed, the Vcc level will get back to normal level and the output will automatically return to the normal operation. On/Off Control The LD7531 can be turned off by pulling COMP pin lower than 1.2V. The gate output pin of the LD7531 will be disabled immediately under such condition. The off-mode can be released when the pull-low signal is removed. 10

11 VCC UVLO(on) UVLO(off) COMP OLP UVLO(off) OLP Reset OLP delay time t 5.0V Fig. 18 Over Load Protection (OLP) To protect the circuit from being damaged under over load condition or short condition, a smart OLP function is implemented in the LD7531. The Figure 19 shows the waveforms of the OLP operation. In this case, the feedback system will force the voltage loop proceed toward the saturation and then pull up the voltage on COMP pin (V COMP ). Whenever the V COMP trips up to the OLP threshold 5V and stays longer than the OLP delay time, the protection will activate and then turn off the gate output to stop the switching of power circuit. The OLP delay time is to prevent the false trigger from the power-on and turn-off transient. Typically the OLP delay time will be around 50mS. By such protection mechanism, the average input power can be reduced to very low level so that the component temperature and stress can be controlled within the safe operating area. OLP trip Level t OUT Switching Non-Switching Switching t Fig. 19 Fault Protection There are several critical protections were integrated in the LD7531 to prevent the power supply or adapter had being damaged. Those damages usually come from open or short condition on the pins of LD7531. Under the conditions listed below, the gate output will turn off immediately to protect the power circuit RT pin short to ground 2. RT pin floating 3. CS pin floating 11

12 Reference Application Circuit W (12V/4.2A) Adapter Schematic AC F1 NTC1 MOV1 NA R1A R1B R6 LF1 LF2 BD1 CX1 - + R2A R2C C9 R2E D2 D3 C8 C4 5 3 IC1 LD7531 SOT-26 RT 1 2 IC2/B 6 4 C6 R9 C5 R8 R11 CY1 R10 Q1 D4 R56 D1 C2 R4B*2 ZD1 C1 C54 C53 R4A*2 R5A R5B T1 CR51 C51 IC51 R51B R51A L51 R54 IC2/A C55 C52 R55 R53 R52 R99A/B/C ZD51 C99 Fig

13 Reference Application Circuit W (12V/4.2A) Adapter BOM P/N Component Value Note P/N Component Value Note R1A 1MΩ, 1206, 1% C1 100μF, 400V TY R1B 1MΩ, 1206, 1% C2 1000pF, 1000V, 1206 R2A 1MΩ, 1206, 1% C4 3.3μF, 50V LZG R2C 1MΩ, 1206, 1% C5 220pF, 50V, 0805 R2E 1MΩ, 1206, 1% C6 3.3nF, 50V, 0805 R4A/1 100KΩ, 1206, 1% C8 10μF, 50V LZG R4A/2 100KΩ, 1206, 1% C9 NA R4B/1 100KΩ, 1206, 1% C pF, 1000V, 1206 R4B/2 100KΩ, 1206, 1% C52 220μF, 25V LZG R5A 22Ω, 1206, 1% C μF, 16V LZG R5B 22Ω, 1206, 1% C μF, 16V LZG R6 0Ω, 1206, 5% C55 10nF, 50V, 0805 R8 0.43Ω, 2WS C99 NA R9 200Ω, 0805, 1% CX1 0.33μF, X-cap R10 15Ω, 1206, 1% CY1 2200pF,Y-cap, class1 R11 20KΩ, 1206, 1% D1 1N4007 RT 100KΩ, 0805, 1% D2 1N4007 R51A 75Ω, 1206, 1% D3 1N4148, R51B 75Ω, 1206, 1% D4 1N4148 R KΩ, 0805, 1% Q1 8A, 600V R KΩ, 0805, 1% BD1 2A, 600V R54 510Ω, 0805, 1% CR51 10A, 100V R55 3KΩ, 0805, 1% ZD1 NA R56 NA ZD51 NA R99A 4.7KΩ, 1206, 1% IC1 LD7531 Leadtrend R99B NA IC2 EL817B R99C NA IC51 KA431, 1% NTC1 3A, 5Ω F1 250V, T2A Walter LF1 Leadtrend s Design MOV1 NA LF2 Leadtrend s Design T1 Leadtrend s Design L51 Leadtrend s Design 13

14 Reference Application Circuit # W Adapter with 2-Stage Startup Circuit Pin < 0.25W when Pout = 0W F1 AC input R1A R1B NTC1 CX1 Z1 RT 100K Ohm FL1 RT D1A~D1D C1 VCC IC1 LD7531 OUT CS COMP GND R8 R7 C3 C2 D3 D2 R2B R2A 2-stage Startup Circuit R51B R51A C51 L51 T1 R4A CR51 C4 C52 R4B ZD51 R56A R56B R6 D4 Q1 RS2 RS1 R54 R52 IC2 C5 photocoupler C55 CY1 R55 IC51 R53 C54 Fig

15 Reference Application Circuit # W Adapter with 2-Stage Startup Circuit BOM P/N Component Value Original R1A N/A R1B N/A R2A 2.2MΩ, 1206 R2B 2.2MΩ, 1206 R4A 39KΩ, 1206 R4B 39KΩ, 1206 R6 2.2Ω, 1206 R7 10Ω, 1206 R8 10KΩ, 1206 RS1 2.70Ω, 1206, 1% RS2 2.70Ω, 1206, 1% R51A 100Ω, 1206 R51B 100Ω, 1206 R KΩ, 0805, 1% R KΩ, 0805, 1% R54 220Ω, 0805 R55 10KΩ, 0805 R56A 1KΩ, 1206 R56B N/A NTC1 5Ω, 3A 08SP005 FL1 20mH UU9.8 T1 EI-22 L51 2.7μH P/N Component Value Note C1 22μF, 400V L-tec C2 10μF, 50V L-tec C3 2.2μF, 50V C4 1000pF, 1000V, 1206 Holystone C5 0.01μF, 16V, 0805 C pF, 50V, 0805 C μF, 10V L-tec C54 470μF, 10V L-tec C μF, 16V, 0805 RT 100kΩ, 0805, 1% CX1 0.1μF X-cap CY1 2200pF Y-cap D1A 1N4007 D1B 1N4007 D1C 1N4007 D1D 1N4007 D2 PS102R D3 1N4148 D4 1N4007 Q1 2N60B 600V/2A CR51 SB540 ZD51 6V2C IC1 LD7531 GS SOT-26 IC2 EL817B IC51 TL431 1% F1 250V, 1A Z1 N/A 15

16 Package Information SOT-26 Symbol Dimension in Millimeters Dimensions in Inches Min Max Min Max A B C D F 0.95 TYP TYP H I J M θ

17 Package Information DIP-8 Symbol Dimension in Millimeters Dimensions in Inches Min Max Min Max A B C D E F I J L Important Notice Leadtrend Technology Corp. reserves the right to make changes or corrections to its products at any time without notice. Customers should verify the datasheets are current and complete before placing order. 17

18 Revision History Rev. Date Change Notice 00 6/25/2008 Original Specification 18