Improved ON-resistance Measurement at Wafer Probe using a "DARUMA" stage

Transcription

1 Improved ON-resistance Measurement at Wafer Probe using a "DARUMA" stage Masatomo TAKAHASHI ACCRETECH, Japan Nobuyuki TOYODA TESEC, Japan

2 Background Trend of MOSFET Overview Solution DARUMA Transition of low ON resistance Overview of DARUMA Chuck (Rds (on) ) products Advantage of DARUMA Chuck etc. Present situation Verification Measurement by Standard Measurement by DARUMA stage Comparison with standard stage Matter of concern Simulation Suspected root cause Conclusion 2

3 Application and Criteria Trends of MOSFET Load switch for DC Supply-unit in server Low On-Resistance (Rds (on) ) Low Thermal Resistance (Rθjc, etc.) Wide Safe Operating Area (SOA) Switching device for switched-mode power supply (SMPS) Low Rds (on) Low Gate Charge (Qg) Motor control Low Reverse Recovery Time (trr) 3

4 Trends of MOSFET Purpose vs Representative Characteristics Energy savings Low On-Resistance (Low loss) Fast switching Low gate Capacitance (High speed) High reliability Wide Safe Operating Area, (High performance) High breakdown resistance Miniaturization Enhancement of Heat-resisting property (Small packaging) 4

5 Transition of low ON resistor products Si marginal Less than 1m ohm Sic marginal Gan marginal Breakdown volt (V) Graphs from Toshiba Review Vol.65No.1 (2010) 5

6 Present situation Standard System connection TESEC 431-TT Discrete DC Tester VI-SMU inside Test Station Drain Force(DI), Drain Sense(DV) Gate Force(GI), Gate Sense(GV), Source Force(SI), Source Sense(SV) Accretech UF2000 Wafer Prober 6

7 Present situation Simplified Schematics for Rds (on) testing at wafer probe IDS A Ammeter IDS Pulse Current VGS V Voltmeter VDS Drain Pulse Voltage Gate DUT Source 7

8 Present situation Simplified Schematics for Rds (on) to check waveform A Ammeter IDS Pulse Current IDS VGS V Voltmeter VDS Waveform Monitor on the Tester Drain VDS Pulse Voltage IDS, VGS DSO Gate DUT Source Current Sense Transformer 8

9 Present situation Timing chart VGS IDS 100uS 300uS 9

10 Present situation [Measurement result-1] Test condition : Rds (on), IDS=200A, Test time=500us Stage type : Standard 100uS 500uS 100uS 500uS VGS IDS 10

11 Present situation [Measurement result-2] Test condition : Rds (on), IDS=200A, Test time=1000us Stage type : Standard 100uS 1000uS 100uS 1000uS Stable after 500uS, but still gradually cut-down VGS IDS 11

12 Matters of concern Measurement waveform is unstable (Need longer test time to be stabilize) Increases Forcing time of test current Increases temperature of the tested device Decreases the test accuracy and production quality 12

13 Ideal test environment (Temperature) Matters of concern Exists when the channel(junction) and case (package) temp are the same. Requires Very short pulse during on-resistance test to achieve temperature parity between Junction and Case Characteristic of MOSFETs, the on-resistance will rise as the device temp is increased in an attempt to protect the device itself (as the resistance increases, the current decreases) Therefore, when testing Rds (on), controlling the temperature rise is critical to measurement stability. To control the temp during test, minimize the test time ON resistance vs Channel temperature From Fuji Electric AN-079 Rev

14 Ls (Stray Inductance) Expected root cause Self inductance of wire loop (round trip) I I d Diameter of the wire to be 2a, When the current is uniformly distributed in the electric wire, and the conductor is nonmagnetic. L = 4 * log(d/a) * 10^-7 [H/m] 14

15 Ls (Stray Inductance) Expected root cause Mutual inductance between parallel wires l d Pair of parallel wires, When l >> d, and in the air atmosphere. M = 2 * l * (log(2 * l / d) -1) * 10^-7 [H] 15

16 VDS waveform is NOT stable. Expected root cause Influence of the Stray Inductance (Ls) of the wiring between DUT and source & measurement circuits. Ls increases as the wire loop increases. A Drain Stage Source Wafer V 16

17 Expected root cause The cause of the VDS Spiking is in Ls. ΔV=Ls(di/dt) VGS IDS 17

18 DARUMA The Daruma doll, is a hollow, round, Japanese traditional doll modeled after Bodhidharma (Dharma), the founder of the Zen sect of Buddhism. Daruma has a design that is rich in symbolism and is regarded more as a talisman of good luck to the Japanese. When purchased, the eyes are white so a person can decide on a goal or wish and paint one eye in. Once the goal is achieved, the second eye is filled in. 18

19 Overview of DARUMA Chuck (1) Standard connection To Tester DARUMA connection To Tester Several cm Metal Plate Wire Over 2m 19

20 Overview of DARUMA Chuck (2) Pogo Block DARUMA Chuck Probe Card Needles Wafer Chuck Z Unit 20

21 DARUMA Chuck Advantage of DARUMA Chuck Back Pogo Pins Tester Probe Card Front Wafer Chuck Wafer Front side of wafer 200mm DARUMA Back side of wafer Wafer Chuck DARUMA Chuck Wafer Chuck DARUMA Chuck Maintain same distance 21

22 Alignment for Pogo Pins Probe to pad alignment camera Search pogo pin height and check the difference using alignment camera. Then calculate the best over drive point for contacting to the DARUMA chuck. 22

23 Maintenance Turn ON voltage/contact resistance <- Chuck surface condition Large current/inductive load test -> Deteriorating chuck top Required periodical chuck top maintenance Remove chuck Remove chuck Install chuck Planarity check 23

24 Overview of Evaluation Setup 24

25 Verification DARUMA System connection TESEC 431-TT Discrete DC Tester VI-SMU inside Test Station Drain Sense(DV) Gate Force(GI), Gate Sense(GV), Source Force(SI), Source Sense(SV), Drain Force(DI) Accretech UF2000 Wafer Prober 25

26 [Measurement result-1] Verification Test condition : Rds (on), IDS=200A, Test time=500us Stage type : DARUMA 100uS 500uS 100uS 500uS VGS IDS 26

27 [Measurement result-2] Verification Test condition : Rds (on), IDS=200A, Test time=1000us Stage type : DARUMA 100uS 1000uS 100uS 1000uS VGS Furthermore IDS 27

28 Comparison with standard stage Test condition : Rds (on), IDS=200A, Test time=1000us Standard connection DARUMA connection 28

29 Comparison with standard stage Standard DARUMA 29

30 Comparison with standard stage Standard system connection TESEC 431-TT Discrete DC Tester VI-SMU inside Test Station Drain Force(DI), Drain Sense(DV) Gate Force(GI), Gate Sense(GV), Source Force(SI), Source Sense(SV) Accretech UF2000 Wafer Prober 30

31 Comparison with standard stage DARUMA system connection TESEC 431-TT Discrete DC Tester VI-SMU inside Test Station Drain Sense(DV) Gate Force(GI), Gate Sense(GV), Source Force(SI), Source Sense(SV), Drain Force(DI) Accretech UF2000 Wafer Prober 31

32 Comparison with standard stage Point of interest North North Standard DARUMA Pogo Pins SI SI SV SV GI GI V GV V GV DI DI DV West East DV West East South South 32

33 Comparison with standard stage Point of interest Device Connection Comparison Table Standard vs DARUMA Standard DARUMA GV Probe Card GI Probe Card SV Probe Card SI Probe Card DV South East South of the Stage of the Stage DI North West of the Stage via 2m Wire North of the Stage via DARUMA 33

34 Point of interest Comparison with standard stage R3 is Contact resistance between Wafer and Stage. R3 DV R1 R2 DI R1 and R2 do not affect to VDSON value. R3 is added to VDSON. It is only R3 that increases VDSON. Measurement values are almost independent of location. 34

35 Simulation Simulated model Schematics for Standard connection A V R9 = Rds (on) Tester, Station and Wiring (Outside of the Prober) Inside of the Prober 35

36 Simulation Waveform Simulated vs Simulated Standard Actual Standard IDS VDS 36

37 Simulation Simulated model Schematics for DARUMA connection A V R9 = Rds (on) Tester, Station and Wiring (Outside of the Prober) Inside of the Prober 37

38 Simulation Waveform Simulated vs Simulated DARUMA Actual DARUMA IDS VDS 38

39 Simulation Simulated Waves comparison Standard vs DARUMA Simulated Standard Simulated DARUMA IDS IDS VDS VDS 39

40 Conclusion Demand for higher-efficiency of Mobile and Automotive devices, is driving the need for MOSFETs with even lower Rds (on). Improving measurement accuracy while at the same time reducing device stress will continue to be test challenges for the future. However, by employing a DARUMA stage, these test challenges can be met at wafer probe when testing (Rds (on) ) on MOSFETs. Ls will be minimized to enable reduced test time (especially at high current). By reducing test time, temperature rise will be reduced producing less stress on the DUT also resulting in more stable and accurate measurements. 40

41 Acknowledgements We would like to thank the following colleagues for supporting this workshop. Yuji SHIGESAWA Tomoyuki MYOJO Shoji TERADA Yuichi KAKIZAKI Kiyoaki KOYAMA Muneo ISHINOHACHI Masashi HOSHINO We hope these efforts bring further development of products that will contribute to societal advancements. 41

42 Thank you 42