Composants HEMT InAlGaN/GaN pour applications en bandes Ka et Q.

Transcription

1 Composants HEMT InAlGaN/GaN pour applications en bandes Ka et Q. Stéphane PIOTROWICZ, Olivier PATARD, Jean-Claude JACQUET, Piero GAMARRA, Christian DUA & Sylvain DELAGE RF & Microwave 22 mars 2018 Copyright 2011 III-V Lab. All rights reserved.

2 Summary InAlN and InAlGaN at III-V Lab Buffer design Passivation scheme Characterizations DC pulsed I-V [S]- parameters and load-pull Robustness MMIC Conclusion 2

3 InAlN InAlGaN HEMT In 17 Al 83 N/GaN : - Spontaneous polarization without lattice mismatch Spontaneous polarization of GaN, InN and AlN compounds vs lattice constant Stronger spontaneous polarization: Higher electron density Higher power density Lattice match: Less lag effects? Better reliability? 3

4 InAlN InAlGaN HEMT InAlGaN barrier layer High Ns and saturation velocity High spontaneous polarization at the interface -> high 2DEG density High mobility thanks to AlN interlayer Barrier layer nearly lattice matched to GaN Thin barrier, large barrier height Good for high frequency applications Short gate length needed to address Ka to Q bands Need for an efficient buffer layer to avoid short channel effects 4

5 Device structure The technology transfer from our research reactor (2 wafers) to 3 & 4 multi wafers reactor involved many changes at epitaxy and process level One point is the introduction of a reproducible Ga Incorporation in the barrier layer generating a quaternary InAlGaN layer. Source Gate InAlGaN (6.5 nm) AlN Interlayer (1 nm) GaN Nid (150 nm) PE-CVD passivation ICP-CVD passivation Drain 2DEG GaN AlN InAlGaN Strain management layers AlGaN Back-barrier GaN - nid AlN Nucleation (100 nm) SiC Substrate (1.6 µm) SiC AlN TEM Analysis: P. Ruterana CIMAP (Caen) 5

6 Wafer to wafer reproducibility 100 mm wafers Average sheet resistance CREE susbtrates (4H-SiC) SiCrystal susbtrates (6H-SiC) Norstel Substrate (4H-SiC) Target value: 250 Ω/sq Average sheet resistance: Ω/sq, Standard deviation: 5.8 Ω/sq 6

7 Technology Overview Mulifinger devices TEM cross section LETI Gate 100mm 150nm Source 100mm compatible process 0.15µm gate length & 0.1µm underway Bi-layer passivation Multi-finger devices MMIC process compatible with UMS Source bridge 100mm MMIC compatible technology 7

8 Buffer Layer designed by TCAD DRAIN CURRENT (A/mm) Buffer Layer Role : Ensure the electron confinement in the 2-DEG : High On/Off ratio for optimum transconductance -> high gain and minimum short channel effects PE-CVD passivation Source Gate InAlGaN (6.5 nm) AlN Interlayer (1 nm) GaN Nid (150 nm) GaN - nid AlN Nucleation (100 nm) SiC Substrate ICP-CVD passivation Drain 2DEG 1.E+00 1.E-01 1.E-02 1.E-03 1.E-04 1.E-05 1.E-06 1.E-07 1.E-08 1.E-09 1.E-10 Simulation TCAD GATE VOLTAGE (V) nid GaN in the buffer layer -> No pinch-off 8

9 DRAIN CURRENT (A/mm) Buffer Layer designed by TCAD DRAIN CURRENT (A/mm) Buffer Layer Role : Ensure the electron confinement in the 2-DEG : High On/Off ratio for optimum transconductance -> high gain and minimum short channel effects 1.E+00 1.E-01 1.E+00 1.E-01 Simulation TCAD 1.E-02 1.E-02 1.E-03 1.E-03 1.E-04 1.E-04 G m 1.E-05 1.E-05 1.E-06 1.E-06 1.E-07 1.E-07 1.E-08 1.E-08 1.E-09 1.E-09 1.E GATE VOLTAGE (V) 1.E GATE VOLTAGE (V) Good pinch-off : High Gm 9

10 Electrical validation of our back-barrier buffer layer Id & Ig (A/mm) Sub-Threshold Swing (mv/dec) Good pinch-off characteristics with our AlGaN Backbarrier with 0.15µm gate length Vgs (V) 2x50x0.15µm E Vds=5V Vds=10V Vds=15V Vds=20V 1.E-01 1.E-02 1.E-03 1.E-04 1.E-05 1.E µm 0.25µm Vds (V) Sub-threshold swing of 140mV/dec to 220mV/dec Between 5V and 20V with Ids+ > 1.2A/mm 10

11 Electrical validation of our back-barrier buffer layer Recovery Time Measurement Bench Hall effet probe Digital Oscilloscope Thermal chuck On wafer probe station AMCAD PIV HP8114A HP81110A 11

12 Buffer designed by TCAD Experimental recovery Time Measurement Id (A) Vgs is kept constant Vds is pulsed : Ids measured using a hall effect probe and digital oscilloscope Stimuli Pulse Vds : 9V à 19V AlGaN/GaN with Fe-doped buffer InAlGaN/GaN with back-barrier Vgs est fixe Vds (V) Our buffer layer incorporating a back-barrier approach significantly reduces the recovery time of drain current in comparison to Fe-doped buffer layer. 12

13 Buffer designed by TCAD Experimental recovery Time Measurement Drain current (A/mm) Comparison with TCAD simulations AlGaN/GaN with Fe-doped buffer InAlGaN/GaN with back-barrier Simulation TCAD SILVACO InAlN_BB AlGaN_Fer time, msec TCAD simulations have well predicted the time domain behavior of the drain current. The time domain signature of the Iron in the buffer layer is well established. 13

14 Buffer designed by TCAD Experimental recovery Time Measurement Drain current (A/mm) Impact of the back-side temperature AlGaN/GaN with Fe-doped buffer 30 C 40 C 50 C 60 C 70 C 80 C 90 C 100 C TCAD : The time domain signature of the iron in the buffer layer is well established also versus the temperature Simulation TCAD 30 C 40 C 50 C 60 C 70 C 80 C SILVACO 90 C 100 C time, msec 14

15 Temperature Increase ( C) Thermal validation of back-barrier buffer layer Raman Measurements performed at TRT TS837_SiC CREE03-04_SiC TS837_GaN CREE03-04_GaN T GaN Fe-doped buffer III-V Lab Back-Barrier buffer T SiC Fe-doped buffer 0 III-V Lab Back-Barrier buffer 0,6 0,7 0,8 0,9 1 1,1 1,2 1,3 1,4 1,5 1,6 1,7 1,8 1,9 2 2,1 Dissipated Power (W) Same temperature increase for Fe-doped buffer layer and backbarrier buffer, A buffer layer thermally optimized and with reduced lagging effects has been developed successfully by III-Vlab. 15

16 Id Id (A) (A/mm) And from the surface Non optimal passivation PASS3 : Bi-layer of SiN Vgsq =0V, Vdsq =0V Vgsq =-5V, Vdsq =0V Vgsq =-5V, Vdsq =25V Vgs = 1 V Vgs = 0 V Vgs = -1 V Vgs = -2 V Vgs = -3 V Vgs = -4 V Vgs = -5 V Our bi-layer passivation approach (PASS3) had significantly reduced lagging effects coming from the surface Vds (V) Reduced lagging effects up Vds q = 25V 16

17 DC Characteristics : Ids+, Ig leak & gm Gmmax (ms/mm) Vds=10V Vgs=-7V Vds=10V Vgs=+1V Vds=10V TS838W6_2x50D15S8G15V2#C4_m02 (mes2) IgL eak low (<300 µa/mm) Ids+ # 1.2A/mm Igs # 0.2 ma/mm Gm_ext # 450 ms/mm 0207_[18] 0208_[19] 0210_[21] 0307_[30] 0308_[31] 0310_[33] 0407_[42] 0408_[43] 0410_[45] 0507_[54] 0508_[55] 0510_[57] Vgs (V) Vgs (V) Gm (ms/mm)

18 Buffer Layer Buffer Layer Approaches : Acceptor dopant Back-Barrier Iron Carbon AlGaN (Al 8% - 1.6µm) AlGaN Patent Pinch-off J K J J Recovery time L K J J Thermal resistance J J L L J III-V Lab have developed a buffer layer thermally optimized and with reduced lagging effects 18

19 MSG/MAG & H21 ² (db) InAlGaN/GaN 0.15µm [S]-Parameters Small signal figures of merit H21 ² MSG/MAG 10 F (GHz) 20V 200mA/mm 2x50µm x 0.15µm -20dB/dec F t & F MAG # 70 GHz & ma/mm MSG = 30 GHz (probes planes no de-embedding) GHz GHz

20 Load-Pull Measurements Load-pull active/passive bench from S-Band to 30 GHz : Upgrade to 40 GHz in 2018 Active Harmonic matching. HPA1 HPA2 Powered by 20

21 30 GHz CW 6 InAlGaN/GaN HEMT measured : 8x50µm ; Lg=0.15µm Vd = 17.5V ; Ids = 100mA/mm 1.2W power 30 GHz Pout PAE Gp Pout : [ ] PAEmax [ ] W [3-3.5] W/mm MaxPAE : [41-45] % Gp : [ dB PAEmax 21

22 30 GHz CW 0.15µm - 8x50µm InAlGaN/GaN devices 2W/mm 1W 48% 1.4W 45% 2.5W/mm 4.5W/mm 4.5W/mm Optimum load for PAE Jds=50mA/mm Vds=15V Vds=17V Vds=20V Vds=22V Optimum load for Power Jds=50mA/mm Vds=15V Vds=17V Vds=20V Vds=22V 22

23 PAE (%) 10 GHz CW 0.15µm - 6x60µm InAlGaN/GaN devices x60µm F 0 =10 GHz Vds=15V Ids=200mA/mm Γ H2 = 1; φl H2 = 60 H2 optimum H2=50 Ohms ZL Fund for ZL H2 opt ZL Fund for ZL H2 50Ω PAE : up to 80% achieved WITH H2 control on InAlGaN/GaN HEMT devices Pout (dbm) 23

24 I DS =8V (%) Vds=8V (%) Some DC stability tests On-wafer DC stability tests DC Life test conditions: V DS =17.5V - 20V; I DS =200mA/mm; 64 h The evolution of the output characteristics is monitored during the test Stable DC parameters (I DSS degradation < 10%) I DS (V DS ) interim measurements 0% 0% -5% I DSS evolution DC Life Test_TS838W6 I DS =200mA/mm & V DS =15V, 17.5V, 20V (2x50µm, Lg=0.15µm) 17.5V, Ta=RT -10% 20V, Ta=RT -15% -20% -20% 15V, Ta=85 C 17.5V_XFD 17.5V_XED 20V_XDP 15V_BYH_a 15V_BXH_b Improvement still needed and on-going -30% Time (h) Passivation identified as not robust enough at high Vds 24-25% - 30% Time (hrs)

25 HPA MMIC Simulations 3 stages [ ] GHz Pout # 40 dbm PAE > 22% 5140x3640µm² Vds=17.5V Ids=200mA/mm Demonstration at circuit level in Ka and Q bands ARCTURUS 28 GHz Simulations 3 stages [ ] GHz Pout # 37 dbm PAE > 15% 5140x3640µm² Vds=17.5V Ids=200mA/mm SIRIUS 38 GHz 25

26 Demonstration at circuit level in Ka and Q bands Pulsed power Vds=17V 800mA 0.2nH On Wafer (50 Ohms) 0.2nH On Wafer (50 Ohms) Up to 10W at 25 GHz PAE > 20% On JIG measurements should improve performances in the upper frequency band 26

27 Demonstration at circuit level in Ka and Q bands Pulsed power Vds=17V 800mA 25dBm 25dBm 27dBm 27dBm 6W at 39.5 GHz with 20% PAE 27

28 Conclusions InAlGaN technology with 0.15µm gate length can operate up to Q-Band Optimized AlGaN back-barrier buffer layer offers disruptive behaviors Thermal and recovery time 100mm process MMIC compatible technology 6W demonstrated at 39.5 GHz at HPA level Robustness improvement is on going 28

29 Acknowledgments The authors would like to thank : the European Defense Agency (EDA) for the support to this work in the context of the project entitled European Gallium Nitride Industry supply Chain (EUGaNIC) funded by Germany, France Italy and Sweden in the frame of the Project n B-1447-IAP1-GP of the European Defence Agency. French Ministry of Economy (DGE) : VEGaN project French MOD (DGA) and CNES And : UMS for MMIC processing and measurements Prof. Juan Obregon for constant technical advices and fruitful discussions 29

30 Thank you for your attention! 30