CMF20120D-Silicon Carbide Power MOSFET 1200V 80 mω Z-FeT TM MOSFET

Transcription

1 CMFD Rev. A CMFD-Silicon Carbide Power MOSFET V 8 mω Z-FeT TM MOSFET N-Channel Enhancement Mode Subject to change without notice.

2 CMFD-Silicon Carbide Power MOSFET Z-FeT TM MOSFET N-Channel Enhancement Mode Features Package V DS R DS(on) = V = 8 mω I C =5 C = 33 A Industry Leading R DS(on) High Speed Switching Low Capacitances Easy to Parallel Simple to Drive Pb-Free Plating, RoHS Compliant, Halogen Free Benefits TO-47-3 G D S Higher System Efficiency Reduced Cooling Requirements Avalanche Ruggedness Increased System Switching Frequency Applications Solar Inverters High Voltage DC/DC Converters Motor Drives Part Number CMFD Package TO-47-3 Maximum Ratings Symbol Parameter Value Unit Test Conditions Note I D Continuous Drain Current 33 V T C = 5 C A 7 V T C = C I Dpulse Pulsed Drain Current 78 A E AS Single Pulse Avalanche Energy. J Pulse width t P limited by T jmax T C = 5 C I D = A, V DD = 5 V, L = 9.5 mh E AR Repetitive Avalanche Energy.5 J t AR limited by T jmax I AR Repetitive Avalanche Current A I D = A, V DD = 5 V, L = 3 mh t AR limited by Tjmax V GS Gate Source Voltage -5/+5 V P tot Power Dissipation 5 W T C =5 C T J, T stg Operating Junction and Storage Temperature -55 to +5 C T L Solder Temperature 6 C.6mm (.63 ) from case for s M d Mounting Torque 8.8 Nm lbf-in M3 or 6-3 screw CMFD Rev. A

3 Table of Contents Features... Benefits... Applications... Maximum Ratings... Table of Contents...3 Applications Information...4 ESD Ratings...7 Electrical Characteristics...8 Reverse Diode Characteristics...8 Thermal Characteristics...8 Gate Charge Characteristics...8 Typical Performance...9 Clamped Inductive Switch Testing Fixture... Package Dimensions... Recommended Solder Pad Layout...3 Notice CMFD Rev. A

4 Applications Information The Cree SiC MOSFET has removed the upper voltage limit of silicon MOSFETs. However, there are some differences in characteristics when compared to what is usually expected with high voltage silicon MOSFETs. These differences need to be carefully addressed to get maximum benefit from the SiC MOSFET. In general, although the SiC MOSFET is a superior switch compared to its silicon counterparts, it should not be considered as a direct drop-in replacement in existing applications. There are two key characteristics that need to be kept in mind when applying the SiC MOSFETs: modest transconductance requires that V GS needs to be V to optimize performance. This can be see in the Output and Transfer Characteristics shown in Figures -3. The modest transconductance also affects the transition where the device behaves as a voltage controlled resistance to where it behaves as a voltage controlled current source as a funtion of V DS. The result is that the transition occurs over higher values of V DS than are usually experienced with Si MOSFETs and IGBTs. This might affect the operation anti-desaturation circuits, especially if the circuit takes advantage of the device entering the constant current region at low values of forward voltage. The modest transconductance needs to be carefully considered in the design of the gate drive circuit. The first obvious requirement is that the gate be capable of a > V (+ V to -V) swing. The recommended on state V GS is + V and the recommended off state V GS is between - V to -5 V. Please carefully note that although the gate voltage swing is higher than the typical silicon MOSFETs and IGBTs, the total gate charge of the SiC MOSFET is considerably lower. In fact, the product of gate voltage swing and gate charge for the SiC MOSFET is lower than comparable silicon devices. The gate voltage must have a fast dv/dt to achieve fast switching times which indicates that a very low impedance driver is necessary. Lastly, the fidelity of the gate drive pulse must be carefully controlled..5v The nominal threshold voltage is.5v and the device is not fully on (dv DS /dt ) until the V GS is above 6V. This is a noticeably wider range than what is typically experienced with silicon MOSFETs and IGBTs. The net result of this is that the SiC MOSFET has a somewhat lower noise margin. Any excessive ringing that is present on the gate drive signal could cause unintentional turn-on or partial turn-off of the device. The gate resistance should be carefully selected to ensure that the gate drive pulse is adequately dampened. To first order, the gate circuit can be approximated as a simple series RLC circuit driven by a voltage pulse as shown below. 4 CMFD Rev. A

5 V PULSE R LOOP L LOOP C GATE ζ = R LOOP LOOP C L R GATE LOOP L C LOOP GATE As shown, minimizing L LOOP minimizes the value of R LOOP needed for critical dampening. Minimizing L LOOP also minimizes the rise/fall time. Therefore, it is strongly recommended that the gate drive be located as close to the SiC MOSFET as possible to minimize L LOOP. The internal gate resistance of the SiC MOSFET is 5 Ω. An external resistance of 6.8 Ω was used to characterize this device. Lower values of external gate resistance can be used so long as the gate fidelity is maintained. In the event that no external gate resistance is used, it is suggested that the gate current be checked to indirectly verify that there is no ringing present in the gate circuit. This can be accomplished with a very small current transformer. A recommended setup is a two-stage current transformer as shown below: IG SENSE VCC GATE DRIVE INPUT + GATE DRIVER T SiC DMOSFET - VEE 5 CMFD Rev. A

6 Stray inductance on source lead causes load di/dt to be fed back into gate drive which causes the following: Switch di/dt is limited Could cause oscillation Kelvin gate connection with separate source return is highly recommended LOAD CURRENT V V R GATE R GATE DRIVE SiC DMOS DRIVE SiC DMOS LOAD CURRENT L STRAY L STRAY A schematic of the gate driver circuit used for characterization of the SiC MOSFET is shown below: THESE COMPONENTS ARE LOCATED ON THE PLANE +VCC +VCC THESE COMPONENTS ARE LOCATED ON THE GND PLANE C u C C3 u C4 GND C5 +VCC C6 u R C7 u C IN OUT GND U LM93T-5. 3 C u 6.3V R C3 J BNC C 39 n ISO C8 PIN SOURCE C9 PULSE GEN INPUT D R3 R4 R5 R C4 6N37 PIN GATE U 4 VCC IN VCC OUT NC OUT GND GND TBD 6 8 RB6M-6 7 R7 6 TBD 6 5 D R8 IXDI44 TBD 6 C5 RB6M-6 J BNC C6 VGS MONITOR +VCC C7 C8 C9 C u The gate driver is an IXYS IXDI44. This device has a 35 V ouput swing, output resistance of.6 Ω typical, and a peak current capability of 4 A. The external gate resistance used for characterization of the SiC MOSFET was 6.8 Ω. Careful consideration needs to be given to the selection of the gate driver. The typical application error is selection of a gate driver that has adequate swing, but output 6 CMFD Rev. A

7 resistance and current drive capability are not carefully considered. It is critical that the gate driver possess high peak current capability and low output resistance along with adequate voltage swing. A significant benefit of the SiC MOSFET is the elimination of the tail current observed in silicon IGBTs. However, it is very important to note that the current tail does provide a certain degree of parasitic dampening during turn-off. Additional ringing and overshoot is typically observed when silicon IGBTs are replaced with SiC MOSFETs. The additional voltage overshoot can be high enough to destroy the device. Therefore, it is critical to manage the output interconnection parasitics (and snubbers) to keep the ringing and overshoot from becoming problematic. ESD RATINGS ESD Test Total Devices Sampled Resulting Classification ESD-HBM All Devices Passed V (>V) ESD-MM All Devices Passed 4V C (>4V) ESD-CDM All Devices Passed V IV (>V) 7 CMFD Rev. A

8 Electrical Characteristics Symbol Parameter Min. Typ. Max. Unit Test Conditions Note V (BR)DSS Drain-Source Breakdown Voltage V V GS = V, I D = μa V GS(th) I DSS Gate Threshold Voltage Zero Gate Voltage Drain Current.5 4 V DS = V GS, I D = ma, T J = 5ºC V.8 V DS = V GS, I D = ma, T J = 5ºC V DS = V, V GS = V, T J = 5ºC μa 5 V DS = V, V GS = V, T J = 5ºC I GSS Gate-Source Leakage Current 5 na V GS = V, V DS = V R DS(on) g fs Drain-Source On-State Resistance Transconductance C iss Input Capacitance 95 C oss Output Capacitance C rss Reverse Transfer Capacitance 3 t d(on)i Turn-On Delay Time 7. t r Rise Time 3.6 t d(off)i Turn-Off Delay Time 6 t fi Fall Time 35.6 E ON Turn-On Switching Loss (5ºC) (5ºC) E Off Turn-Off Switching Loss (5ºC) (5ºC) 8 VGS = V, ID = A, TJ = 5ºC mω 95 3 V GS = V, I D = A, T J = 5ºC 7.3 V DS= V, I DS= A, T J = 5ºC S 6.8 V DS= V, I DS= A, T J = 5ºC pf ns V GS = V V DS = 8V f = MHz VAC = 5mV V DD = 8V V GS = -/V I D = A R G = 6.8Ω L = 856μH Per JEDEC4 Page 7 R G Internal Gate Resistance 5 Ω V GS = V, f = MHz, V AC = 5mV NOTES:. The recommended on-state V GS is +V and the recommended off-state V GS is between -V and -5V Reverse Diode Characteristics Symbol Parameter Typ. Max. Unit Test Conditions Note μj μj fig. 3 fig. 5 fig. V sd Diode Forward Voltage t rr Reverse Recovery Time ns Q rr Reverse Recovery Charge 4 nc I rrm Peak Reverse Recovery Current.3 A 3.5 V GS = -5V, I F =A, T J = 5ºC 3. V V GS = -V, I F =A, T J = 5ºC V GS = -5V, I F =A, T J = 5ºC V R = 8V, di F/dt= A/μs fig. 3,4 Thermal Characteristics Symbol Parameter Typ. Max. Unit Test Conditions Note R θjc Thermal Resistance from Junction to Case.58.7 R θcs Case to Sink, w/ Thermal Compound.5 R θja Thermal Resistance From Junction to Ambient 4 C/W fig. 6 Gate Charge Characteristics Symbol Parameter Typ. Max. Unit Test Conditions Note Q gs Gate to Source Charge 3.8 Q gd Gate to Drain Charge 43. Q g Gate Charge Total 9.8 nc V DD = 8V I D =A V GS = -/V Per JEDEC4- fig.9 8 CMFD Rev. A

9 Typical Performance I D (A) 8 6 V GS=V V GS=8V V GS=6V I D (A) 8 6 V GS=V V GS=8V V GS=6V V GS=4V 4 V GS=4V 4 V GS=V V GS=V V GS=V V GS=V V DS (V) Fig. Typical Output Characteristics T J = 5ºC V DS (V) Fig. Typical Output Characteristics T J = 5ºC I D (A) 3 T = 5 C T = 5 C Normalized R DS(on)..8.6 V GS=V V GS (V) Figure 3. Typical Transfer Characteristics T ( o C) Fig 4. Normalized On-Resistance vs. Temperature.E-8 V GS = V f = MHz.E-8 V GS = V f = MHz C iss C iss.e-9.e-9 Capacitance (F).E- C oss Capacitance (F).E- C oss C rss C rss.e V DS (V).E V DS (V) Fig 5A and 5B. Typical Capacitance vs. Drain Source Voltage 9 CMFD Rev. A

10 Typical Performance.E+.E- Z th ( o C/W).E-.E-3.E-4.E-6.E-5.E-4.E-3.E-.E-.E+.E+ Time (s) Fig 6. Transient Thermal Impedence, Junction - Case Switching Loss (µj) 4 3 V GS= -/V RG=.8Ω Total VDD= 8V ID= A Switching Loss (µj) 4 3 V GS= -/V RG=.8Ω Total VDD= 8V ID= A Temp ( C) Fig 7. Inductive Switching Energy(Turn-on) vs. T Temp ( C) Fig 8. Inductive Switching Energy(Turn-off) vs. T V DS V GS (V) 5 I D =A V DD =8V I DS (A) 5 I DS 5 V DS (V) 5 E AS =. J Gate Charge (nc) Fig 9. Typical Gate Charge 5 C Time (s) Fig. Typical Avalanche Waveform CMFD Rev. A

11 Clamped Inductive Switch Testing Fixture tw VGS(on) pulse duration Input (V i ) 5% 9% 9% 5% % % 856μH CDD A, V SiC Schottky VGS(off) Input Pulse Rise Time Input Pulse Fall Time + 8V - 4.3μf td(on)i tfi td(off)i tri CMFD D.U.T. id(on) % % Output (i D ) 9% 9% id(off) ton(i) toff(i) Fig. Switching Waveform Test Circuit Fig. Switching Test Waveform Times Ic t rr Qrr= trr id dt tx Vpk tx % Vcc Irr % Irr Vcc Diode Recovery Waveforms + - 8V 4.3μf 856μH CMFD CMFD D.U.T. Diode Reverse Recovery Energy Erec= t id dt t t t Fig 3. Body Diode Recovery Waveform Fig 4. Body Diode Recovery Test CMFD Rev. A

12 E A = /L x I D Fig 5. Avalanche Test Circuit Fig 6. Theoretical Avalanche Waveform Package Dimensions Package TO-47-3 G D S Inches Millimeters POS Min Max Min Max A A A b b b b b c D D D E E E E E e.4 BSC 5.44 BSC N 3 3 L L ØP Q S CMFD Rev. A

13 Recommended Solder Pad Layout TO-47-3 Part Number CMFD Package TO-47-3 The levels of environmentally sensitive, persistent biologically toxic (PBT), persistent organic pollutants (POP), or otherwise restricted materials in this product are below the maximum concentration values (also referred to as the threshold limits) permitted for such substances, or are used in an exempted application, in accordance with EU Directive /95/EC on the restriction of the use of certain hazardous substances in electrical and electronic equipment (RoHS), as amended through April, 6. This product has not been designed or tested for use in, and is not intended for use in, applications implanted into the human body nor in applications in which failure of the product could lead to death, personal injury or property damage, including but not limited to equipment used in the operation of nuclear facilities, life-support machines, cardiac defibrillators or similar emergency medical equipment, aircraft navigation or communication or control systems, air traffic control systems, or weapons systems. Copyright - Cree, Inc. All rights reserved. The information in this document is subject to change without notice. Cree and the Cree logo are registered trademarks and Z-REC and Z-FET are trademarks of Cree, Inc. Cree, Inc. 46 Silicon Drive Durham, NC 773 USA Tel: Fax: CMFD Rev. A