TIBPAL22V10-20M HIGH-PERFORMANCE IMPACT-X PROGRAMMABLE ARRAY LOGIC CIRCUITS

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1 TBPALV-M HGH-PERFORMANCE MPACT-X PROGRAMMABLE ARRAY LOGC CRCUTS Second-Generation PLD Architecture High-Performance Operation: f max (External Feedback) MHz Propagation Delay... ns Max ncreased Logic Power Up to nputs and Outputs ncreased Product Terms Average of per Output Variable Product Term Distribution Allows More Complex Functions to Be mplemented Each Output s User Programmable for Registered or Combinational Operation, Polarity, and Output Enable Control Power-Up Clear on Registered Outputs TTL-Level Preload for mproved Testability Extra Terms Provide Logical Synchronous Set and Asynchronous Reset Capability Fast Programming, High Programming Yield, and Unsurpassed Reliability Ensured Using Ti-W Fuses AC and DC Testing Done at the Factory Utilizing Special Designed-n Test Features Dependable Texas nstruments Quality and Reliability Package Options nclude Plastic Dual-n-Line and Chip Carrier Packages description CLK/ GND SRPSB JUNE 99 REVSED APRL JT OR W PACKAGE (TOP VEW) The TBPALV-M is a programmable array logic device featuring high speed and functional equivalency when compared to presently available devices. They are implemented with the familiar sum-of-products (AND-OR) logic structure featuring the new concept Programmable Output Logic. These MPACT-X circuits combine the latest Advanced Low-Power Schottky technology with proven titaniumtungsten fuses to provide reliable, high-performance substitutes for conventional TTL logic. These devices contain up to inputs and outputs. They incorporate the unique capability of defining and programming the architecture of each output on an individual basis. Outputs may be registered or nonregistered and inverting or noninverting as shown in the output logic macrocell diagram. The ten potential outputs are enabled through the use of individual product terms. Further advantages can be seen in the introduction of variable product term distribution. This technique allocates from to logical product terms to each output for an average of product terms per output. This variable allocation of terms allows far more complex functions to be implemented than in previously available devices. NC V CC FK PACKAGE (TOP VEW) CLK/ NC VCC GND NC NC No internal connection Pin assignments in operating mode NC This device is covered by U.S. Patent 4,4,97. MPACT-X is a trademark of Texas nstruments ncorporated. PRODUCTON DATA information is current as of publication date. Products conform to specifications per the terms of Texas nstruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright, Texas nstruments ncorporated POST OFFCE BOX 5533 DALLAS, TEXAS 755

2 TBPALV-M HGH-PERFORMANCE MPACT-X PROGRAMMABLE ARRAY LOGC CRCUTS SRPSB JUNE 99 REVSED APRL description (continued) Circuit design is enhanced by the addition of a synchronous set and an asynchronous reset product term. These functions are common to all registers. When the synchronous set product term is a logic, the output registers are loaded with a logic on the next low-to-high clock transition. When the asynchronous reset product term is a logic, the output registers are loaded with a logic. The output logic level after set or reset depends on the polarity selected during programming. Output registers can be preloaded to any desired state during testing. Preloading permits full logical verification during product testing. With features such as programmable output logic macrocells and variable product term distribution, the TBPALV-M offers quick design and development of custom LS functions with complexities of 5 to equivalent gates. Since each of the ten output pins may be individually configured as inputs on either a temporary or permanent basis, functions requiring up to inputs and a single output or down to inputs and outputs are possible. A power-up clear function is supplied that forces all registered outputs to a predetermined state after power is applied to the device. Registered outputs selected as active-low power up with their outputs high. Registered outputs selected as active-high power up with their outputs low. A single security fuse is provided on each device to discourage unauthorized copying of fuse patterns. Once blown, the verification circuitry is disabled and all other fuses will appear to be open. The TBPALV-M is characterized for operation over the full military temperature range of 55 C to 5 C. POST OFFCE BOX 5533 DALLAS, TEXAS 755

3 TBPALV-M HGH-PERFORMANCE MPACT-X PROGRAMMABLE ARRAY LOGC CRCUTS functional block diagram (positive logic) SRPSB JUNE 99 REVSED APRL & 44 x 3 Set Reset C S R Output Logic CLK/ 4 4 denotes fused inputs POST OFFCE BOX 5533 DALLAS, TEXAS 755 3

4 TBPALV-M HGH-PERFORMANCE MPACT-X PROGRAMMABLE ARRAY LOGC CRCUTS SRPSB JUNE 99 REVSED APRL logic symbol (positive logic) CLK/ ncrements First Fuse Numbers P = 5 R = 59 P = 5 R = 5 P = 5 R = 53 P = 54 R = 55 P = 5 R = Asynchronous Reset (to all registers) 4 POST OFFCE BOX 5533 DALLAS, TEXAS 755

5 TBPALV-M HGH-PERFORMANCE MPACT-X PROGRAMMABLE ARRAY LOGC CRCUTS SRPSB JUNE 99 REVSED APRL Fuse number = First fuse number + ncrement nside each MACROCELL the P fuse is the polarity fuse and the R fuse is the register fuse. P = 5 R = 59 P = 5 R = 5 P = 5 R = 53 P = 54 R = 55 P = 5 R = Synchronous Set (to all registers) POST OFFCE BOX 5533 DALLAS, TEXAS 755 5

6 TBPALV-M HGH-PERFORMANCE MPACT-X PROGRAMMABLE ARRAY LOGC CRCUTS SRPSB JUNE 99 REVSED APRL output logic macrocell diagram Output Logic MUX AR R = 3 D C From Clock Buffer SS S G 3 MUX S G S AR = asynchronous reset SS = synchronous set POST OFFCE BOX 5533 DALLAS, TEXAS 755

7 TBPALV-M HGH-PERFORMANCE MPACT-X PROGRAMMABLE ARRAY LOGC CRCUTS SRPSB JUNE 99 REVSED APRL R R D D C C S S = S S = S = S = REGSTER FEEDBACK, REGSTERED, ACTVE-LOW OUTPUT REGSTER FEEDBACK, REGSTERED, ACTVE-HGH OUTPUT S = S = S = S = /O FEEDBACK, COMBNATONAL, ACTVE-LOW OUTPUT /O FEEDBACK, COMBNATONAL, ACTVE-HGH OUTPUT MACROCELL FEEDBACK AND OUTPUT FUNCTON TABLE FUSE SELECT S S FEEDBACK AND OUTPUT CONFGURATON Register feedback Registered Active low Register feedback Registered Active high /O feedback Combinational Active low /O feedback Combinational Active high = unblown fuse, = blown fuse S and S are select-function fuses as shown in the output logic macrocell diagram. Figure. Resultant Feedback and Output Logic After Programming POST OFFCE BOX 5533 DALLAS, TEXAS 755 7

8 TBPALV-M HGH-PERFORMANCE MPACT-X PROGRAMMABLE ARRAY LOGC CRCUTS SRPSB JUNE 99 REVSED APRL absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, V CC (see Note ) V nput voltage (see Note ) V Voltage applied to disabled output (see Note ) V Operating free-air temperature range C to 5 C Storage temperature range C to 5 C NOTE : These ratings apply except for programming pins during a programming cycle or during a preload cycle. recommended operating conditions MN NOM MAX UNT V CC Supply voltage V V H High-level input voltage 5.5 V V L Low-level input voltage. V OH High-level output current ma OL Low-level output current ma t w Pulse duration Clock high or low 5 Asynchronous Reset high or low ns nput 7 t su Setup time before clock Feedback 7 Synchronous Preset (active) 7 ns Asynchronous Reset (inactive) t h Hold time, input, set, or feedback after clock ns T A Operating free-air temperature 55 5 C POST OFFCE BOX 5533 DALLAS, TEXAS 755

9 TBPALV-M HGH-PERFORMANCE MPACT-X PROGRAMMABLE ARRAY LOGC CRCUTS SRPSB JUNE 99 REVSED APRL electrical characteristics over recommended operating free-air temperature range PARAMETER TEST CONDTONS MN TYP MAX UNT V K V CC = 4.5 V, = ma. V V OH V CC = 4.5 V, OH = ma V V OL V CC = 4.5 V, OL = ma.5.5 V OZH V CC = 5.5 V, V O =.7 V. ma OZL V CC = 5.5 V, V O =.4 V. ma V CC = 5.5 V, V = 5.5 V ma H V CC = 5.5 V, V =.7 V 5 μa CLK. L V CC = 5.5 V, V =.4 V ma All others. OS V CC = 5.5 V, V O =.5 V 3 9 ma CC V CC = 5.5 V, V = GND, Outputs open ma C i f = MHz, V = V 5.5 pf C o f = MHz, V O = V pf C clk f = MHz, V CLK = V 7 pf All typical values are at V CC = 5 V, T A = 5 C. Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second. V O is set at.5 V to avoid test problems caused by test equipment ground degradation. switching characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER FROM (NPUT) TO (OUTPUT) TEST CONDTON MN MAX UNT f max External feedback 33.3 MHz t pd, /O /O R = 39 Ω, ns t pd, /O (reset) Q R = 75 Ω, 5 ns t pd CLK Q See Figure 4 5 ns t en, /O /O, Q ns t dis, /O /O, Q ns f max (with feedback) = t su t pd (CLK to Q).Verification of t su and t pd (CLK to Q) may be used to verify expected performance. POST OFFCE BOX 5533 DALLAS, TEXAS 755 9

10 TBPALV-M HGH-PERFORMANCE MPACT-X PROGRAMMABLE ARRAY LOGC CRCUTS SRPSB JUNE 99 REVSED APRL preload procedure for registered outputs (see Notes and 3) The output registers can be preloaded to any desired state during device testing. This permits any state to be tested without having to step through the entire state-machine sequence. Each register is preloaded individually by following the steps given below: Step. With V CC at 5 V and pin at V L, raise pin 3 to V HH. Step. Apply either V L or V H to the output corresponding to the register to be preloaded. Step 3. Pulse pin, clocking in preload data. Step 4. Remove output voltage, then lower pin 3 to V L. Preload can be verified by observing the voltage level at the output pin. Pin 3 Pin t d t su t w t d V HH V L V H V L V H Registered /O nput Output V L V OH V OL Figure. Preload Waveforms NOTES:. Pin numbers shown are for the JT package only. f chip-carrier socket adapter is not used, pin numbers must be changed accordingly. 3. t d = t su = t w = ns to ns. V HH =.5 V to.75 V. POST OFFCE BOX 5533 DALLAS, TEXAS 755

11 TBPALV-M HGH-PERFORMANCE MPACT-X PROGRAMMABLE ARRAY LOGC CRCUTS power-up reset SRPSB JUNE 99 REVSED APRL Following power up, all registers are reset to zero. The output level depends on the polarity selected during programming. This feature provides extra flexibility to the system designer and is especially valuable in simplifying state-machine initialization. To ensure a valid power-up reset, it is important that the rise of V CC be monotonic. Following power-up reset, a low-to-high clock transition must not occur until all applicable input and feedback setup times are met. V CC 4 V 5 V t pd ( ns typ, ns MAX) Active High Registered Output State Unknown.5 V V OH V OL Active Low Registered Output State Unknown.5 V V OH V OL t su CLK.5 V.5 V V H V L t w This is the power-up reset time and applies to registered outputs only. The values shown are from characterization data. This is the setup time for input or feedback. Figure 3. Power-Up Reset Waveforms programming information Texas nstruments programmable logic devices can be programmed using widely available software and inexpensive device programmers. Complete programming specifications, algorithms, and the latest information on hardware, software, and firmware are available upon request. nformation on programmers capable of programming Texas nstruments programmable logic is also available, upon request, from the nearest T field sales office, local authorized T distributor, or by calling Texas nstruments at (4) POST OFFCE BOX 5533 DALLAS, TEXAS 755

12 TBPALV-M HGH-PERFORMANCE MPACT-X PROGRAMMABLE ARRAY LOGC CRCUTS SRPSB JUNE 99 REVSED APRL PARAMETER MEASUREMT NFORMATON 5 V From Output Under Test C L (see Note A) S R R Test Point LOAD CRCUT FOR 3-STATE OUTPUTS Timing nput Data nput nput n-phase Output t pd t pd t su Out-of-Phase Output (see Note D).5 V.5 V t h.5 V VOLTAGE WAVEFORMS SETUP AND HOLD TMES VOLTAGE WAVEFORMS PROPAGATON DELAY TMES 3 V 3 V.5 V.5 V t pd V OH.5 V.5 V V OL t pd V OH.5 V.5 V V OL 3 V (see Note B) High-Level Pulse Low-Level Pulse Output Control (low-level enabling) Waveform S Closed (see Note C) Waveform S Open (see Note C) t en t en.5 V.5 V t w.5 V.5 V VOLTAGE WAVEFORMS PULSE DURATONS.5 V.5 V t dis.5 V t dis.5 V 3 V 3 V (see Note B) 3 V (see Note B) 3.3 V V OL +.5 V V OL V OH V OH.5 V V VOLTAGE WAVEFORMS ABLE AND DSABLE TMES, 3-STATE OUTPUTS NOTES: A. C L includes probe and jig capacitance and is 5 pf for t pd and t en, 5 pf for t dis. B. All input pulses have the following characteristics: PRR MHz, t r and t f = ns, duty cycle = 5%. C. Waveform is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform is for an output with internal conditions such that the output is high except when disabled by the output control. D. When measuring propagation delay times of 3-state outputs, switch S is closed. E. Equivalent loads may be used for testing. Figure 4. Load Circuit and Voltage Waveforms POST OFFCE BOX 5533 DALLAS, TEXAS 755

13 TBPALV-M HGH-PERFORMANCE MPACT-X PROGRAMMABLE ARRAY LOGC CRCUTS TYPCAL CHARACTERSTCS SRPSB JUNE 99 REVSED APRL SUPPLY CURRT vs FREE AR TEMPERATURE PROPAGATON DELAY TME vs SUPPLY VOLTAGE Supply Current ma CC V CC = 5.5 V V CC = 5.5 V 9 4 V CC = 5 V V CC = 4.75 V V CC = 4.5 V T A Free Air Temperature C Propagation Delay ns t pd 4 t PHL (, /O to O, /O) t PHL (CLK to Q) t PLH (, /O to O, /O) t PLH (CLK to Q) 4 T A = 5 C R = 3 Ω R = 39 Ω C L = 5 pf Outputs Switching V CC Supply Voltage V Figure 5 Figure Propagation Delay ns t pd 4 PROPAGATON DELAY TME vs FREE AR TEMPERATURE t PLH (, /O to O, /O) t PHL (CLK to Q) t PHL (, /O to O, /O) 4 t PLH (CLK to Q) V CC = 5 V R = 3 Ω R = 39 Ω C L = 5 pf Outputs Switching T A Free Air Temperature C Propagation Delay ns t pd 4 PROPAGATON DELAY TME vs LOAD CAPACTANCE t PLH (, /O to O, /O) t PHL (, /O to O, /O) t PHL (CLK to Q) t PLH (CLK to Q) V CC = 5 V 4 R = 3 Ω R = 39 Ω C L = 5 pf Outputs Switching C L Load Capacitance pf Figure 7 Figure POST OFFCE BOX 5533 DALLAS, TEXAS 755 3

14 TBPALV-M HGH-PERFORMANCE MPACT-X PROGRAMMABLE ARRAY LOGC CRCUTS SRPSB JUNE 99 REVSED APRL TYPCAL CHARACTERSTCS PD Power Dissipation mw V CC = 5 V R = 3 Ω R = 39 Ω C L = 5 pf T A = C T A = 5 C POWER DSSPATON vs FREQUCY BT COUNTER MODE T A = 5 C 3 5 F Frequency MHz 7 Propagation Delay Time ns t pd 4 PROPAGATON DELAY TME vs NUMBER OF OUTOUTS SWTCHNG t PHL (, /O to O, /O) t PLH (, /O to O, /O) t PHL (CLK to Q) t PLH (CLK to Q) V CC = 5 V R = 3 Ω R = 39 Ω C L = 5 pf T A = 5 C Number of Outputs Switching Figure 9 Figure 4 POST OFFCE BOX 5533 DALLAS, TEXAS 755

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TIBPAL22V10-10C HIGH-PERFORMANCE IMPACT-X PROGRAMMABLE ARRAY LOGIC CIRCUITS

TIBPAL22V10-10C HIGH-PERFORMANCE IMPACT-X PROGRAMMABLE ARRAY LOGIC CIRCUITS TBPAL22V-C HGH-PERFORMANCE MPACT-X PROGRAMMABLE ARRAY LOGC CRCUTS Second-Generation PLD Architecture High-Performance Operation: f max (External Feedback)... 7 MHz Propagation Delay... ns Max ncreased