For example, if the op amp has

Transcription

1 Op Amps in Line-Driver nd Rece iver Circllits. Prt 1. Video pplictions by W it J u ng INTRODUCTlON* Signl integrity is most-often compromised in the between ponions of electronic interconnections systems. Audio nd video signls hve to be trnsmitted from their plce of origjn to nother loction or system with no loss of fidelity. To pproch this idel, creful nention must be pid to lyout nd grounding tech niques, the electricl nd physicl conftgurtion of the driver nd receiver stges, the noise nd distortion performnce of these stges, nd the medium: in the cse of wired interconnections, the ctul trnsmission line(s). Figure 1.. Op mp drives cpcitive lo d. Success of ppli ction depends on op-mp properties. b. Step response of AD705 with l-nf l od. Ccomp For exmple, if the op mp hs 0 pf. c. Ccomp n 200 pf. open-loop pbse sh ift of 1 35 ner its unity-gin frequency, nd if Ro nd CL produce 45 phse shift in tht sme vicinity, severe peking or even oscilltion will result. The follower connection tends to mximize this ten Here we look t the design considertions for building line-driving dency, becuse it involves 1 00% feedbck. This point is illusuted nd -receiving circuits- nd pplying them for high performnce by the pulse response (Figure l b) of in video systems. A future rticle will discuss how the consider OP-97 nd AD705 fmilies, driven in this circuit with 200-mV n mplifier typicl of the tions differ for udio systems. p-p input signl. In this cse, there is considerble overshoot nd UNE DRIVERS-GENERAL CONSIDERATIONS ringing, but no sustined oscilltion. It's usully difficult to design stges to drive lines nd remote These mplifiers hve tenninl (pin 5) tht cn be used option lods, becuse they must often hndle high CWTent nd/or voltge lly for overcompenstion. When dditionl cpcitnce is con without degrding stbility or bndwidth. Current nd voltge nected from this node [0 ground, the mplifier's crossover (unity requirements re firly strightforwrd ; mny IC nd discrete gin) frequency is reduced, nd so is the phse shift t tht devices nd circuits re vilble on the mrket in with suitble frequency, restoring power specifictions. But it is no simple mner ro use them to cpcitnce dmps the ringing substntilly (Figure lc). drive lines with dequte bndwidth nd predictble c response nd dynmic stbility - so we will first consider these issues. It is not esy to chieve dequte perfonnnce with cpcitive loding - key design issue becuse most lines hve substntil cpcitnce. Though chieving stbility often involves complex circuitry nd reduced performnce, stndrd techniques exist for stbilizing drivers fced with cpcitive lods, nd they cn be implemented in resonbly direct fshion. The bility to mke choices nd trdeoffs cn help in chieving efficient designs. Cpcitive loding should be looked t in ny driver-circuit ppli ctiod, however benign. Signl led cpcitnce cn build u p quick.1y, even for long runs O D single PC bord. Cpcitive loding of off- bord" circuits should be evluted crefully to the " degree possible. Generl-purpose drivers, with OUtputs intended for the unknown or poorly defmed lod cpcitnce of unspecified destintions in the outside world, must be considered worst cse nd bulletproofed by pproprite (over-) design. Overcompenstion A follower-connected op mp with cpcitive lod is the clssic cse of potentil stbility disster ( Figure l ). A simple circuit, which could be embodied with most op-mp types, it is ner worst-cse exmple of stbility-sensitive design. It is likely to respond to pulses with severe overshoots nd ringing, if not outright oscilltion. Wht it ctully does depends on the op mp's gin- nd phse mrgins with the lod in plce, function workble phse mrgin. Here, 200 pf of Op mps tht permit custom compenstion cn be used in this wy to improve stbility, but-in ddition to the inherent bnd width reduction ssocited with most pproches to reducing cpcitive lod effects- there is further downside. The mplifier used must llow ccess to the internl compenstion node, n uncommon feture tody mong precision op mps, such s the OP-07 or AD707. W hile this is useful option when vilble, one must sty flexible nd be wre of ll options. Higher closed-loop gin (reduced feedbck) will lso help stbil ity, fouowing generl feedbck theory, becuse phse tg is gen erlly lower t the lower unity-loop-gin frequencies. Therefore, inveners or higher-gin followers (with ttenuted inputs, if nec essry) will hve less tendency to oscillte or pek. Sensitivity to cpcitive loding is not unique to generl-purpose feedbck mplifiers (Figure 1). "Open-loop" IC buffers nd dis crete followers cn oscillte, given the right combintion of source impednce nd loding. I Like op-mp feedbck circuits, they must be isolted from cpcitive lods nd stbilized. Compensting for Cpcitive Lods Pssively The simplest fix for cpcitive loding (Figure 2) is with pssive, or "open-loop" circuitry: to isolte the mplifier-circuit's output from the cpcitive lod, using series resistor (outside the feed bck loop). The lod on the mplifier looks like resistnce, R.\(, t frequenci bove 1I(21TR. L); lthough it slightly reduces the of the op mp's open-loop response nd output impednce (Ro). mplifier's open-loop gin, it does not introduce dditionl loop *Dlll sheets for!he devices mentioned in this rticle will be found in!he Anlog DeviC'e$ Amplift" Rtferenct Mnul, vilble frtt. Circle 2 ever, che resistnce, Rx, cuses voltge drop proportionl to Anlog DIlogue 26-2 (19921 phse Jg, nd th e circuit's stbility is l s sensitive to CL ' How 13

2 lod current; it must be smll compred to 2:: I ill, produces smll «I -db) e rrors. The buffer mplifier specs must be consis tent with the lod re quirements -generlly for "musculr" ou tput stge. Tble 1 * lis ts slient fetures o f voltge-input (s distinguished from rrn simpednce] op mps suitble for line driving by virtue of their high speed nd current output, nd low output resistnce. The AD845 in the exmple of Figure 2 hs minimum gin of 100 V/mY driving lods of 500 n nd more, nd FET input stge with less thn l -na bis current. It below the bsic 1 6-MHz bndwidili of the AD84S op mp. In RL to mirumlze l ow-freq uency error. R x is lypic.lly n, which, for lods cn deliver up to essence, the bndwi dt h will be limited [0 1/([21fCL(RxIIRL»). Loss of slew rte: The cpcitive lod cn limit the slew rte (SR). In generl, the inherent SR of the mplifier will be reduced to 10 (MD./CL volts per second. For exmple, while the ADS45 hs bsic SR of 100 V/ILS, the ::t 50-rnA output-current limits cuse it to fll to bout SO V/}l-s with CL 1 nf. The SR is subje ct to the uncertinly of ilie mplifier's short-circuit current limit, which usully vries inversely with te mperture. This generl limittion will pply fier nd 10 ny cpcitively loded mpli cute in high-51ew-rte devices. is prticulrly z 50 rna of output with n open-loop output impednce of 5 n. The generl technique of Figu re 2 cn be used with most mpli Tble 1. Voltge Input Op Amps SuitbJe for Une Driving on complementry bipolr (CB) process)-provides more cur Device Ro (fl) AD8IS AD840 AD84J AD842 AD843F ADS45F OP-42F OP-64 OP-27S I BW SR (V/p.s) (MHz) SOO 400 4OO1 l ] ] Vs (Vjll to (ma) ::90 (min) 5 0 (min) :: 1 00 (min) 5 0 (min) 50 :: S O 30 :: 2. 5 to 18 : 5 to :: I S 5 to 18 ::S to : d8 5 to :: 18 :s to : 18 :8 to : to.:t 1 8 :5 to :: :: 30 z fien. The higher-spee d, l OO-rnA-output AD842-mnufctured rent to lod, but it mu st be connected for closed- loop gin of t lest 2 VN. This cn gin by connecting be done without ffecting the low-frequency n pproprite "dummy" noise-gin resistor between the mplifier's z inputs. (R-C networks cn lso be used, voididg n increse in OUtPUt dc offset -but possibly incresing settli ng time. ) With trnsimpe<ince mplifiers, even higher current drive is vil ble - up to :!: 1 50 ma, for the ADS l l,3 connected s shown in Figure 3. NOTES TO TABLE ' Dul device. 'Gin bndwidth product, listed t minimum stble gin of: A D 8 1 S & AD842 2, OP 64 5, AD IMximuro rnges shown. FFET input device. becuse the ADS l l is trnsimpednce mplifier. When they re For low-impednce lods, such s 500 n for 2, R F is set t 750 nj for simple voltge fouower, R/N is left open. To correct for the output ttenution. R/N is 30.9 kn. tnce, This circuit, similr to Figure 2, i s configured differently for gin, used s non-inverting gin stges, the vlue of RF is fixed, nd R/N 's vlue is set to djust the gin. For the conditions of Figure Rv series resis Rx, of SO n produces 9% gin error, which often requires correction for unity overll gin. either loclly or elsewhere in the Unlike voltge-input op mps, trnsimpednce mplifiers prefer be chieve d loclly by using feedbck resistors in n optimum vlue of RF for flt frequency response- function system. It cn ilie sme rtio, RxlRL; ccurcy of ilie overll gin will depend on of supply voltge, closed-loop gin, nd device lype. For the whether RL is constnt. If the circuit is lred y connected for A t gin of + I, it is 750 n. With other devices, the RF (I + RxlRL) gin increse. The ADS l l lso permi t s RF to be incresed to improve cpcitive gin, the re quired correction mens revising resistnce vlues for vlue specified on the device's dt sheet should be used. This series-rx cpcitive-lod compenstion technique, though lod-hndling for generlly effective nd quite simple, does hve drwbcks : With Loss of gin (or c uses gin ccurcy) : used with fixed-gin stge, it gin/power loss, which will vry with loding. If the lod is known nd stble, the low-frequency gin error-s well s correspondidg cble losses-cn be optionlly compensted. Loss of bndwidth: This technique (like lmost ll oiliers to Rx Rx 0, but wiili less-flt frequency response. 12 n, s shown, response is optimized into I -nf lod4. The ADS l I hs mjor benefits in this ppliction, sin ce the bndwidili is incre sed (over Figure 2) to MHz. The ma sho rt-c i rcu it output drive of the ADS l l incre ses the circuit's S R to I SO V/IJ.S (much less thn its unloded 2500 V/IJ.S spec, but much more thn tht of Figure 2). isol te cpcitive lods) lso cuses loss of frequency response, Trnsimpednce mplifiers, used s in Figure 3, tend to hve loss likely to be poo rer dc nd low-frequency performnce thn conventionl op serious with high-speed mplifiers. For this exmple, the e ffective bndwidth will Rw Iku RF r.illr.- J,"',,-_---, I 'V' :Il O.,.,F V.. o { be bout 3. 5 MHz, well NOTES: I. FOR GA'N COMPEN SATION. LET A'H Rl 1.!!L.!!JI... t3db :. 2.,C. (R", RJ mps. Common-mode errors cn be minimized by u s ing the A,. 3D. ku R, 7SOU r.l/ r ---- I 'V' V,. o l oo" FI 25V -15V Figure 2. Open-loop series resistnce isoltes cpcitive lod i n vo ltge-i nput op- m p ci rcuit. 14 Anlog Dilogue 26-2 (19921

3 mplifier s n invener, rther thn s follower (whe n poss ible ), or s high-current buffer with nother op mp in composite stge (Figure 7 below). Finlly, the ADS46 is trnsimpednce op mp with precision dc chrcteristics. Tble 2* illustrtes the specs of vriety of trnsimpednce op Some cvets ssocited with internl compenstion: Loss of bndwid t h : As with pssive compenstion, bndwidth decreses (depending on the ppliction) s the device slows down to prevem oscilltion s lod current flows. Signl-level dependency ; The compenstion network hs its mps tht re relevnt to use s line d rivers. Similr RF nd R/N gretest effect when enough output current flows to produce selection considertions to those discussed bove would pply voltge cross with other trnsimpednce mplifiers when used in this circui t. the network on speed is much less, Tble 2. Trnsimpednce Amplifiers SuitbJe for line Driving Device RF (nr] BW (MHz) SR (V/lJ.s) 10 (0lA) VS (V'}S] [ ::':: 7 5 ADS I } ADS44z :,: 80 ADS46l lk 450 :':: 65 AD96}7 4tl2 1 4tlO ::: 60 ::,:: :,: 60 ::,:: /-45 ::: 5 to :': ::':: 50 :,:5 to :': 1 8 AD Ik OP S25 OP k [0 :!: ctions. Though it doesn't mke mplifiers such s the AD ::,:5 to ::: 1 8 of distort i o n chieved by otherwise comprble mplifiers (some problem, the design is not freed from other instbility from strys). These still need to be considered - s for ny ppliction. Cpcitive-Lod Compenstion simpler pproch i s [0 use n op mp In sum, internl cpcitive lod compenstion cn be gret utility feture, mking pplictions esier to get up nd run ning. But when the limits of performnce re pushed, other mp l i fie rs, nd more Internl designed t o hndle cpcitive lods without requiring externl compenst ion. Tble comprehensive pproches, my be better choices. Tble 3 lists some mplifiers with internl cpcitive lod compenstion. 3* lists number of vilble mplifiers with this internl feture. Tble devices, pn of the mplifier compenstion network is cpcitor, to feed fonvrd round unity-gin output stge. In norml circuit opertion, t his cpcitor hs little effect; bu t with cpcitive loding nd lrge signls, current is drwn from drop ppers cross (he CF network, AD827 I AD829 pcitnce to the device's internl compenstion, effectively slow AD844 (V/J.ls) 10 (ma) ::,: :,: ::':: 80 NA1, ) 50 AD847 AD848 SR BW (MHz) Device AD8! 7 ccompnied by current (low. This in effect dds dditionl c ing the mplifier's response. 3. Amplifiers with Internl Cpcitive Lod Compenstion Suitble for line Driving Typicl of such mplifiers re the AD847 nd A D 8 l 7. In these voltge The pproch cn help gretly, but it is not pnce. Tho u g h n op mp of t his type my solve the loding ' DI SA B L E pin vijble. the output nd exmples will illustrte this poim). No "free lunches.' '': sources (such s input cpcitnce, feedbck nd PC-bord 'Compenstion node v il ble. 'Dul device. 'Optimum vlue will vry wilh supply voltge. 'Mximum " lues shown. Cp, connected Distortion : Becuse the circuit is bsed on nonliner principle, or ADS 1 7 unusble for video; i t precludes the very lowest levels NOTES TO TABLE A greter ringing my lods; this fctor impcts mplifier performnce in video ppli ::':: I S S to 1 8 :!: S so ctully be possible for some circuits for low-level signls. the internl network ffects distortion nd the bility to drive A DS I 0 1 S CF' Conversely, t smll signl levels the effect of 1 75(31 60 Vs (V)IS] ::':: 2. 5 to ::':: 1 8 :!o S to 1: 18 :!o S to :!: 18 :!o S to :t :!: 5 to :!: :!: 5 10 :!: IS 18 ::':: 5 10 :!: IS AD846 SO 450 ::':: 65 OP / -45 IS :>: 5 10 ::':: IS NOTES TO TAB L E ' Dul dc\ icc. 'BJndwid lh \'rie's wilh compens.ll ion. 1 00pF LOAD li.rc-d t minimum,tble gin 0(: A , (or ADS19 (, G 20, BW 50 MHz (cn Ix compensled (or G I ). 'Cp 100<1 comrcnstion optionlly vilble externlly (see d ( sheet). )"i3ximum rnges shown. 'Gin bndwidth product. Externl Cpcitive lod Compenstion 1000pF LOAD Figure 4. Lrge-signl Externl, or "in-the-loop" compenstion is compenstion for cpcitive lod (AD847. AD817). Figure 4 shows typicl lrge-signl response (or I OO-pF nd I OOO-pF lods. The smll cpcitive lod (top) llows fst OUtput swings, while the lrger cpcitnce (bottom) slows t he output rte of ch nge but wjthout instbility. The compenstion is dp, is ccurte; t he isollion principlly by the circuit's gin resistors (ssuming dequte op mp gin). Unfortuntely, like other techniques discussed Ihus fr, it lso reduces bndwidth nd slew rte. Figure S illust rtes the principle. the output moves more quickly. This results in simpler pplic Figure t ions ; stbility issues due to output cpcitive loding rise less 26-2 (1992) opertion. It frequency gin ccurcy, indepe ndent of t h e lod nd limited gin-of-2 stge, resistor Anlog Dilogue It is resistor is included within dc feedbck loop for excellent low tive, coming into ply s needed, s either loding is incresed or freq uently, llowing ttention to other detils. most flexible nd flexi ble; in p ri nc i ple, i t pplies to ny unity-gin stble op mp, in inverting or noninverting response of mpli fiers w i th internl [he ccurte generl wy to isoltdcompenste cpcit ive lods. 2, the Rx In Ihis ci rcu i t, noninvert i ng isol t es the cpcit ive lod CL ' feed bck return is t ke n from the lod side U n l i ke of R.\., Dt for lhe dcvices mcl1lionoo in this rticle' will be found in the A nlog Devices Amplifier Reference Mnil/. Circlc 2 1 1;

4 enclosing it within t he loop; t his utomticlly corrects gin errors cused by lo d ing 3t t h e lower frequencies. The gin expression is CdC,... This compenstion technique is good one to tune t his like tht of stndrd noninverting op mp stge. 2.5kll R'M. m u m, the displyed response (not shown) tends towrd s i ncresed overshoot for higher C,/Cn nd towrds overdmped, for lower circu it for gurnteed stbili ty. If the mximum CL is known, the 2.5kU RF stge cn be t uned to ccom modte i t, nd lower CL vlucs mke it slower nd more stbk. A relted unity-gin inverting circuit is shown in Figure 5b. I t uses the sme vlues nd hs the sme noise gin s the circui t of Figure S. 6b sholvs the well-con t rolled pulse response for the sme 200-mV p-p OUtput level nd l-nf lod cpcitnce. When tilored properly, t h e output nd compenst ion networks cn infl uence bndwidth nd SR more thn the device used. For exm pk, A D845 nd OP-27S, tested in these circuits, gl'e smll signl results qu ite similr 10 those shown in 6 nd 6b. \Vhen the required current output exceeds given op mp's specs, n " inside-the-loop" buffer cn be dded. For exmple, Figure 7 shows non-inverting ppliction - l i ke Figure 5 in concept - where n A D8 1 1, connected s unity-gin buf(er, is inter posed between t he U l nd the lod to boost the current output u p to F i gu re 5.. l n s i de-the-ioop com penstion of non- i nvert i n g :!: 1 00 ma ( ::,: 1 50 ma pek). U2 dri ves t h e lod - i nsted of the ou t put stge of the UI mpl i fie r. stge u sing vo ltge - input op m p. b. I nverting version o f (). Dynmicll ', cpcitor CF provides compenstion for the ddi tionl lg int roduced by the R."CL combint ion. For given set. RIH 2.S H R, 2.SkU t ktl of vlues, C,.. cn be dj usted to cncel much of the destbilizing effect of CL nd p rov ide well-dmped step response, countering t he tendency towrds overshoot, ringing or oscilltion. Bndwidth is reduced; the closed loop bndwid t h of t h i s stge is function of RF nd Cp, s well s Rx nd C,., The vlue chosen for Rx is not highly critic l, bu t it should be kept smll to void degrding power output nd bndwidth; the stge cn be t uned with vlues in the rnge of ohms. The optimum vlue for CF is function of R.,., CL nd the gin resistors; with fixed \'lues for RI" R/N nd R:(> it will trck CL ' W h i le severl references suggest proccdures for predicting CnP. 6) prcticl pp roch is to select close nominl vl ue for Cl" then djusl it for optimum pulse response in the finl circuit lyout. 7 This pproch, tking into ccount ddit ionl prsit ic cpcitnces, ws used in the exmples discussed. Figure7.. I n s i de-the- Ioop compenstion of buffered non i nverting stge using ::': 100-mA cu rrent-feedbck op-mp s To minimize sensitivity 10 stry cpcitnce, it helps to keep the unily-g i n buffer. b. Sml l-signl respon se. c. Lrge-signl vlues of RF nd R/N low. The resu l t ing higher vlues of Cl" response. typiclly >20 pf, will be more predictble nd stble. Cr is best While the bsic compenstion components function s before, Rx mde up of n NPO cpcitor in prllel with n NPO trimmcr. is decresed to JO ohms to llow greter lods to be d riven, in this Optionlly, once the optim u m vlue is ve ri fied in finl lyout, cse 4.7 nfi1499 ohms. Figures 7 b nd 7c show the circuit's re single fixed vlue cn be used. The following exmples use 1 5 -V power supplies (bypssed s noted in t he sidebr). Figure 6 sholvs the well -controlled response of the circuit of Figure S - with n OP-42 driving l - n F lod -to 200-mV POp smll-signl pulse. As CF (or Cl.. ) is vried wy from this opti- sponse to smll- nd l rge signls. Becuse of slew-relted Jg, the circuit cnnot be identiclly compensted for both lrge nd smll sig nls; lvith CF djusted for slightjy overcompensted smll signl response, the lrge-signl response shows j ust smll over shoot. The I SO-mA current limit of the ADS I I cn slew the 4. 7-nF lod t bout 30 V/f.Ls. Figure 8 shows buffered inverting circuit with the sme lod ing; smll- nd lrge-signl responses re seen in 8b nd 8c. As before, the smll-signl response is well controlled; the lrge signl response is sligh tly less dmped, due to the slew lg. These externl compenstion tech niques for op mps re widely pplicble; with proper djustment, [hey provide compenstion Figure 6.. Sm l l -signl response of Figure 5 b. Sm l l signl response of (5b). 16 without much reduction of bndwidth nd SR. This technique cn be used with vriety of devices, buffered nd unbuffered. (colllijlued Anlog Dilogue 011 pge 18) 26-2 (1992)

5 CHOOSING IIC AMPLIFIERS FOR HIGH PERFORMANCE BUFFERING Buffer stges re widely used in nlog circuits nd systems to :!: 70 ma. When stnding lone, it requires no externl circuitry, preserve signl ccurcy by unloding high-impednce circuits except for offset nuljjng- i f desired -nd the usul bypssing. - nd to drive difficult lods. Buffer stges re typiclly config ured s voltge followers-non-inverting unity- (or low) voltge gin stges, with high current gin. For exmple, this gene.rl purpose buffer circuit works with mny rc mplifiers, with or without overll loop feedbck -s needed. 1IIu INPUT Cl O ' t.' C. 7 + ""F medite nswer to the speed/ccurcy question. As rule, they perform much beller lhn voltge-input devices for high-speed nism hs much less of tendency towrds slew limiting nd dosed-loop bndwidth chnges much less with incresing gin. So, trnsimpednce mplifiers dynmiclly re more suitble OUTPUT thn conventionl op mps for follower-type buffers. Trnsimpednce mplifiers generlly hve better gin ccu rcy C2 thn open-loop designs. In contrst to I % gin errors for some open-loop designs, good trnsimpednce buffer cn hve.00:,,/.s;vlo 2SV _t SY '00..1', 25Y -5ov 10 -UY Trnsimpednce (or current-input) mplifiers provide n inter pplictions. The trnsimpednce mplifier's feedbck mech WIDEBAND GENERAL PURPOSE BUFFER R, TRANSIMPEDANCE AMPLIFIER BUFfERS unity-gin error of the order of 0. 1 % ( gin of ) with lods well below I kh. Higher gins re lso vilble by pproprite Avilble lc forms of buffers re generlly "open-loop"-non choice of resistnce rtios. (Rn,' feedbck-types. They typiclly operte with slew rte (SR) of A t rnsimpcdnce mplifier s unity-gin follower few hundred V/fLS, gin-bndwidth of up to 1 00 MHz, lod in the buffer circuit shown bove llows mximum flexibility for drive down to 1 00 ohms t current levels of up to 1 00 ma, with low distortion nd stble gin. DC performnce (gin ccurcy, open) gin nd lod drive. This circuit must use feedbck resistor (RI.-), specific for given device (Tble 2). To configure the R,.v' offset nd drift, nd input impednce) is often secondry buffer for gins greter thn unity, dd n pproprite which cn limit their overll utility (or require dc stbiliztion). The AD8! 1, especilly useful for driving hevy lods, due to its Op AMP BUFFERS high output current, is optimum from speed/power point of DC nd low frequency specs.re the strength of conventionl (vs. trnsimpednce) op mps. They hve low offset, bis cur rent, nd common-mode errors (including power-supply sensi tivity). However, speed is reltively poor becuse of limited slew rte nd bndwidth. Tbe limits become most CUle when con view, with 2500 V/fLS SR, ± 1 00-mA output current, nd more thn 1 00 MHz of bndwidt h. The gin error of n A D8! 1 voltge follower, with l -kn Rp will be 0.067%. The dc perfor mnce is still ttrctive; Input offset voltge of the A D8 1 1 is typiclly 0. 5 mv; bis current is 2 fla. ventionl op mps serve s unity-gin voltge followers. DC performnce of the bove circuit of is lso limited by the Nevertheless, selected devices re notble for providing u seful CMR nd PSR of the device: db for the AD For combintion of specs (see Tbles). Of these, perhps the best criticl simtions, the AD846 cn be used. It bs 1 25 db of overll utility is provided by the ADS I 7 or ADS45. With con CMR nd PSR nd n R-r of 200 M H. [n t.he sme circui t, gin R F s error of the A DS46 will be %, representing two orders-of ventionl op mps, the bove buffer circuit does not need follower, but cn use borh RF nd desin.-d. Interestingly, the AD8 1 7, with RIN., RI'" should gin be mgnitude improvemen t. I k D, s shown, GEN RAl NOTES ON BUFFER STAGES mintins gin fltness up MHz in this circuli. Regrdless of which IC is employed, close ttention should be In generl, besides the ultimte slew rte due to limittions on g iven to minimizing prsitics in buffer stges, t input, output, the chrging rte of internl cpcitnces, the output-current nd supply terminls. Buffers should follow the rules for physi limited slew rte of this buffer (nd those discussed below), cl construction of high-speed circuits. A solid, hevy copper operting into cpcitive lod with short-circuit current, ground plne should be used, nd circuit lyout should be 1",." will be s discussed with the circuit of Figure 2. compct, with low cpcitnce round high-impednce nodes. OPEN LooP BUFFERS In contrst to conventionl op mps, open-loop buffers nd Signl runs nd grounds should be lid out with signl coupling nd lod-current flow in mind. l o 11 rrnsimpednce, or current-feedbck, mpli.fiers operte without I f the lod will not be source-mtched to cble with imeml slew-rte limittions. Not needing overll lg compen o h m termintion for stion, open loop buffers tend to be much fster. The trditionl cpcitive loding (see text). Some mplifiers my require n trdeoff here hs been speed for ccurcy, which tends to be input prsitic suppression resistor worse without corrective loop feedbck. The BUF-0 3, for exm Power supplies should be well bypssed close to the high-current ple, hs no loop-feedbck corrective gin mechnism (lthough lhe novel hybrid output stge does minimize dynmic errors).9 More-recent bipolr buffer designs, such s the AD9620 nd AD9630, chieve excellent ccurcy of u p to VN, but R,'o(> then Rx should b e 1 0 n, to isolte (R I ) (see device dt sheets). IC pins. Low-inductncellow ESR rf bypss cps (Cl ' CJ) should be used right t the pins. These re O. I -flf surfce mount chips (or other low-inductnce types). For driving high pek-current lods, these bypsses should be ugmented by with proprietry closed loop topology. short-led high-cpcitnce, low-esr electrolytics The strength of the BUF-03 lies in its very low input current flf). As they crry 'trnsient currents, tbey should be ( I SO rted for high frequency (viz., switching-supply types). p_a), low offset volt.ge (2 mv), nd high output current of Anlog Dilogue 26 2 (1992) (Cl' & C, -+ 17

6 DC power mngement nd dissiption re lso importnt with buffer les, which cn dissipte firly lrge power levels t light lods. For exmple, the ADS l l 's quiescent current drin is I S ma. So het sink should be used for supplies > ::t 12 V. To minimize power nd temperture rise, note tht video nd other low-volt.ge-swing pplictions cn use.::t V 'Supplies. For buffer circuits needing full ::t 15 V, use the lowest-possible-therml-resistnce pckge, nd dd n p proprite het sink (Thermlloy 2227 fo r the BUF-()3 or other TO-99 les, AAvid #580 1 for the ADS l l or other S-pin ICs). Becuse of this stge's very wide bndwidth, low phse shift, nd low OU'lput impednce. fst buffer cn either "stnd lone," s shown here, or serve s more-conventionl "inside-the loop" buffer, to minimize loding on high-pr-edsior mpli fier. For ny conventionlly rted-output mplifier this cn be 'Slient improvement ; it cn increse the liner output drive to ::t 100 ma, while mximizing linerity, preserving gin, nd r-educing distortion. The Tbles show number of mplifiers suilble for buffers. The circuit exmples cn be used s shown here; but plese lso note tht similr cpcitive-lod compenstion rchiteclures, wit h the vlues optimized for specific devices, re shown o n mny o f our op-mp dt sheets.. R'H 2.5kll RG..60A A.S9 7sv CASL.E V,. t V p-p O { Figure 9_ Imped nce-mtched l i ne driver with 7 5-D lod. (contillued from pge / 6) V,H When source nd lod impednces, R T nd R v re equl t o the nominl Zo, in this cse 75-ohms, the loding presented to RT t the input side of the line is 7S-fi re sis tnce. The line is nominlly flt in frequency response, within the tolernce of its trnsmission-lin e design prmeters. The mpli fie r sees n effec tive resistive lod of RT plus RL, in this cse ISO fi. The ttenu tion from mplifier output terminl to the lod is 2 : 1 ; system bndwidth is determined principlly by the mplifier. To deliver 1 V p-p to the l od, the mplifier output must be 2 V Pop (into 150 fi), requiring n mplifier gin (U I ) of 2 times. These systems hve the d vntge of wide bndwidth, but the low lod impednces my req uire considerble power for high output levels- twice s much s ppers t the lod. Also, U l must hve slew rte 2 x t h t required t the lod. Nevertheless, for low s ig nl leveis (sy, 2 V pop), this drive system is quite prcticl, R. 2.5kll chieving high performnce for well-chosen U I, such s the AD8 1 8 or the AD8 1 7 (more below). R. LINE DRIVERlRECEIVER CIRCUITS FOR VIDEO loll Video Une Receivers In high-speed cooununictions, the line-receiver stge ccepts Cl 4.7nF C, video informtion from n incoming trnsmission li ne, nd buff ers it for locl processing. Figure 10 shows typicl system to 75pF ccomplish this, single-ended driver t the input end of the coxil trnsmission line - nd principle, different il-input receiver. In differentil end-to-end tiosmission system would be best, but single-ended drive systems re covered here becuse of "" CO_ t "'--- their predominnce. As the digrm shows, noise between driver/ receiver grounds A nd B is rejected by the inherently high common-mode rejection (CMR) of the differentil video receiver. SINCI.E ENDED VIDEO ORtVER R A!...c: Figure 8.. I nverting ve rs i on of Figure 7. b. Sm l l -signl response. c. Lrge-signl response. V '; 1 V IO E O.. " SourceILod-Terminted Trnsmission-line System A hrdly perfect solution to the line-driving problem. Perhps the best nd most fool proof wy 10 drive long line (which would otherwise present substntil cpcitive lod) is 10 R T.4- ' '.. DIFFEREN TiAL VIOEO RE CEv ER ; _ er fi ff ' GROUND The cpcitive-lod compenstion teclmiques described bove re - VlrfotS :: A AN '-. Ren 10' -IO'l,} R s, ' GROUND 8 W Figure 10. Vi deo signl trnsm ission syste m. tret it s sou rce- nd lod-terminted trnsmission line - stndrd for The coxil l i n e i s terminted in its chrcteristic impednce by mny yers in vide<j- nd rf-system signl d i stributio n. With R THRM, in this cse 7S D. Becuse neither end of proper termintion, bndwidth limi ttions re gretly reduced. connected directly to ground B, both inputs of receiver B see Figure 9 shows bsic widebnd video driver, con figured to drive video line nd remote lod, Rv with I -V p-p signl. With mtched, widebnd trnsmission line, such s 7S-ohm coxil cble, the cpcitnce of the line is not seen directly by the mplifier. Insted, s distributed-constnt t rnsmission line, it hs chrcteristic impednce, zo,t lo) where Zo 18 V(L/C). RTERM is essentilly the sme common-mode voltge, VNOISE ' which is rejected in proportion to B 's CMR. A typicl CMR gol is 70 d B or better for frequencies u p to 1 0 MHz. Return resistors, Rb2, Rbl if needed, keep Ib,. from developing excessive CM V. nd A t VOUT> stge B delivers replic of tbe originl driving signl VIN' It my lso mplify or nenute the received signl nd drive Anlog Dilogue 26-2 (1992)

7 n ddit ionl 7 5 -fl line. With proper termintions t both ends, other differentil pir. Since the integrtor seeks s tedy stte these ides lso pply for line impednces olher thn 7 5 n. with its two input c urrents in blnce, the feedbck forces the Other criticl prmeters for chis video receiver re signl bnd width - for both the - 3-dB nd O. I -db frequencies (che lner is typicl H DTV requirement)-nd v ideo-d isto rti o n specifictions. Video distortion is usully rted in terms of differentil nd differentil phse n, gin (%) while operting l rted lod with (NTSC) or 4.43-MHz (PAL) subcrriers. Diffe rencing-op-amp Une Receiver Figure 1 1 shows low cost, medium-performnce v ideo line re ceiver, using high speed "video" op mp in stndrd 4-resistor output vo l tge, Vl, to equl the input, V I ' Since the common mode rejection of this device is provided by the two inherently blnced differenril input pirs, there is no need for mtched resistor bridges, with their c-trim nd other problems. In this bsic ppliction, the input signl is pplied to input I, nd the output signl is tied to input 2_ VOUT is mde equl to V,..., while grounds, A nd B, re isolted by the CMR of t he AD830 - cypiclly 75 db t frequencies below 1 M H z, 60 db t 4.43 MHz, nd essentilly independent of supply \'oltge. bridge instrumenttion mplifier. It is implemented for video with With only minor chnges, video line receiver with gin of 2 VN high-speed, high-cmr op mp nd low-resistnce c-trimmed cn be implemented, simply by ttenuting the feedbck. Here, resistors. Resistor mtching is criticl to CMRj for highesc noise pir of 499-(1 resistors, R I nd R), provide 21 1 ttenution. The rejection, single-substrte dul-mtched-pir thin-film network gin expression is then similr to t ht for non-inverting op-mp, should be used. Mtching of che rtios, R,IRz nd R/R4' to 1 % (l + R I/R2) For R,II R l. lowest dc offset, use bis-blnce resistor, R" gives low-frequency CMR of 4{) d B. Above I MHz, the bridge equl to blnce is dominced by c effects, nd the Cl As ground-isolting video repeter, this circuit cn drive - C! cpci tive blnce should be trimmed for best performnce - mtch tht is essen til for chieving CMR bove 40 db t high frequencies. Rz 1kQ terminted 75-(1 output l ine, delivering video output, VOUT> equl to the originl input, V '.'1 ' Video distortion s term i nted line driver is lowest for supply voltges '" I O V ; d i fferen t il gin is typic l ly 0.06%, nd differentil phse is bout Gin- nd phse errors re boul double t 5 V. VIDEO LINE DRIVERS Video l ine-drivers buffer signl from single-ended bord -level (possibly high-impednce) source, scle it if necess ry, nd drive vour o--jw\r--...-< r- _ V'N L. 0+-A./\ -{ n outgoing mtched trnsmission line. The c i rcuits t ht fol low Oesh out the terminted video trnsmission system (Figures 9 nd 1 0) s to rc choices, operting options, nd performnce in "bred nd bu tter" \'ideo pplictions. The circuic environment supplied llows direct performnce ssessment. A Workble Video Une Driver The bsic video l i ne driver of Figure 1 3 uses t he A D8 1 8, low-cost mplifier noted erlier; it is cpble of perfo rming very F i gu re 11. S i m p l e video l ine receiver. Video gin/phse performnce of this stge depends on the choice of device for U I, the operting supply volcges, nd the lo d i ng. Suitble mplifiers work best t supplies of 1 5 V, nd with lods of 1 ko or more, since this mximizes the bndwidth of the op wel l. The U 1 stge gin is set t 2 x by equl R,.. nd RI.v; cheir resistnce is low to minimize the feedbck time-constn t. The AD8 1 8 is compensted for stble opertion t G 2, with mxi- Use Ihe reply crd for I.,;hnicl dt on IlIese n ew producls. Circle 6 tusc (he reply crd for Ic.:hnicl dt on litis new producl Circk 7 mp nd minimiz loding. The A D nd A D8 ) 8* re the best ll -round perfonners, cpble of differentil gin/phse of less thn 0. 1 %/0. 1. This circui t, with its two l -ko inpuc resistors, does lod \'ideo line somewh t ; r.his loding should be tken into ccou n!. t <,... """, Integrted Video Une-Receivers. 499V Full integrtion of r.he video line-receiver elimintes drwbcks of the simple line-receiver pproch nd improves both performnce R,...' nd circuit Oexibility. The AD830,t shown in Figure 1 2, is two input rc "ctive feedbck mplifier" designed for this function_ The AD830 opertes wilh supplies from 5 V to ::':: ] 5 V, hs VOUf ;' 50-MHz bndwidth nd SR of 250 V/jJ.s. Its two high-cmr, VIN - VOUl votn ::; --st fully d i fferentil inputs hndle signls up to 2 V. The current outputs of the input trnsconduccnce stges re summed nd vex" ; v,. OR integrted vi cpcitor C; n output follower buffers its voltge. In norml use, the input is connected to one differentil pir; feedbck is tken from the single-ended output nd pplied to the Anlog Dilogue v v,. 1. st Figure 12. T:. (,. ) I mproved video 9 v,. l i n e-receiver rchitecture with AD830 d ifferentil feedbck mpli fier. 19

8 mum bndwidth of over 50 MHz. Since it doesn't use internl cpcitive lod compenstion, it is quite liner. The ADS I S's exceptionl video differentil gjn nd phse for NTS C system nd :t n re summrized in the figure for supplies of ± 5 V 15 V. (The lod represents the 75-0 cble-drive system. ) To minimize video distortion, loding should be mini mized nd mximum supply voltges used when possible. This circuit drws power-conserving quiescent current of 6 ma. Other video-speed op mps cn lso be used for U l, with some increse of distortion. At ± 1 5 V } for exmple, the ADS17 hs typicl gin/phse of O.04%/O.Oso. The AD810, trnsimpednce mplifier, correct vlue of must be used with the RF for best results. The figure indictes the different vlues, optimized for bndwidth, for ± 5 V nd ± IS V. Highest Perfonnnce Video DriverlDisbibution Amp Figure IS illustrtes very high performnce video line driver. This circuit uses the ADS l l s gin-of-2 video buffer or line driver. It differs from the driver circuits of Figures 1 3 nd 1 4 in tht it optionlly doubles s distribution mplifier, driving two output lines. Operting t gin of 2, the ADS l l drives pir of 75-0 output lines through 75-0 termintions. VO U T, nd Voun re inclividully isoltedlbuffered replics of VIN' "..,.."... "'" IIOu LOAD v,.sv J5V O.Ot. u.v & Figure 13. Bsic (good) video l i ne driver. A Higher Perionn nce Video Driver _,.,.,N.uv ",. -...u Figure 15. H i gher-performnce (even "" -' '0 '0 O.OtJ 0, '" better) l i ne driver/ distribution mplifier. Figure 14 shows higher-performnce video line driver using the ADSlO trnsimpednce mplifier. This circuit is lso reltively With ± I S-V supplies, the circuit's - 3-dB bndwidth is 1 20 MHz, perform better thn Figure 13 becuse of with NTSC differentil gin/phse of 0.01%/0.01 dri ving one line inexpensive, but it cn the ADS 10's pprecibly higher SR higher output current. It lso hs n nd gin-bndwidth, plus its optionl DISABLE function; the stge cn be shut down by control logic. re (RL 150 0). The gin fltness (ripple free) is within 0. 1 db to 35 MHz. For two lines, the gin errors re bout the sme, but the phse errors increse to summrized in Though lower supply voltge degrdes performnce, differentil the figure for supplies of ± 5 V nd ± 15 V. As with the ADRl phse is still < with ± 5 V. The -3-d.B frequency drops [0 The differentil gin nd phse of the ADS I 0 nd O. I -db gin fltness is held to 25 MHz. ::t l O V. circuit, NTSC video dis[qrtion is low, t 0.03%/0.05, with mini 80 MHz, ml loding nd high supply voltge. However, the cpbility is chieved for supply voltges > ADSlO lso does reltively well with ± 5-V supplies; it is the mplifier of choice for such configurtions. Like the ADR I 8, the ADS I O hs low quiescent current, S ma. The AOS I O hs - 3-dB bndwidth of 65 MHz here, nd ripple-free O. I -db bndwidth of 20 MHz, both bener thn for Figure 14. The DISABLE pin (8) is ctive-low to shut the device down to stndby current drin of 2 ma, with 6O-dB input output isoltion t 10 MHz. This permits on/off logic control of single le -or multiplexing the outputs of number of devices. Usc the reply crd for technicl dt on this Full vid eo Cl new product. Circle 6 (only items re currently vilble from AD!) I. M. Chessmn, N. Sokl, "Prevent Emitter Follower OsciJl tion," Eknmi.c Design, June 2 1, REFERENCES 2. J. BlIJ(lon, "Creful Design Tmes High-Speed Op Amps," Electronic Derign, April 1 1, Circle 8 3. D. Whitney, W. Jung, "Applying High Performnce Video Opertionl Amplifier," AlUllog Dilogue 26-1, 1992.* Circle 9 4. D. Whimcy, "Driving Cpcitive Lods," A DS I I dt sheet. * Circle B. Gilben, "Driving LrgeCpcitive Lods," AD844 dt sheet.* Circle D. StOut, M. Kurron, Hndbook of Operri01lQI Amplifier Circuit Design, New York: McGrw Hill, J. Dostl, Opertitml Amplifiers, New York: E1sevier Scientific Publishing, v,. IV p S. G. Erdi, " A 300-V/1J-S Monolithic Voluge Follower," IEEE Jounwl of o-+--( J R.,." Solid-SID./e Circuils, VL SC 14, No. 6, December, G. Erdi et I, "Fst, Open Loop IC Buffer Spurs New Voltge Follower Vloeo PERFORMANCE v..sv A,.... R,. 1$00:.15V 150u LOAO,\G l"l,0 (0.,,-) 0_0< 0.0$ b.03 0_0$ Figure 14. H igh-performnce (better) l i ne d river. 20 Applictions," Ekctronic Design, December 6, P. Brokw, J. Brrow, Grounding for Low nd High Frequency Circuits," AM/og Dilogue 23 3 ( 1989). - Circle 12 I L A. Rich, "Shielding nd Gurding," AIID/og Dilogue 1 7 1, ( 1983). *Re printed in The Begl of AnJJlog Dilogue, /967-/991. -Circle A. Albrecht. "Trnsmission Lines," Ch. 8 i n L. GicolJelo, Dnigner'$ Hndbook, 2nd 00.. New York: McGrw Hill, Electronic 13. B. Slttery, "Video FormtS nd Required Lod Termintions," Anlog Devices AN20S. - Circle 43 Anlog Dilogue 26-2 (1992)

9 OpAmps in Line-Driver nd Receiver Circuits Prt 2. Audio pplictions by Wit Jung nd Adolfo Grci INTRODUCTION The first rticle in this series (Anlog Dilogue 26-2),* covering generl line driving nd buffer design considertions, gve exmples of video line-driver nd -receiver designs. In this rticle, we consider udio line drivers nd receivers. The generl techniques re still germne, in prticulr the mplifier tbles nd buffer design/selection guidelines. Cpcitive lod isoltion is lso importnt to udio drivers; long trnsmission lines pper cpcitive becuse udio trnsmission systems do not tend to use terminted trnsmission lines. In generl, the "housekeeping" rules on lyout nd bypssing re lso strongly recommended for prcticl udio circuits of ny type, especilly drivers (nd were followed for the exmples in this rticle). Trnsmitting udio signls between vrious components usully involves some form of trdeoff. For highest performnce, fully differentil or blnced trnsmission systems re best t rejecting low frequency nd r-f noise. Figure 1 is block digrm of typicl udio system using differentil trnsmission. In concept, vriety of input/output coupling schemes re vilble for blnced trnsmission system; they will be discussed briefly. DIFFERENTIAL LINE DRIVER G;;;2 VNOISE BETWEEN COMMON MODE", VNOISE DIFFERENTIAL LINE RECEIVER G '" 0,5 GROUNDS A & B r rvr Figure 1. Audio blnced trnsmission system. Trnsformers [1]-[4] hve been trditionl input or output udio line-coupling element. While unexcelled in certin res, they hve well-known problems: noise pickup, poor frequency response, distortion, nd limited operting level-problems tht cn be mitigted to some degree (often t firly high cost). The trnsformer's outstnding virtue is its bility to isolte glvniclly voltges up to its windings' brekdown potentil; signls cn be trnsmitted between circuits with hundreds of volts of potentil difference, feture not esy to chieve with solid-stte circuits. Quite high common-mode rejection (CMR) is lso vilble, > 100 db over the udio rnge, less t high frequencies. Figure 1 cn use either trnsformer or ctive coupling to the line. The gol for either pproch is to reproduce the input signl, VINo t the output, while rejecting noise between grounds A nd B by db. A typicl unity gin design uses line drive of ±VlN nd receiver gin of 112, to mximize receiver CMR. AUDIO LINE RECEIVERS A mjor purpose of this circuit nd ll line receivers is to reject common-mode noise, s might be picked up on twisted-pir trnsmission line. A brief review of the topologies nd pros nd cons of ctive udio line receivers helps in understnding their evolution. The clssic single-op-mp, 4-resistor sl,lbtrctor circuit of Figure 2 cn ct s differentil mplifier. When the resistor rtios provide gin, the circuit is known s n instrumenttion mplifier (la). Some of tody's lc udio line receivers, bsed on feedbck circuitry, re direct descendnts of this circuit. [5]-[9] R2 C2J L 25kll r - - -, OPTIONAL I BUFFER t', ;> : -----<>---00 V OUT R4 25kSl.- Figure 2. Simple line-receiver topology. The simple line receiver FOR. R, R, G. V OUT V IN R j The circuit of Figure 2 is simple; the minimum ingredients re four mtched film resistors nd good udio op mp. While it works functionlly, its degree of common-mode rejection (CMR) my be problemticl. The performnce of such bridge-bsed difference mplifiers depends criticlly upon resistor-rtio mtching-including source impednces in series with RI nd R3. The mplifier lso contributes error, but with high-qulity op mp, noise rejection is limited by c & dc bridge unblnce. Selecting four discrete resistors from sme-vendor-sme-btch lot, to rtio-mtch within 0.1 %-or (more likely) using purchsed thin-film network with 0.1 % specified mismtch -results in CMR of 66 db. In generl, the worst-cse CMR of this type of circuit (mplifier CMR 100 db): 1 + R2/RI CMR (db) 20 log where Kr is the net rtio tolernce in frctionl form.[5] Clerly, for high nd stble noise rejection with tempermre trcking, thick- or thin-film resistors integrted on single substrte with rtio mtching to within 0.01% (from vendors such s Cddock nd Vishy-Ohmtek) re preferred to selected individul resistors. The Figure 2 topology is most effective when the resistors nd mplifier re mde simultneously in single monolithic le. The Anlog Devices 8-pin SSM-2141 nd SSM-2143t re such ICs, designed nd chrcterized s low distortion, high CMR udio line receivers with net gins of 1.0 (SSM-2141), nd 0.5 (SSM- 2143). The SSM-2141 hs the sme resistnce vlues s in Figure 2, while the SSM-2143 uses 12-kfl/6-kfl resistors. Amplifier protection is inherent in two wys: the input commonmode voltge (CMV) in the unity-gin cse is hlved t the mplifier inputs (nd cn be further reduced by resistors to ground), nd the series resistnce limits fult currents due to excessive *Use the reply crd. Circle 18 for Anlog Dilogue 26-2, 19 for the rticle reprint. ttechnicl dt for the mplifiers mentioned in this rticle cn be found in the 1992 Amplifier Reference Mnul, vilble t no chrge. If you need copy circle 10 K r 14 Anlog Dilogue 27-1 (1993)

10 -- CMV. Receiver circuits not needing input resistors my cll for input resistors nywy for protection in prcticl circuitry. Figure 2's working CM input rnge is [1 + (R3IR4)]X V CM(ulj' nd the differentil input resistnce is RI + R3 Gin of the circuit isn't esily chnged, becuse of the mtched R-rtios. For widebnd udio uses, the bridge impednce-rtio mtch needs to be mintined for c, to chieve flt CMR with incresing frequency. Cpcitnces t the RzlRI nd R41R3 nodes need to be blnced. This is best chieved with very low nd/or blnced prsitic cpcitnces t CI-C2 Implementing the simple line-receiver function For dequte input impednce, these receivers typiclly use input resistnce ::>:20 ko. With well mtched resistor network nd low- or blnccd prsitic cpcitnces, suggested mplifiers re the AD711 nd AD744 (singles), nd the AD712, AD746, OP-249 nd OP-275 (duls). With ko resistnces, extremely low mplifier voltge noise is not criticl requirement, but high slew rte (SR) nd husky output drive permit high mplitude levels, clen high-frequency response, nd lods. For circuits such s these, tht resistively lod the source, the line nd source resistnces, if unblnced, cn compromise CMR. For exmple, mismtch of cn esily occur in wiring; if it is not blnced out, CMR cn be degrded to 86 db. These circuits behve hest when the sources re blnced nd low-impednce. Other issues with the simple line receiver The circuit of Figure 2 hs symmetry of sort, but it is not relly blnced. If blnced pir of input voitges, + VIN nd -V'N' re pplied to the two inputs, the currents in the two legs re different. Here, the current in the R3 leg is VINISO ko nd the current in the RI leg, becuse of the op-mp feedbck <Inion, is [-VIN - VIN12]/25 ku -3VIN150 ko, three times s much. Thus, the inpub lod the ource nd the connecting lines differently. If the source is trnsformer winding, the circuit will un blnce the line, driving the minus-input side to virtul ground. Idelly, n udio line receiver should exhibit equl c loding t the two inputs. Wirh the simple line receiver of Figure 2, this gol is not met. Nevertheless, for grounded symmetricl source nd line pir, with ingle receiver, loding uf the source resistnce will produce gin error, but the symmetricl current will not substntilly ffect the CMR becuse feedbck will compenste for the greter voltge drop on the Ri side. But, in systems with numerous blnced trnsmission line pirs, the input current imblnce my be more serious; ssocited fields will not cncel s they do for completely blnced loding. Thus there is potentil for crosstlk impirment in such systems. While not optimum in lrge systems, the simple line receiver is nevertheless useful in more modest situtions. With resistnces R l-r 3 reltively high (20 k11 or more), it is quite dequte for smll-scle or confined systems where I/O lines re reltively short or few in number-or re not cbled. Devices like the SSM-2141 nd SSM-2143 serve well s efficient single-le solutions. A blnced form of line receiver Birt, of the BBC, nlyzing the simple line receiver topology, hs described blnced form[4]: in Figure 3, Ul uses n identicl 4-resistor network, but the unity-gin inverter, U2, drives R4's previously grounded reference terminl t - V O UT' This equlizes the input currents in thc :+:: input legs nd provides choice of blnced push-pull output with gin of RiR, or single-ended output of either polrity with gin of 112 [RzIRJ (one-hlf tht of the Figure 2 circuit). Existing line receivers cn be converted to the blnced topology by dding n pproprite inverter, U2, nd doubling the gin (R21R1 R4/R, 2) if necessry. The common-mode rnge of this circuit is the sme s for Figure 2, but common-mode rejection t V OUT (or -V OUT) is bout doubled with ll resistnces nominlly equl. The il}verter resistnce rtio, R61Rs ffects blnce-but not CMR. R1 25k\1 R2 25kQ r VOUT I (-) o--\mr- --V\f\r o VOUT, 1 (+) o--'\mr- --IlAi'v <.. R5 10kQ Figure 3. Blnced line receiver using push-pull feedbck pth. Other blnced line receivers Why not use n instrumenttion mplifier [5-8] s line receiver? Conventionl high-input-impednce instrumenttion mplifier circuits (including single-chip in-mps) cn esily chieve the gol of fully blnced input loding. Too, they my specify high CMR -but generlly t low frequencies. They my not be desirble for other resons. For exmple, the input resistors of circuits like Figure 2 reduce common-mode voltge nd limit fult currents, necessry input-protection considertion in mny rel world udio systems. To dd mtched ttenutors hed of n in mp for this purpose degrdes performnce nd dds cost. An "ll inverting" blnced line receiver Figure 4, using only inverting mplifiers, cn be configured for high CMV rnge nd input resistnce. The CMR of this circuit is limited essentilly by the bility to mtch resistnce rtios, since the mplifiers' CMRs rc irrelevnt. The mximum input voltge the circuit cn hndle is limited by the output rnge of UI, so R11R2 cn be incresed to del with higher common-mode input voltges. The differentil input resistnce is RI + R3. Unlike the others, the gin of this circuit cn be djusted with single resistnce, R" without disturbing the CMR. Gin cn be flexibly djusted to vlues both greter nd less thn unity. As shown, the drive is blnced signl, but note tht it cn be driven with single ended sources t either the (+) or the (-) terminl. Multiple inputs cn be summed, by dding dditionl rtiomtched input-resistor pirs. This exmple shows gin of 0.5. In this improved version of the otherwise well-known circuit [5)-[8], phse led compenstion enhnces high-frequency CMR. R4 is shunted by low cpcitnce (driven through n ttenutor), chosen to compenste for the lg through Ui; it mximizes phse mtching of the ±CM signls t U2. The ttenutor (R6-R7) cn be used to void extremely low cpcitnce vlues. Its nominl division rtio is pproximted by: K, 1 2 'TT BW(Ul) R4 Cl where Kc is the division rtio of R6-R7' For this exmple, with BW 5 MHz (the closed-loop bndwidth of Ul), Kc is bout 0.6, providing n effective Cc of bout 3 pf. Circuit prsitics, Anlog Dil gue 27 1 (1993) 15