Operating Temperature Range

Transcription

1 1.2 mm 2 µpower, 5 ppm, khz TCXO with In-System Auto-Calibration Features khz ±5 ppm all-inclusive frequency stability In-system auto-calibration: Compensates for board-level stress-induced frequency errors Improves all-inclusive frequency stability World s smallest TCXO Footprint: 1.2 mm x 0.8 mm CSP No external bypass cap required Drives multiple loads and eliminates multiples XTALs Low integrated phase jitter (IPJ) suitable for multiplying up for portable audio: 2.5ns RMS Ultra-low power: 4.5 µa Supply voltage: 1.8V ±10% Operating temperature ranges: -20 C to +70 C, -40 C to +85 C Pb-free, RoHS and REACH compliant Electrical Characteristics Applications Smart watches, health and wellness monitors Ultra-accurate RTC reference clock Smart utility meters, E-meters Internet of Things (IoT) Table 1. Electrical Characteristics Conditions: Min/Max limits are over temperature, Vdd = 1.8V ±10%, unless otherwise stated. Typicals are at 25 C and Vdd = 1.8V. Parameter Symbol Min. Typ. Max. Unit Condition Frequency and Stability Output Frequency Fout khz Total Frequency Stability after F_stab -5 5 ppm All inclusive, after overmold, post in-system calibration. Overmold [1] ppm All inclusive, after overmold, before in-system calibration. Total Frequency Stability without Overmold or Calibration [1] -5 5 ppm Allan Deviation AD 1e-8 4e-8-1 second averaging time. All inclusive, under influence of up to 5 C/sec temp gradient and board-level underfill. First Year Frequency Aging F_aging ±1 ppm T A = 25 C, Vdd = 1.8V, with overmold. Jitter and Frequency Response Performance Integrated Phase Jitter IPJ ns RMS 50 mv peak-to-peak sinusoidal noise on Vdd. Noise Integration bandwidth = 100 Hz to khz. Inclusive of frequency 100 Hz to 20 MHz. RMS Period Jitter PJ RMS nsrms 10,000 samples, per JEDEC standard 65B 7Peak-to-Peak Period Jitter PJp-p nsp-p Dynamic Temperature Frequency Response ppm/sec Under temp ramp up to 1.5 C/sec Supply Voltage and Current Consumption Operating Supply Voltage Vdd V Supply Current Idd µa No Load. Start-up Time at Power-up t_start 300 ms Operating Temperature Range Op_Temp Operating Temperature Range C C ordering code C I ordering code. LVCMOS Output Output Rise/Fall Time tr, tf 9 20 ns 10-90% (Vdd), 15 pf Load. Output Clock Duty Cycle DC % Output Voltage High VOH 90% Vdd I OH = -1 µa Output Voltage Low VOL 10% Vdd I OL = 1 µa Measured when supply reaches 90% of final Vdd to the first output pulse. Note: 1. Contact SiTime for specific overmold conditions. Relative to khz, includes initial tolerance, over temp, Vdd, load, hysteresis, board-level underfill, and, 3x reflow. Tested with Agilent 53132A frequency counter. Measured with 100ms gate time for accurate frequency measurement. Rev. 1.0 March 15,

2 Table 2. Pin Configuration CSP Pin Symbol I/O Functionality CSP Package (Top View) 1 Auto-Cal or NC Control Input Used for communicating calibration information to the chip for improving stability in the presence of board level induced stresses. Leave pin floating (NC) when not using the calibration function. CAL/NC 1 4 GND 2 CLK Out OUT Oscillator clock output. 3 Vdd Power Supply 1.8V ±10% power supply. For most applications, the internal bypass filtering is acceptable. A PSNR plot is shown in the Typ Ops section. If power-supply bypassing is required, a nf low ESR, ceramic capacitor is acceptable. 4 GND Power Supply Ground Connect to ground. CLK Out 2 3 Vdd Figure 1. Pin Assignment Table 3. Absolute Maximum Ratings Attempted operation outside the absolute maximum ratings may cause permanent damage to the part. Actual performance of the IC is only guaranteed within the operational specifications, not at absolute maximum ratings. Parameters Test Conditions Value Unit Continuous Power Supply Voltage Range (Vdd) -0.5 to 4.0 V Continuous Maximum Operating Temperature Range 105 C Human Body Model (HBM) ESD Protection JESD22-A V Charge-Device Model (CDM) ESD Protection JESD22-C V Machine Model (MM) ESD Protection T A = 25 C 200 V Latch-up Tolerance JESD78 Compliant Mechanical Shock Resistance Mil 883, Method ,000 g Mechanical Vibration Resistance Mil 883, Method g 1508 CSP Junction Temperature 150 C Storage Temperature -65 to 150 C System Block Diagram MEMS Resonator GND Control Regulators Vdd Temp Control Temp-to-Digital NVM Prog Prog Cal/NC Sustaining Amp Ultra-low Power Frac-n PLL Divider Driver CLK Out Figure 2. SiT1568 Block Diagram Rev. 1.0 Page 2 of 13

3 Description SiT1568 is an ultra-small and ultra-low power khz TCXO optimized for battery-powered applications. SiTime s silicon MEMS technology enables the first 32 khz TCXO in the world s smallest footprint and chip-scale packaging (CSP). Typical supply current is 4.5 µa under no load condition. SiTime's MEMS oscillator consists of a MEMS resonator and a programmable analog circuit. SiT1568 MEMS resonator is built with SiTime s unique MEMS First process. A key manufacturing step is EpiSeal during which the MEMS resonator is annealed with temperatures over 1000 C. EpiSeal creates an extremely strong, clean, vacuum chamber that encapsulates the MEMS resonator and ensures the best performance and reliability. During EpiSeal, a poly silicon cap is grown on top of the resonator cavity, which eliminates the need for additional cap wafers or other exotic packaging. As a result, SiTime s MEMS resonator die can be used like any other semiconductor die. One unique result of SiTime s MEMS First and EpiSeal manufacturing processes is the capability to integrate SiTime s MEMS die with a SOC, ASIC, microprocessor or analog die within a package to eliminate external timing components and provide a highly integrated, smaller, cheaper solution to the customer. TCXO Frequency Stability SiT1568 is factory calibrated (trimmed) over multiple temperature points to guarantee extremely tight stability over temperature. Unlike quartz crystals that have a classic tuning fork parabola temperature curve with a 25 C turnover point with a 0.04 ppm/c 2 temperature coefficient, the SiT1568 temperature coefficient is calibrated and corrected over temperature with an active temperature correction circuit. The result is a 32 khz TCXO with extremely tight frequency variation over the -40 C to +85 C temperature range. When measuring the output frequency of SiT1568 with a frequency counter, it is important to make sure the counter's gate time is >100 ms. Shorter gate times may lead to inaccurate measurements. In-System Auto Calibration SiT1568 provides a unique, in-system calibration feature that compensates for assembly-related frequency offsets for improved overall frequency stability. The on-chip autocalibration function is performed one-time during the customer's production system manufacturing process. In order to initiate the one-time auto calibration process, refer to the pin 1 auto-calibration description. After assembly, follow the calibration steps as shown in the flow chart (Figure 3). Connect pin 1 to a 10 MHz reference (GPS disciplined or equivalent) and monitor the SiT1568 CLK Out for status and error flags. A summary of these flags is shown in Table 7. SiT1568 will compare its khz (plus the assembly-related error) frequency to the accurate 10 MHz reference, calibrate (remove) the error and store the calibration in its internal non-volatile memory. The result is a calibrated khz output frequency with an overall stability (accuracy) of ±5 ppm. The entire auto-calibration process typically takes about 2 seconds. Auto calibration is intended to be performed one time to remove the board-related offset errors. The auto-calibration procedure can be repeated if process fails during the initial steps (see Table 7). The maximum number of retries is determined by the customer. Dynamic Temperature Frequency Response Dynamic Temperature Frequency Response is the rate of frequency change during temperature ramps. This is an important performance metric when the oscillator is mounted near a high power component (e.g. SoC or power management) that may rapidly change the temperature of surrounding components. For moderate temperature ramp rates (< 2 C/sec), the dynamic response is primarily determined by the steadystate frequency vs. temperature of the device. The best dynamic response is obtained from parts which have been trimmed to be flat in frequency over temperature. For high temperature ramp rates (>5 C/sec), the latency in the temperature compensation loop contributes a larger frequency error, which is dependent on the temperature compensation update rate. This part achieves excellent performance at 3Hz update rate. This device family supports faster update rates for further reducing dynamic frequency error at the expense of slightly increased current consumption. Rev. 1.0 Page 3 of 13

4 Initial Conditions Post assembly and over mold, wait time = t_settle Step 1 Power Up 1. Power up Pin 3 Vdd with t_vdd_ramp_up to Vdd_cal from 0V Pin 1 should be floating Output = khz ± 25ppm Step 2 Set-up & Calibrate 2. Connect Pin 1 to f_refin* waiting t_pu_to_refin after Vdd powerup Output = khz (Auto-Calibration in progress flag) Yes Status Flag: Ready for memory program CLK output = khz Step 3 Program Calibration Results into Memory Check CLK Out for successful calibration. Wait time in this state is t_cal Yes 3. Switch Pin 1 to V_prog with t_prog_ramp_up Output = khz (Ready to start memory burn flag) No Error Flag: See Error Table CLK output = 5.12 khz or 2.56 khz No No Auto-Cal retry reaches Max limit Retry? ** No Auto-calibration failed. Log error flag and discard module Yes Yes Return to Step 1 Check CLK Out for valid V_prog on pin 1 No Yes Status Flag: 3.5V detected on pin 1 CLK output = khz Yes Pass Status Flag: Auto-Cal successful CLK output = khz ±3 ppm Check CLK Out for successful memory program. Wait time is t_prog_mem Pass Fail Fail Error Flag: See Error Table CLK output = 1.28 khz or 0.64 khz Auto-calibration successful. Switch pin 1 to from V_prog to float with ramp < t_prog_ramp_dn. Log output frequency. Optionally power cycle VDD to 1.8V, then log output frequency * GPS-disciplined 10 MHz OCXO Reference ** Max Retry count set by customer Figure 3. Initial Offset Auto-Calibration Procedure Rev. 1.0 Page 4 of 13

5 In-System Auto-Calibration Table 4. Pin 1 Auto-Calibration Mode DC Electrical Characteristics Parameter Symbol Min. Typ. Max. Unit Condition Input Impedance Z_IN 80 kω Internal pull-down Input VIH VIH 70% Vdd Input VIL VIL 30% Vdd Input Overshoot Voltage V_IN_OD 75 mv Program Voltage V_prog V Pin 1 NVM program voltage Program Current I_prog 30 ma pk Peak current required on pin 1 during auto-calibration 5 ma avg Average current required on pin 1 during auto-calibration Auto-Cal Voltage Noise Ripple 50 mvpp Max noise on 3.5V auto-calibration voltage (pin 1) Auto-Cal Vdd Supply Vdd_cal V Vdd (pin 3) supply voltage during auto-calibration Vdd Bypass Capacitor 0.1 µf Vdd (pin 3) bypass cap required during auto-calibration Pin 3 Idd Prog Current Idd_prog 1 ma Idd (pin 3) current required during auto-calibration Pin 3 Min Power Down Threshold Voltage Table 5. Auto-Calibration Mode Timing Characteristics Vdd_pd 0.7 V Pin 1 Vdd threshold to guarantee internal device power-down Parameter Symbol Min. Typ. Max. Unit Condition Post System Assy Settling Time t_settle 24 hr Wait time between > absolute max storage temp exposure (150 C) and auto-cal start Pin 3 Power Supply Ramp Rate t_vdd_ramp 100 ms Ramp rate for Vdd pin during auto-calibration Auto-Cal Ref-in Wait Time t_pu_to_refin 0.5 sec Time to supply auto-cal clock on pin 1 after within spec Vdd (pin 3) Ref In Detection Time t_refin_to_clk_ flag_65k 1.2 ms Time to detect 10 MHz auto-cal reference inputs, k Hz output Auto-Cal Time t_cal 2 5 sec Time in Step 2, auto-calibration Pin 1 Float Duration t_refin_to_float 200 µs Pin 1 float time required prior to applying prog voltage Pin 1 Prog Voltage Ramp Rate t_prog_ramp_up µs Ramp rate on Cal pin to V_prog during auto-calibration Prog Voltage Detection Time t_prog_to_clk_ flag_10k 100 ms Time to detect program voltage, khz output flag Pin 1 Prog Voltage Ramp Down t_prog_ramp_dn µs Time to power-down prog voltage Memory Programming Time t_prog_mem 100 ms Time in Step 3, Memory program Pin 3 Power-Down Delay t_prog_to_pd 1 ms Pin 3 Vdd power-down delay from Pin 1 prog voltage power down Table 6. Auto-Calibration Reference Clock Characteristics Parameter Symbol Min. Typ. Max. Unit Condition Auto-Cal Ref Clock Freq f_refin MHz (10 MHz ± 100ppb) Correct reference frequency for auto-calibration Auto-Cal Ref Clock Rise/Fall Time t_refin_r/f 4 20 ns 20/80%; Rise and fall time of the auto-cal 10 MHz ref clock Auto-Cal Ref Clock Duty Cycle dc_refin % Auto-Cal Ref Clock Period Jitter pj_refin 200 ps RMS Auto-Cal Ref Clock Allan Deviation ad_refin 10 ppb For averaging time = 1 second Rev. 1.0 Page 5 of 13

6 VDD Pin 3 Vdd_cal 0V Float Float Pin 1 = Auto-Cal Ref-in Pin 1 = V_Prog Float V_prog Cal Pin 1 VIH VIL t_cal t_prog_mem t_vdd_ramp t_pu_to_refin t_refin_to_float t_prog_ramp_up t_prog_ramp_dn t_prog_to_pd Clk Pin khz khz khz khz khz t_refin_to_clk_flag_65k t_prog_to_clk_flag_10k Figure 4. Auto-Calibration Timing Diagram Table 7. Auto-Calibration Status and Error Flags Flag Name Output Frequency [2] Recommended Minimum Gate Time Status or Error Flag Retry Calibration Auto-Calibration in progress khz 10 ms Status N/A Ready to start memory burn khz 10 ms Status N/A 3.3V on Pin 1 detected khz 10 ms Status N/A Auto-Calibration successful khz ±3ppm 100 ms Status No 10 MHz reference lost during calibration step khz 10 ms Error Yes Frequency correction out of range in step khz 10 ms Error Yes Memory burn failed in step khz 10 ms Error No 3.3V lost on Pin 1 during memory burn step khz 10 ms Error No Note: 2. Frequency tolerance is ±5% except for 32 khz frequency output. Rev. 1.0 Page 6 of 13

7 Switch Control Switch Control 3.5V 1µF 1.8V G Power MOSFET S IRLML6402 D 249k 1N MHz Calibration Input 5V FSA4157 SPDT relay 10pF CAL/NC No-connect on customer module 1 SiT GND Roof top Antenna Level Shifter SN74AUP1G17 10MHz OCXO 500mV sine-wave GPS - disciplined OCXO reference Microsemi XL- GPS V2 Customer Test Board To Ref-in (Back Panel) Frequency Counter Agilent 53230A Buffer OPA355UA To measurement channel 5V Place buffer close to connector 0.1µF C L < 50pF To controller via LAN/GPIB CLK-OUT khz clock on customer module 2 3 Customer Product Board Vdd 1.8V Vdd Figure 5. In-System Auto-Calibration Hardware Interface Rev. 1.0 Page 7 of 13

8 Typical Operating Curves (T A = 25 C, Vdd = 1.8V, supply current plots are no load, unless otherwise stated) Frequency Stability (PPM) Total Current (ua) No Load Temperature ( C) Figure 6. Frequency Stability over Temperature (Post Reflow) Temperature ( C) Figure 7. Supply Current over Temperature Internal Caps Charging Logic Start-up NVM Read OSC Start-up Temperature Compensation (13 µa) khz Steady State 350ms Figure 8. Start-up and Steady-State Current Profile Figure 9. LVCMOS Output Swing No Vdd bypass 10 nf Vdd bypass Figure 10. Power Supply Noise Rejection (PSNR) Rev. 1.0 Page 8 of 13

9 Dynamic Frequency Response for Moderate Temperature Ramps Frequency accuracy under a moderate temperature ramp up to 2 C/sec is limited by the TCXO s trimmed accuracy of the frequency stability over-temperature. Note: 3. Measured relative to khz. Rev. 1.0 Page 9 of 13

10 Dynamic Frequency Response for Fast Temperature Ramps 5 C/sec Temp Ramp Frequency Response 10 C/sec Temp Ramp Frequency Response ~10 C/sec ~5 C/sec [4] [4] 3 Hz Temp Comp Refresh Rate 3 Hz Temp Comp Refresh Rate For temperature ramps >5 C/sec, the frequency accuracy is limited by the update rate of the temperature compensation path (see the 5 C/sec and 10 C/sec plots). Contact SiTime for applications that require improved dynamic performance. Note: 4. Referenced to khz. Rev. 1.0 Page 10 of 13

11 Dimensions and Patterns Package Size Dimensions (Unit: mm) Recommended Land Pattern (Unit: mm) #4 #3 #1 #2 (soldermask openings shown with dashed line around NSMD pad) Recommended 4-mil (0.1mm) stencil thickness Manufacturing Guidelines 1) No Ultrasonic or Megasonic cleaning: Do not subject the SiT1568 to an ultrasonic or megasonic cleaning environment. Permanent damage or long term reliability issues may occur. 2) Applying board-level underfill and overmold is acceptable and will not impact the reliability of the device. Any post assembly frequency shift can be calibrated with the in-system auto-calibration feature. 3) Reflow profile, per JESD22-A113D. 4) For additional manufacturing guidelines and marking/tape-reel instructions, refer to SiTime Manufacturing Notes. Rev. 1.0 Page 11 of 13

12 Ordering Information SiT1568AI-JE-DCC S Part Family SiT1568 Revision Letter A : is the revision Temperature Range C : Extended Commercial, -20 to 70ºC I : lndustrial, -40 to 85ºC Package Size J : 1.5 mm x 0.8 mm CSP Packaging S : 8 mm Tape & Reel, 10ku reel D : 8 mm Tape & Reel, 3ku reel E : 8 mm Tape & Reel, 1ku reel Samples in cut Tape Output Clock Frequency (khz) khz LVCMOS Output All-Inclusive Over Temp Stability E : ±5 ppm Rev. 1.0 Page 12 of 13

13 Table 8. Revision History Version Release Date Change Summary /30/2015 Advanced datasheet initial release /10/2016 Preliminary datasheet initial release /15/2018 Updated POD (Package Outline Drawing) Updated logo and company address, other page layout changes SiTime Corporation, 5451 Patrick Henry Drive, Santa Clara, CA 95054, USA Phone: Fax: SiTime Corporation The information contained herein is subject to change at any time without notice. SiTime assumes no responsibility or liabi lity for any loss, damage or defect of a Product which is caused in whole or in part by (i) use of any circuitry other than circuitry embodied in a SiTime product, (ii) misuse or abuse including static discharge, neglect or accident, (iii) unauthorized modification or repairs which have been soldered or altered during assembly and are not capable of being tested by SiTime under its normal test conditions, or (iv) improper installation, storage, handling, warehousing or transportation, or (v) being subjected to unusual physical, thermal, or electrical stress. Disclaimer: SiTime makes no warranty of any kind, express or implied, with regard to this material, and specifically disclaims any and all express or implied warranties, either in fact or by operation of law, statutory or otherwise, including the implied warranties of merchantability and fitness for use or a particular purpose, and any implied warranty arising from course of dealing or usage of trade, as well as any common-law duties relating to accuracy or lack of negligence, with respect to this material, any SiTime product and any product documentation. Products sold by SiTime are not suitable or intended to be used in a life support application or component, to operate nuclear facilities, or in other mission critical applications where human life may be involved or at stake. All sales are made conditioned upon compliance with the critical uses policy set forth below. CRITICAL USE EXCLUSION POLICY BUYER AGREES NOT TO USE SITIME'S PRODUCTS FOR ANY APPLICATION OR IN ANY COMPONENTS USED IN LIFE SUPPORT DEVICES OR TO OPERATE NUCLEAR FACILITIES OR FOR USE IN OTHER MISSION-CRITICAL APPLICATIONS OR COMPONENTS WHERE HUMAN LIFE OR PROPERTY MAY BE AT STAKE. SiTime owns all rights, title and interest to the intellectual property related to SiTime's products, including any software, firmware, copyright, patent, or trademark. The sale of SiTime products does not convey or imply any license under patent or other rights. SiTime retains the copyright and trademark rights in all documents, catalogs and plans supplied pursuant to or ancillary to the sale of products or services by SiTime. Unless otherwise agreed to in writing by SiTime, any reproduction, modification, translation, compilation, or representation of this material shall be strictly prohibited. Rev. 1.0 Page 13 of 13