SiP11206DB. 200 W 1/16 th Brick IBC Demo Board using SiP Vishay Siliconix

Transcription

1 00 W / th Brick IBC Demo Board using SiP0 SiP0DB DESCRIPTION SiP0 is a half-bridge controller for intermediate bus converters. While SiP0 allows for overall better efficiency through out the input voltage range, since its duty cycle is fixed and is optimally set closer to its maximum 0 %. This also limits the input voltage range to a narrower V to V typical range because of the fixed duty cycle the output voltage will have a proportionally wider voltage swing. The SiP0 is best for applications where efficiency is key and a wider output voltage can be tolerated. This demo board is a sixteenth-brick IBC power converter, which plugs into a baseboard. The IBC board has the following specifications and options: Narrow input voltage range ( V to V) with SiP0 controller IC Nominal V output, nominal load current 7 A PowerPAK - for primary and secondary power MOSFETs The baseboard contains input fuse, input/output terminals, remote enable connectors, enable switch, input bulk capacitors and output voltage measurement BNC connector. The cutout in the baseboard allows for probing of both sides of the IBC board. Photos are shown in figure. Figure. Photos of Demo Board with PowerPAK MOSFET Options Size comparison of Vishay / th and / th Brick Modules This document details the following of the demo board:. Set up. Operation. Waveforms and performance curves. Schematic and BOM. Board layout SET UP The connection diagram for the demo board is depicted in figure. Power and sense connections are provided at the input and output for the main current path and for voltage sensing for efficiency monitoring. Wire rated at A should be used for the input connections and x 0 A rated wire should be used for the output lines. The board can be enabled/disabled manually by using the on-board switch or by connecting a 0 V/ V logic signal in the disable connector. V represents disable. S09-0-Rev. B, 0-Mar-09

2 SiP0DB Wiring lengths should be kept as short as possible, especially at the output in order to avoid excessive voltage drop across the cable length. The demo board has two 7 µf capacitors at the input to help minimize the issues with long cables lengths used at the input. It should be noted that with long cable lengths, the input voltage might be quite oscillatory on power up, potentially leading to under-voltage or the converter cycling in and out of operation until the voltage becomes steady. A small fan should be placed so that air is blown over both sides of demo board in the direction shown. If the temperature of the board exceeds ~ 0 ºC, the board will be disabled by the over temperature shutdown mechanism. Figure. Connection Diagram OPERATION AND TEST RESULTS The power circuit is a half-bridge converter controlled by the SiP0 IC. In the SiP0, the converter duty cycle is fixed and is set by R. This version of the chip was used on the demo board which maintains the highest overall efficiency since the duty cycle is constant. It is typically set to a value close to 0 % for maximum efficiency. The output voltage is then determined by the input voltage and the transformer turns ratio. In this demo board, the transformer turns ratio is :. The controller IC is powered at startup by its own internal 9. V pre-regulator, which is driven from the line voltage. Once converter switching commences, a separate 0. V V CC supply is supplied from an auxiliary transformer winding, and linear regulator R, Q 7, D. The secondary side synchronous rectifiers are self-driven, but with a controlled gate voltage that does not vary with input voltage. The result is improved efficiency and safer drive voltages because the secondary gate drive is generated locally and clamped to ~ 0 V through D 9, R 9, C and D 0. MOSFETs Q and Q are triggered by the opposite transformer node, and the 0 V is coupled to the synchronous rectifier gate less a threshold voltage drop. A Schottky diode can be connected across the output filter which improves efficiency for longer dead times. During dead time, the synchronous rectifiers are off as there is no transformer voltage available to turn them on. Hence, without the Schottky diode present, the inductor current will flow through the body diodes of the synchronous rectifiers. The Schottky diode has a smaller voltage drop than the body diodes, and so may enhance efficiency dependent on deadtime, sync-fets, layout etc. Some typical converter waveforms are shown in figures to 7. (a) V with 0 A, DL, V LOUT (b) V with 0 A, DL, V LOUT Figure. Secondary Switching Waveforms S09-0-Rev. B, 0-Mar-09

3 SiP0DB Startup 0 A Load V REF, DL, SS, V OUT Startup 0 A Load V REF, DL, SS, V OUT Startup 0 A Load V DET, DL, SS, V OUT Startup 0 A Load V DET, DL, SS, V OUT Figure. Startup Waveforms Shutdown 0 A Load V REF, DL, SS, V OUT Shutdown 0 A Load V REF, DL, SS, V OUT Shutdown 0 A Load V DET, DL, SS, V OUT Shutdown 0 A Load V DET, DL, SS, V OUT Figure. Shutdown Waveforms S09-0-Rev. B, 0-Mar-09

4 SiP0DB A Load V DET, DL, SS, V OUT A Load V REF, DL, SS, V OUT Figure. Over Current Protection/Hiccup Waveforms No Load mv pk-pk 0 A Load 7 mv pk-pk Figure 7. Ripple Waveforms Efficiency 97 % 9 % 9 % 9 % 9 % 9 % 9 % 90 % 9 % % 7 % V IN = V V IN = V V IN = V VOUT 0 Line Reg = V Line Reg = V Line Reg = V % % % Output Current (A) Load SiP0 / th Brick Efficiency / th Brick Line-Load Regulation Figure. Efficiency Figure 9. Line-Load Regulation S09-0-Rev. B, 0-Mar-09

5 SiP0DB PCB LAYOUT The demo board is an 0 layer board in the sixteenth-brick form factor, manufactured with oz copper on the outer layers and oz copper on the inner layers. The circuit schematics for the demo board are illustrated in figures 0 and. The transformer is a planar magnetic component with an EI core. The primary winding has turns, located on layers,, and 7, with turns per layer. Each secondary winding has turns, located on layers,,, and with turn per layer. The auxiliary winding has turns, consisting of turns on the bottom layer figure. Figure shows the top bottom of the base board. Figure 0. Layers to of PCB (l-r) Figure. Layers to of PCB (l-r) Figure. Top and Bottom Layout Figure. Top and Bottom PCB layout of Base Board S09-0-Rev. B, 0-Mar-09

6 SiP0DB The schematics are shown in figures and, and parts list are shown in table and. TABLE - IBC PARTS LIST - PART VALUES ARE FOR NARROW INPUT VERSION Designator Description Comment Footprint Quantity Value C Capacitor 0 00 nf/ V C Capacitor 0 µf/ V C Capacitor 0 00 pf/ V C Capacitor 0 nf/ V C Capacitor 0 0 pf/ V C Capacitor.7 µf/0 V C0 Capacitor.7 µf/0 V C Capacitor 0 0. µf/ V C Capacitor 0 µf/ V C Capacitor µf/ V C Capacitor µf/ V C7 Capacitor 0 0. µf/ V C Capacitor 0 µf/ V D Default Diode BAV9WS SOD/X. D Schottky Diode SSC Diode SMC D7 Schottky Diode BAS70WS SOD/X. D Schottky Diode BZXB-V % SOD/X. D9 Schottky Diode BAS70WS SOD/X. D0 Schottky Diode BZXB-V % SOD/X. L Inductor IHLPCZ-0 IHLPCZ µh P V IN Pin-through-hole xx P On/Off Pin-through-hole xx Pin-through-hole xx P V O Pin-through-hole --00-xx P 0 V Pin-through-hole --00-xx Q Synch MOSFET Si77DN PowerPAK---single Q Synch MOSFET Si77DN PowerPAK---single Q MOSFET Si0DS SOT Q Synch MOSFET Si7DN PowerPAK---single Q Synch MOSFET Si7DN PowerPAK---single Q7 SOT NPN Silicon ZXTN0F SOT Q MOSFET Si0DS SOT R Resistor 0 K R Resistor 0 0.K R Resistor 0 0R/ % R Resistor 0 K/ % R Resistor 0.K/ % R7 Resistor 0 0 R R9 Resistor 0 00K R0 Resistor 0 00K R Resistor 0 K R Resistor 0 0K S09-0-Rev. B, 0-Mar-09

7 SiP0DB TABLE - IBC PARTS LIST - PART VALUES ARE FOR NARROW INPUT VERSION Designator Description Comment Footprint Quantity Value R Resistor 0 0K R7 Resistor R R Resistor 0.K/ % R9 Resistor 0.K T EI- Planar E-Planar-TFM U PWM CTLR SiP0 MLP--Pitch 0. mm U Temperature Sensor LM-Thermal-Sensor SO-G/P.9 Z Micropower Voltage Reference LM0-V REF SO-G/P.9 TABLE - BASE BOARD PARTS LIST Designator Description Comment Footprint Quantity Value Coax-F Connector H-0 Coax-F Connector H-0 Coax-F Connector H-0 Cap Capacitor C RB-0. 7 µf/0 V Cap Capacitor C RB pf Cap Semi Capacitor (Semiconductor SIM Model) C CR-0 00 pf BAS Silicon Switching Diode for High-Speed Switching D SO-G/C. BAS Silicon Switching Diode for High-Speed Switching D SO-G/C. Fuse Fuse F CR-0 Coaxial-Connection J Test Point Test Point J Test Point Test Point J Header Header, -Pin JP 770 Header Header, -Pin JP 770 MHDRX Header, -Pin JP 7700 MMUNLTG NPN Bipolar Transistor Q SO-G/X.9 Res Resistor R CR-0 K Res Resistor R CR-0.K SW-SPDT SPDT Toggle Switch S ET0MD Test Point Test Point TP 0-7 Test Point Test Point TP 0-7 Test Point Test Point TP 0-7 Test Point Test Point TP 0-7 S09-0-Rev. B, 0-Mar-09 7

8 SiP0DB + VP P V IN P U LM-Thermal-Sensor ON/OFF P HYST V TEMP Z REF ENA + VP LM0-V REF R 00 K % R 00.K % SD V+ V O V IN V REG V det C 00 µf V V cc Isen D BAV9WS C 00 0 P V V REF + VP DH BST VDET VIN V CC LX Q D COMP L U DL CS P 0 A SiP0 SS 9 RDB COSC 7 ROSC V REF Cosc R osc R 00 C R 0R % 00 R µf 00 V K Boot 00 K % Q Si77DN DH C nf V V C 00 R DB nf C R pf V SS 00 0.K % + VP L X 7 Si77DN Rss+ 7 C R9 Si7DN Si0DS 00.7 µf 0 V SD 00K 7 T EI- Planar R Q R0 C SV Q REG 00 SD 0K SG 00K.7 µf 0 V BAS70WS 9 SCT R R Figure. Schematic Q7 ZXTN0F C 00 µf V Aux 7 7 Q Si7DN D7 BAS70WS Aux-R R7 00 0R Aux-DC R 00.K % Pzen D BZXB-V % SG R 00 0K S C µf V Q Si0DS C 00 D IHLPCZ-0 D9 0.7 µh R9 S 00.K 0. µf V SSC S L µf V C S SV+ µf V D0 BZXB-V % C P V O P 0 V S JP Header TP C Cap 7 µf 0 V F C Fuse Cap 00 pf SMB J TP C Cap Semi 00 pf J9 + JP Header TB J S SW-SPDT R Res D K R BAS Res.K TP Q MMUNLTG JP D MHDRX BAS Figure. Schematic - Base Board maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see /ppg?90. S09-0-Rev. B, 0-Mar-09