LF155 LF156 LF157 Series Monolithic JFET Input Operational Amplifiers

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1 LF155LF156LF157 Series Monolithic JFET Input Operational Amplifiers General Description These are the first monolithic JFET input operational amplifiers to incorporate well matched high voltage JFETs on the same chip with standard bipolar transistors (BI-FETTM Technology) These amplifiers feature low input bias and offset currentslow offset voltage and offset voltage drift coupled with offset adjust which does not degrade drift or commonmode rejection The devices are also designed for high slew rate wide bandwidth extremely fast settling time low voltage and current noise and a low 1f noise corner Advantages Replace expensive hybrid and module FET op amps Rugged JFETs allow blow-out free handling compared with MOSFET input devices Excellent for low noise applications using either high or low source impedancevery low 1f corner Offset adjust does not degrade drift or common-mode rejection as in most monolithic amplifiers New output stage allows use of large capacitive loads (5000 pf) without stability problems Internal compensation and large differential input voltage capability Applications Precision high speed integrators Fast DA and AD converters High impedance buffers Wideband low noise low drift amplifiers Logarithmic amplifiers Simplified Schematic Photocell amplifiers Sample and Hold circuits Common Features (LF155A LF156A LF157A) December 1994 Low input bias current 30 pa Low Input Offset Current 3 pa High input impedance 10 12X Low input offset voltage 1 mv Low input offset voltage temp drift 3 mvc Low input noise current 001 pa0hz High common-mode rejection ratio 100 db Large dc voltage gain 106 db Uncommon Features Extremely fast settling time to 001% Fast slew rate Wide gain bandwidth Low input noise voltage LF155A LF156A LF157A Units (A V e5) ms Vms MHz nv0hz LF155LF156LF157 Series Monolithic JFET Input Operational Amplifiers 3 pf in LF157 series TLH BI-FETTM BI-FET IITM are trademarks of National Semiconductor Corporation C1995 National Semiconductor Corporation TLH5646 RRD-B30M115Printed in U S A

2 Absolute Maximum Ratings If MilitaryAerospace specified devices are required contact the National Semiconductor Sales OfficeDistributors for availability and specifications (Note 8) LF155A6A7A LF15567 LF355B6B7B LF35567 LF25567 LF355A6A7A Supply Voltage g22v g22v g22v g18v Differential Input Voltage g40v g40v g40v g30v Input Voltage Range (Note 2) g20v g20v g20v g16v Output Short Circuit Duration Continuous Continuous Continuous Continuous T jmax H-Package 150C 150C 115C 115C N-Package 100C 100C M-Package 100C 100C Power Dissipation at T A e 25C (Notes 1 and 9) H-Package (Still Air) 560 mw 560 mw 400 mw 400 mw H-Package (400 LFMin Air Flow) 1200 mw 1200 mw 1000 mw 1000 mw N-Package 670 mw 670 mw M-Package 380 mw 380 mw Thermal Resistance (Typical) i JA H-Package (Still Air) 160CW 160CW 160CW 160CW H-Package (400 LFMin Air Flow) 65CW 65CW 65CW 65CW N-Package 130CW 130CW M-Package 195CW 195CW (Typical) i JC H-Package 23CW 23CW 23CW 23CW Storage Temperature Range b65ctoa150c b65ctoa150c b65ctoa150c b65ctoa150c Soldering Information (Lead Temp) Metal Can Package Soldering (10 sec) 300C 300C 300C 300C Dual-In-Line Package Soldering (10 sec) 260C 260C 260C Small Outline Package Vapor Phase (60 sec) 215C 215C Infrared (15 sec) 220C 220C See AN-450 Surface Mounting Methods and Their Effect on Product Reliability for other methods of soldering surface mount devices ESD tolerance (100 pf discharged through 15 kx) 1000V 1000V 1000V 1000V DC Electrical Characteristics (Note 3) T A e T j e 25C Symbol Parameter Conditions LF155A6A7A LF355A6A7A Min Typ Max Min Typ Max V OS Input Offset Voltage R S e50xt A e25c mv Over Temperature mv DV OS DT Average TC of Input Offset Voltage R S e50x mvc DTCDV OS Change in Average TC R S e50x (Note 4) with V OS Adjust I OS Input Offset Current T j e25c (Notes 3 5) pa T j st HIGH 10 1 na I B Input Bias Current T j e25c (Notes 3 5) pa T j st HIGH 25 5 na R IN Input Resistance T j e25c X Units mvc per mv A VOL Large Signal Voltage V S e g15v T A e25c VmV Gain V O e g10v R L e2k VmV Over Temperature V O Output Voltage Swing V S e g15v R L e10k g12 g13 g12 g13 V V S e g15v R L e2k g10 g12 g10 g12 V 2

3 DC Electrical Characteristics (Note 3) T A e T j e 25C (Continued) Symbol Parameter Conditions V CM CMRR LF155A6A7A LF355A6A7A Min Typ Max Min Typ Max Input Common-Mode a151 a151 V V S e g15v g11 g11 Voltage Range b12 b12 V Common-Mode Rejection db Ratio PSRR Supply Voltage Rejection (Note 6) Ratio AC Electrical Characteristics T A e T j e 25C V S e g15v Symbol Parameter Conditions Units db LF155A355A LF156A356A LF157A357A Min Typ Max Min Typ Max Min Typ Max SR Slew Rate LF155A6A A V e Vms LF157A A V e Vms GBW Gain Bandwidth Product Units MHz t s Settling Time to 001% (Note 7) ms e n Equivalent Input Noise R S e100x Voltage fe100 Hz nv0hz fe1000 Hz nv0hz i n Equivalent Input fe100 Hz pa0hz Noise Current fe1000 Hz pa0hz C IN Input Capacitance pf DC Electrical Characteristics (Note 3) Symbol Parameter Conditions LF15567 LF25567 LF355B6B7B LF35567 Min Typ Max Min Typ Max Min Typ Max V OS Input Offset Voltage R S e50xt A e25c mv Over Temperature mv DV OS DT Average TC of Input Offset Voltage R S e50x mvc DTCDV OS Change in Average TC R S e50x (Note 4) with V OS Adjust I OS Input Offset Current T j e25c (Notes 3 5) pa T j st HIGH na I B Input Bias Current T j e25c (Notes 3 5) pa T j st HIGH na R IN Input Resistance T j e25c X Units mvc per mv A VOL Large Signal Voltage V S e g15v T A e25c VmV Gain V O e g10v R L e2k Over Temperature VmV V O Output Voltage Swing V S e g15v R L e10k g12 g13 g12 g13 g12 g13 V V S e g15v R L e2k g10 g12 g10 g12 g10 g12 V V CM Input Common-Mode V S e g15v g11 a151 g11 g151 a10 a151 V Voltage Range b12 b12 b12 V CMRR Common-Mode Rejection Ratio PSRR Supply Voltage Rejec- (Note 6) tion Ratio db db 3

4 DC Electrical Characteristics T A e T j e 25C V S e g15v Parameter LF155A155 LF255 LF355A355B LF355 LF156A156 LF256356B LF356A356 LF157A157 LF257357B LF357A357 Typ Max Typ Max Typ Max Typ Max Typ Max Typ Max Supply Current ma AC Electrical Characteristics T A e T j e 25C V S e g15v LF LF LF LF LF Symbol Parameter Conditions B LF356B B LF357B B Units Typ Min Typ Min Typ SR Slew Rate LF1556 A V e Vms LF157 A V e Vms GBW Gain Bandwidth MHz Product t s Settling Time to 001% (Note 7) ms e n Equivalent Input Noise R S e100x Voltage fe100 Hz nv0hz fe1000 Hz nv0hz i n Equivalent Input fe100 Hz pa0hz Current Noise fe1000 Hz pa0hz C IN Input Capacitance pf Notes for Electrical Characteristics Note 1 The maximum power dissipation for these devices must be derated at elevated temperatures and is dictated by T jmax i ja and the ambient temperature T A The maximum available power dissipation at any temperature is P d e(t jmax bt A )i ja or the 25C P dmax whichever is less Note 2 Unless otherwise specified the absolute maximum negative input voltage is equal to the negative power supply voltage Note 3 Unless otherwise stated these test conditions apply LF155A6A7A LF15567 LF25567 LF355A6A7A LF355B6B7B LF35567 Supply Voltage V S g15vsv S sg20v g15vsv S sg20v g15vsv S sg18v g15vsv S g20v V S e g15v T A b55cst A sa125c b25cst A sa85c 0CsT A sa70c 0CsT A sa70c 0CsT A sa70c T HIGH a125c a85c a70c a70c a70c and V OS I B and I OS are measured at V CM e0 Note 4 The Temperature Coefficient of the adjusted input offset voltage changes only a small amount (05mVC typically) for each mv of adjustment from its original unadjusted value Common-mode rejection and open loop voltage gain are also unaffected by offset adjustment Note 5 The input bias currents are junction leakage currents which approximately double for every 10C increase in the junction temperature T J Due to limited production test time the input bias currents measured are correlated to junction temperature In normal operation the junction temperature rises above the ambient temperature as a result of internal power dissipation Pd T j et A ai ja Pd where i ja is the thermal resistance from junction to ambient Use of a heat sink is recommended if input bias current is to be kept to a minimum Note 6 Supply Voltage Rejection is measured for both supply magnitudes increasing or decreasing simultaneously in accordance with common practice Note 7 Settling time is defined here for a unity gain inverter connection using 2 kx resistors for the LF1556 It is the time required for the error voltage (the voltage at the inverting input pin on the amplifier) to settle to within 001% of its final value from the time a 10V step input is applied to the inverter For the LF157 A V eb5 the feedback resistor from output to input is 2 kx and the output step is 10V (See Settling Time Test Circuit) Note 8 Refer to RETS155AX for LF155A RETS155X for LF155 RETS156AX for LF156A RETS156X for LF156 RETS157A for LF157A and RETS157X for LF157 military specifications Note 9 Max Power Dissipation is defined by the package characteristics Operating the part near the Max Power Dissipation may cause the part to operate outside guaranteed limits Units 4

5 Typical DC Performance Characteristics Curves are for LF155 LF156 and LF157 unless otherwise specified Input Bias Current Input Bias Current Input Bias Current Voltage Swing Supply Current Supply Current Negative Current Limit Positive Current Limit Positive Common-Mode Input Voltage Limit TLH Negative Common-Mode Input Voltage Limit Open Loop Voltage Gain Output Voltage Swing TLH

6 Typical AC Performance Characteristics Gain Bandwidth Gain Bandwidth Normalized Slew Rate TLH Output Impedance Output Impedance Output Impedance LF155 Small Signal Pulse Response A V ea1 LF156 Small Signal Pulse Response A V ea1 Small Signal Pulse Response A V ea5 TLH TLH TLH TLH LF155 Large Signal Pulse Response A V ea1 LF156 Large Signal Pulse Response A V ea1 LF157 Large Signal Pulse Response A V ea5 TLH TLH TLH

7 Typical AC Performance Characteristics (Continued) Inverter Settling Time Inverter Settling Time Open Loop Frequency Response Bode Plot Bode Plot Bode Plot Common-Mode Rejection Ratio Power Supply Rejection Ratio Power Supply Rejection Ratio Undistorted Output Voltage Swing Equivalent Input Noise Voltage Equivalent Input Noise Voltage (Expanded Scale) 7 TLH

8 Detailed Schematic C e 3 pf in LF157 series TLH Connection Diagrams (Top Views) Metal Can Package (H) Dual-In-Line Package (M and N) TLH Order Number LF156AH LF155H LF156H LF255H LF256H LF257H LF355AH LF356AH LF357AH LF356BH LF355H LF356H LF357H LM155AH883 LM155H883 LM156AH883 LM156H883 LM157AH883 or LM157H883 See NS Package Number H08C TLH Order Number LF355M LF356M LF357M LF355BM LF356BM LF355BN LF356BN LF357BN LF355N LF356N or LF357N See NS Package Number M08A or N08E Available per JM or JM

9 Application Hints The LF15567 series are op amps with JFET input devices These JFETs have large reverse breakdown voltages from gate to source and drain eliminating the need for clamps across the inputs Therefore large differential input voltages can easily be accomodated without a large increase in input current The maximum differential input voltage is independent of the supply voltages However neither of the input voltages should be allowed to exceed the negative supply as this will cause large currents to flow which can result in a destroyed unit Exceeding the negative common-mode limit on either input will force the output to a high state potentially causing a reversal of phase to the output Exceeding the negative common-mode limit on both inputs will force the amplifier output to a high state In neither case does a latch occur since raising the input back within the common-mode range again puts the input stage and thus the amplifier in a normal operating mode Exceeding the positive common-mode limit on a single input will not change the phase of the output however if both inputs exceed the limit the output of the amplifier will be forced to a high state These amplifiers will operate with the common-mode input voltage equal to the positive supply In fact the commonmode voltage can exceed the positive supply by approximately 100 mv independent of supply voltage and over the full operating temperature range The positive supply can therefore be used as a reference on an input as for example in a supply current monitor andor limiter Precautions should be taken to ensure that the power supply for the integrated circuit never becomes reversed in polarity or that the unit is not inadvertently installed backwards in a socket as an unlimited current surge through the resulting forward diode within the IC could cause fusing of the internal conductors and result in a destroyed unit All of the bias currents in these amplifiers are set by FET current sources The drain currents for the amplifiers are therefore essentially independent of supply voltage As with most amplifiers care should be taken with lead dress component placement and supply decoupling in order to ensure stability For example resistors from the output to an input should be placed with the body close to the input to minimize pickup and maximize the frequency of the feedback pole by minimizing the capacitance from the input to ground A feedback pole is created when the feedback around any amplifier is resistive The parallel resistance and capacitance from the input of the device (usually the inverting input) to ac ground set the frequency of the pole In many instances the frequency of this pole is much greater than the expected 3 db frequency of the closed loop gain and consequently there is negligible effect on stability margin However if the feedback pole is less than approximately six times the expected 3 db frequency a lead capacitor should be placed from the output to the input of the op amp The value of the added capacitor should be such that the RC time constant of this capacitor and the resistance it parallels is greater than or equal to the original feedback pole time constant Typical Circuit Connections V OS Adjustment Driving Capacitive Loads LF157 A Large Power BW Amplifier V OS is adjusted with a 25k potentiometer The potentiometer wiper is connected to V a For potentiometers with temperature coefficient of 100 ppmc or less the additional drift with adjust is 05 mvcmv of adjustment Typical overall drift 5 mvc g(05 mvcmv of adj) LF1556 Re5k LF157 Re125k Due to a unique output stage design these amplifiers have the ability to drive large capacitive loads and still maintain stability C L(MAX) j 001 mf Overshoot s 20% Settling time (t s ) j 5 ms TLH For distortion s 1% and a 20 Vp-p V OUT swing power bandwidth is 500 khz 9

Typical Applications Settling Time Test Circuit Settling

inverter and LF157 connected for A V eb5 FET used to

eb5for LF157 TLH5646 16 Large Signal inverter Output V

TLH5646 17 TLH5646 18 TLH5646 19 Low Drift Adjustable

potentiometers should be wire-wound P1 drift adjust P2 V

10 Typical Applications Settling Time Test Circuit Settling time is tested with the LF1556 connected as unity gain inverter and LF157 connected for A V eb5 FET used to isolate the probe capacitance Output e 10V step A V eb5for LF157 TLH Large Signal inverter Output V OUT (from Settling Time Circuit) LF355 LF356 LF357 TLH TLH TLH Low Drift Adjustable Voltage Reference D V OUT DTe g0002%c All resistors and potentiometers should be wire-wound P1 drift adjust P2 V OUT adjust Use LF155 for X Low I B X Low drift X Low supply current TLH

11 Typical Applications (Continued) Fast Logarithmic Converter Dynamic range 100 ma s I i s 1 ma (5 decades) lv Ol e1vdecade Transient response 3 ms for DI i e 1 decade C1 C2 R2 R3 added dynamic compensation V OS adjust the LF156 to minimize quiescent error R T Tel Labs type Q81 a 03%C lv OUTl e 1 a R2 R T( kt q ln V i TLH R r V REF Ri( e log V 1 i R2 e 157k R T e 1k 03%C (for temperature compensation) R i I r Precision Current Monitor V O e5 R1R2 (VmA of I S ) R1 R2 R3 01% resistors Use LF155 for X Common-mode range to supply range X Low I B X Low V OS X Low Supply Current TLH Bit DA Converter with Symmetrical Offset Binary Operation R1 R2 should be matched within g005% Full-scale response time 3ms E O B1 B2 B3 B4 B5 B6 B7 B8 Comments a Positive Full-Scale a (a) Zero-Scale b (b) Zero-Scale b Negative Full-Scale TLH

12 Typical Applications (Continued) Wide BW Low Noise Low Drift Amplifier Isolating Large Capacitive Loads Power BW f MAX e S r j 191 khz 2qV P Parasitic input capacitance C1 j (3 pf for LF155 LF156 and LF157 plus any additional layout capacitance) interacts with feedback elements and creates undesirable high frequency pole To compensate add C2 such that R2 C2 j R1 C1 Boosting the LF156 with a Current Amplifier Overshoot 6% TLH t s 10 ms When driving large C L the V OUT slew rate determined by C L and I OUT(MAX) DV OUT DT e I OUT j 002 C L 05 Vms e 004 Vms (with C L shown) Low Drift Peak Detector TLH5646 I OUT(MAX) j150 ma (will drive R L t 100X) DV OUT DT e b2 Vms (with C L shown) No additional phase shift added by the current amplifier By adding D1 and R f V D1 e0 during hold mode Leakage of D2 provided by feedback path through R f Leakage of circuit is essentially I b (LF155 LF156) plus capacitor leakage of Cp Diode D3 clamps V OUT (A1) to V IN bv D3 to improve speed and to limit reverse bias of D2 Maximum input frequency should be kk qr f C D2 where C D2 is the shunt capacitance of D2 3 Decades VCO Non-Inverting Unity Gain Operation for LF157 1 R1C t (2q) (5 MHz) R1 e R2 a R S 4 A V(DC) e 1 f b3db 5 MHz Inverting Unity Gain for LF157 f e V C (R8aR7) (8 V PU R8 R1) C 0sV C s30v 10 Hzsfs10 khz R1 R4 matched Linearity 01% over 2 decades TLH R1C t (2q) (5 MHz) R1 e R2 4 A V(DC) eb1 f b3db 5 MHz TLH

13 Typical Applications (Continued) High Impedance Low Drift Instrumentation Amplifier V OUT e R3 R 2R2 R1 a 1 ( DV Vb a 2V s V IN common-mode s V a System V OS adjusted via A2 V OS adjust Trim R3 to boost up CMRR to 120 db Instrumentation amplifier resistor array recommended for best accuracy and lowest drift TLH

14 Typical Applications (Continued) Fast Sample and Hold Both amplifiers (A1 A2) have feedback loops individually closed with stable responses (overshoot negligible) Acquisition time T A estimated by T A j 2R ONV IN C h S r ( provided that V IN k 2qS r R ON C h and T A l V IN C h R ON is of SW1 I OUT(MAX) If inequality not satisfied T A j V IN C h 20 ma LF156 develops full S r output capability for V IN t1v Addition of SW2 improves accuracy by putting the voltage drop across SW1 inside the feedback loop Overall accuracy of system determined by the accuracy of both amplifiers A1 and A2 TLH High Accuracy Sample and Hold By closing the loop through A2 the V OUT accuracy will be determined uniquely by A1 No V OS adjust required for A2 T A can be estimated by same considerations as previously but because of the added propagation delay in the feedback loop (A2) the overshoot is not negligible Overall system slower than fast sample and hold R1 C C additional compensation Use LF156 for X Fast settling time TLH X Low V OS 14

15 Typical Applications (Continued) High Q Band Pass Filter By adding positive feedback (R2) Q increases to 40 f BP e100 khz V OUT e 100Q V IN Clean layout recommended Response to a 1 Vp-p tone burst 300 ms TLH High Q Notch Filter 2R1 e R e 10 MX 2C e C1 e 300 pf Capacitors should be matched to obtain high Q f NOTCH e 120 Hz notch e b55 db Q l 100 Use LF155 for X Low I B X Low supply current TLH

16 16

17 Physical Dimensions inches (millimeters) Metal Can Package (H) Order Number LF156AH LF155H LF156H LF255H LF256H LF257H LF355AH LF356AH LF357AH LF356BH LF355H LF356H or LF357H NS Package Number H08C Small Outline Package (M) Order Number LF355M LF356M LF357M LF355BM or LF356BM NS Package Number M08A 17

18 LF155LF156LF157 Series Monolithic JFET Input Operational Amplifiers Physical Dimensions inches (millimeters) (Continued) LIFE SUPPORT POLIC Molded Dual-In-Line Package (N) Order Number LF355N LF356N LF357N LF355BN LF356BN LF357BN NS Package Number N08E NATIONAL S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or 2 A critical component is any component of a life systems which (a) are intended for surgical implant support device or system whose failure to perform can into the body or (b) support or sustain life and whose be reasonably expected to cause the failure of the life failure to perform when properly used in accordance support device or system or to affect its safety or with instructions for use provided in the labeling can effectiveness be reasonably expected to result in a significant injury to the user National Semiconductor National Semiconductor National Semiconductor National Semiconductor Corporation Europe Hong Kong Ltd Japan Ltd 1111 West Bardin Road Fax (a49) th Floor Straight Block Tel Arlington TX cnjwge tevm2nsccom Ocean Centre 5 Canton Rd Fax Tel 1(800) Deutsch Tel (a49) Tsimshatsui Kowloon Fax 1(800) English Tel (a49) Hong Kong Franais Tel (a49) Tel (852) Italiano Tel (a49) Fax (852) National does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications

LF155/LF156/LF355/LF356/LF357 JFET Input Operational Amplifiers

LF155/LF156/LF355/LF356/LF357 JFET Input Operational Amplifiers JFET Input Operational Amplifiers General Description These are the first monolithic JFET input operational amplifiers to incorporate well matched, high voltage JFETs on the same chip with standard bipolar