Low-Jitter Precision LVDS Oscillator
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- Frank Williams
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1 General Description The DSC0 & series of high performance oscillators utilizes a proven silicon MEMS technology to provide excellent jitter and stability over a wide range of supply voltages and temperatures. By eliminating the need for quartz or SAW technology, MEMS oscillators significantly enhance reliability and accelerate product development, while meeting stringent clock performance criteria for a variety of communications, storage, and networking applications. DSC0 has a standby feature allowing it to completely powerdown when EN pin is pulled low; whereas for, only the outputs are disabled when EN is low. Both oscillators are available in industry standard packages, including the small.x. mm, and are dropin replacements for standard pin LVDS quartz crystal oscillators. Block Diagram Features Low RMS Phase Jitter: < ps (typ) High Stability: ±0, ±, ±0 ppm Wide Temperature Range o Industrial: 0 to 8 C o Ext. commercial: 0 to 70 C High Supply Noise Rejection: 0 dbc Short Lead Time: Weeks Wide Freq. Range:. to 0 MHz Small Industry Standard Footprints o.x.0,.x.,.0x., & 7.0x.0 mm Excellent Shock & Vibration Immunity o Qualified to MILSTD88 High Reliability o 0x better MTF than quartz oscillators Low Current Consumption Supply Range of. to. V Standby & Output Enable Function Lead Free & RoHS Compliant LVPECL & HCSL Versions Available Applications Output Enable Modes EN Pin DSC0 High Outputs Active Outputs Active NC Outputs Active Outputs Active Low Standby Outputs Disabled Storage Area Networks o SATA, SAS, Fibre Channel Passive Optical Networks o EPON, 0GEPON, GPON, 0GPON Ethernet o G, 0GBASET/KR/LR/SR, and FCoE HD/SD/SDI Video & Surveillance PCI Express: Gen & Gen DisplayPort DSC0 Page MKQBPD000
2 Absolute Maximum Ratings Item Min Max Unit Condition Supply Voltage V Input Voltage 0. V DD +0. V Junction Temp +0 C Storage Temp +0 C Soldering Temp +0 C 0sec max. ESD HBM MM CDM Note: 000+ years of data retention on internal memory Specifications V Ordering Code Enable Modes 0: Enable/Standby : Enable/Disable DSC 0 C I.0000 Package A: 7.0x.0mm B:.0x.mm C:.x.mm D:.x.0mm N: 7.0x.0mm (no center pad) Temp Range E: 0 to 70 I: 0 to 8 L: 0 to 0 Stability : ±0ppm : ±ppm : ±0ppm Packing T: Tape & Reel : Tube T Freq (MHz).0000 Parameter Condition Min. Typ. Max. Unit Supply Voltage V DD.. V Supply Current Frequency Stability I DD Notes:. Pin VDD should be filtered with 0.uf capacitor.. tsu is time to 00ppm of output frequency after VDD is applied and outputs are enabled.. Output Waveform and Test Circuit figures below define the parameters.. Output is enabled if pad is floated or not connected. Δf EN pin low outputs are disabled DSC0 0 Includes frequency variations due to initial tolerance, temp. and power supply voltage 0.09 ±0 ± ±0 Aging Δf C ± ppm Startup Time t SU T= C ms Input Logic Levels Input logic high Input logic low V IH V IL 0.7xV DD 0.xV DD Output Disable Time t DA ns Output Enable Time t EN DSC0 Enable PullUp Resistor Pullup resistor exist 0 kω LVDS Outputs Supply Current I DD Output Enabled, R L =00Ω 9 ma Output offset Voltage V OS R=00Ω Differential.. V Delta Offset Voltage V OS 0 mv Pk to Pk Output Swing V PP SingleEnded 0 mv Output Transition time Rise Time Fall Time t R t F 0% to 80% R L =0Ω, C L = pf 0 ma ppm V ms ns 00 ps Frequency f 0 Single Frequency. 0 MHz Output Duty Cycle SYM Differential 8 % Period Jitter J PER. ps RMS Integrated Phase Noise J PH 00kHz to 00kHz to khz to ps RMS DSC0 Page MKQBPD000
3 Rejection (dbc) Phase Jitter (ps RMS) DSC0 Nominal Performance Parameters (Unless specified otherwise: T= C, V DD =. V) mV 00mV..0. MHzLVDS MHzLVDS 0MHzLVDS 0MHzLVDS Supply Noise Frequency (khz) Power supply rejection ratio Lowend of integration BW: x khz to 0 MHz Phase jitter (integrated phase noise) Output Waveform t R t F Output Output 80% 0% 0% 80 0 mv mv /f o t EN t DA V IH Enable V IL Typical Termination Scheme V DD 0.uF 00 Ω 00 Ω DSC0 Page MKQBPD000
4 Temperature ( C) DSC0 Test Circuit Solder Reflow Profile 0 C 7 C 00 C 0 C C C/Sec Max. 080 Sec Pre heat 8 min max C/Sec Max. 00 Sec 00 Sec Reflow C/Sec Max. Cool Time 0 C refer to JSTD00C RampUp Rate (00 C to Peak Temp) C/Sec Max. Preheat Time 0 C to 00 C 080 Sec Time maintained above 7 C 00 Sec Peak Temperature 0 C Time within C of actual Peak 00 Sec RampDown Rate C/Sec Max. Time C to Peak Temperature 8 min Max. DSC0 Page MKQBPD000
5 Package Dimensions 7.0 x.0 mm Plastic Package 7±0.0 [0.7±0.00]. [0.00].±0.0 [0.0±0.00] Plane.[0.00] ±0.0 [0.97±0.00].7 [0.] REF.8 [0.0].8 [0.07].±0.0[0.±0.00]. [0.0]. [0.0] 0.8±0.0 OUT OUT VDD PAD TIE TO GND. [0.0].0 x. mm Plastic Package ±0.0 [0.97±0.00].7 [0.00] 0.±0.0 Plane.7[0.0]. [0.07] REF. [0.07] REF.±0.0 [0.±0.00] 0.8± ±0. [0.079±0.00] OUT OUT VDD 0. [0.0]. [ 0.0] DSC0 Page MKQBPD000
6 . x. mm Plastic Package.±0.0 [0.±0.00].0 [0.0] 0.7±0. [0.079±0.00] Plane [0.0] REF 0.9 [0.0] REF [ 0.09].±0.0 [0.098±0.00] 0.9±0.0 [0.0±0.00] 0.[0.00] REF 0.9 [0.0] 0. [0.97] 0.±0.0 [0.98±0.00] No. Pin Terminal 0.8±0.0 OUT OUT VDD. x.0 mm Plastic Package.±0.0 [0.098±0.00] 0.7±0. [0.079±0.00] 0.8 [0.0] 0. REF 0. REF Plane Via to Power 0.7.0±0.0 [0.079±0.00] 0.7±0. [0.079±0.00] 0.7± REF 0.±0.0 [0.0±0.00] 0.±0.0 [0.099±0.00] ±0.0 OUT OUT VDD 0.±0.0 [0.0±0.00] 0.±0.0 [0.099±0.00] DSC0 Page MKQBPD000
7 7±0.0 [0.7±0.00] 7.0 x.0 mm Plastic Package. [0.00].±0.0 [0.0±0.00] Plane.[0.00] ±0.0 [0.97±0.00].7 [0.] REF.±0.0[0.±0.00]. [0.0]. [0.0] 0.8±0.0 OUT OUT VDD. [0.0] Disclaimer: Discera makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. Discera reserves the right to make changes without further notice to materials described herein. Discera does not assume any liability arising from the application or use of any product or circuit described herein. Discera does not authorize its products for use a critical components in lifesupport systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Discera s product in a lifesupport systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Discera against all charges. DISCERA, Inc. 9 Concourse Drive, San Jose, California 9 USA Phone: + (08) 800 Fax: + (08) sales@discera.com DSC0 Page 7 MKQBPD000
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Features. Applications
Ultra-Precision, 8:1 MUX with Internal Termination and 1:2 LVPECL Fanout Buffer Precision Edge General Description The is a low-jitter, low-skew, high-speed 8:1 multiplexer with a 1:2 differential fanout
BLOCK DIAGRAM. Functionality Table 1 details the differences between the parts to assist designers in selecting the optimal part for their design.
FEATURES LVPECL Outputs Optimized for Very Low Phase Noise (-165dBc/Hz) Up to 800MHz Bandwidth Selectable 1, 2 Output Selectable Enable Logic 3.0V to 3.6V Operation RoHS Compliant Pb Free Packages BLOCK
LOW POWER PROGRAMMABLE OSCILLATOR
LOW POWER PROGRAMMABLE OSCILLATOR SERIES LPOP 1.0 110.0 MHZ FEATURES + Low Power Programmable Oscillator for Low Cost + Excellent long time reliability + Frequency range of 1 MHz and 110 MHz accurate to
Storage Telecom Industrial Servers Backplane clock distribution
1:8 LOW JITTER CMOS CLOCK BUFFER WITH 2:1 INPUT MUX (
CLEARCLOCK POWER OPTIMIZED 0.12ps 5x7mm XO
FEATURES APPLICATIONS 0.125ps typ jitter (150fs MAX f > 200MHz, 25 C) Highest in-class frequency range from 50 to 2100MHz Excellent spurious suppresion 70mA MAX IDD (, any VDD) Lowest in-class power consumption
VC-708 VC-708. LVPECL, LVDS Crystal Oscillator Data Sheet Ultra Low Phase Noise. Description
C-708 LPECL, LDS Crystal Oscillator Data Sheet Ultra Low Phase Noise C-708 Description ectron s C-708 Crystal Oscillator is a quartz stabilized, low phase noise, differential output oscillator which is
SM ClockWorks 10-Gigabit Ethernet, MHz, Ultra-Low Jitter LVPECL Clock Frequency Synthesizer. General Description.
ClockWorks 10-Gigabit Ethernet, 156.25MHz, Ultra-Low Jitter LVPECL Clock Frequency Synthesizer General Description The is a 10-Gigabit Ethernet, 156.25MHz LVPECL clock frequency synthesizer and a member
Low Phase Noise, LVPECL VCXO (for 150MHz to 160MHz Fundamental Crystals) FEATURES. * Internal 60KΩ pull-up resistor
0.952mm VDD QB PL586-55/-58 FEATURES DIE CONFIGURATION Advanced non multiplier VCXO Design for High Performance Crystal Oscillators Input/Output Range: 150MHz to 160MHz Phase Noise Optimized for 155.52MHz:
ClearClock Ultra-Low Jitter & Power Optimized 5.0 x 3.2 mm XO. (3): Stability over OTR. D: ±15ppm over -20 C to +70 C F: ±20ppm over -40 C to +85 C
Features Ultra-Low Jitter: 125 fs Typ RMS (200fs MAX, F>250MHz); spurs included Available with any frequency from 50MHz to 2100MHz Factory programmable; samples available within 1-2 week lead times Lowest
Features. Micrel Inc Fortune Drive San Jose, CA USA tel +1 (408) fax + 1 (408)
2.5V Low Jitter, Low Skew 1:12 LVDS Fanout Buffer with 2:1 Input MUX and Internal Termination General Description The is a 2.5V low jitter, low skew, 1:12 LVDS fanout buffer optimized for precision telecom
Features. Applications. Markets
3.2Gbps Precision, LVPECL Buffer with Internal Termination and Fail Safe Input General Description The is a 2.5/3.3V, high-speed, fully differential LVPECL buffer optimized to provide only 108fs RMS phase
Si52112-A1/A2 PCI-EXPRESS GEN 1 DUAL OUTPUT CLOCK GENERATOR. Features. Applications. Description. output buffers. (3x3 mm) spread spectrum outputs
PCI-EXPRESS GEN 1 DUAL OUTPUT CLOCK GENERATOR Features PCI-Express Gen 1 compliant 3.3 V Power supply Low power HCSL differential Small package 10-pin TDFN output buffers (3x3 mm) Supports Serial-ATA (SATA)
OE CLKC CLKT PL PL PL PL602-39
PL602-3x XIN VDD / * SEL0^ / VDD* SEL^ FEATURES Selectable 750kHz to 800MHz range. Low phase noise output -27dBc/Hz for 55.52MHz @ 0kHz offset -5dBc/Hz for 622.08MHz @ 0kHz offset LVCMOS (PL602-37), LVPECL
SY88149HAL. Features. General Description. Applications. Markets. 1.25Gbps Burst-Mode Limiting Amplifier with Ultra-Fast Signal Assert Timing
1.25Gbps Burst-Mode Limiting Amplifier with Ultra-Fast Signal Assert Timing General Description The is a high-sensitivity, burst-mode capable, limiting-post amplifier designed for FTTH PON optical line
Packaging Outline. 7mm. FN A = Product Family. Frequency Stability *AA = ±20 ppm (-10 to +70 C) *A = ±25 ppm (-10 to +70 C)
Series Crystal Clock Oscillator (XO) 3.3V CMOS Low Jitter XO Actual Size = 5 x 7mm Product Features Less than 1.5 ps RMS jitter with non-pll design 3.3V CMOS/TTL compatible logic levels Pin-compatible
AMJD-SERIES. fout = 27MHz, VDD=1.8V,
FEATURES APPLICATIONS Output selectable between 2 frequencies Compact footprint as small as 1.6x1.2mm Low power consumption 1MHz to 100MHz output frequency range Short lead time for new frequencies Wide
LVDS 5 x 3.2mm 2.5V Oscillator
LVDS 5 x 3.2mm 2.5V Oscillator Features This part is no longer available from Fox, please contact IDT for this product. Model: FXU-LC52 SERIES Freq: 0.016 MHz to 1.35 GHz Rev. 07/08/2015 ULTRA Low Jitter
Solder Dip Options T = Standard S = Sn60Pb40 G=SAC305. Package 86 =Leaded 80 = Formed Leads 85=SMT. VCXO model
Description Q-Tech s 5x7mm LVCMOS Voltage Controlled Crystal Oscillators consist of an IC operating at a supply voltage 3.3Vdc and a miniature strip quartz crystal that operates at the fundamental frequency.
SY58608U. General Description. Features. Functional Block Diagram
3.2Gbps Precision, 1:2 LVDS Fanout Buffer with Internal Termination and Fail Safe Input General Description The is a 2.5V, high-speed, fully differential 1:2 LVDS fanout buffer optimized to provide two