Inverted Sine Carrier for Fundamental Fortification in PWM Inverters and FPGA Based Implementations

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1 SERBIAN JOURNAL OF ELECTRICAL ENGINEERING Vol. 4, No. 2, November 27, Inverted Sine Crrier or Fundmentl Fortiiction in PWM Inverters nd FPGA Bsed Implementtions S. Jeevnnthn 1, R. Nndhkumr 1, P. Dnnjyn 1 Abstrct: This pper dels with novel nturl smpled pulse width modultion (PWM) switching strtegy or voltge source inverter through crrier modiiction. The proposed inverted sine crrier PWM (ISCPWM) method, which uses the conventionl sinusoidl reerence signl nd n inverted sine crrier, hs better spectrl qulity nd higher undmentl component compred to the conventionl sinusoidl PWM (SPWM) without ny pulse dropping. The ISCPWM strtegy enhnces the undmentl output voltge prticulrly t lower modultion index rnges while keeping the totl hrmonic distortion (THD) lower without involving chnges in device switching losses. The presented mthemticl preliminries or both SPWM nd ISCPWM give conceptul understnding nd comprison o the strtegies. The detiled comprison o the hrmonic content nd undmentl component o the ISCPWM output or dierent vlues o modultion index with the results obtined or the SPWM is lso presented. Finlly, the proposed modultor hs been implemented in ield progrmmble gte rry (FPGA- Xilinx Sprtn 3) nd tested with the proto-type inverter. Keywords: Crrier modiiction, Inverted sine crrier pulse width modultion (ISCPWM), PWM inverter, THD. 1 Introduction The hrmonic content in the output o the inverter cn be reduced by employing pulse-width modultion (PWM). The PWM techniques nd strtegies hve been the subject o intensive reserch since 197 s were to bricte sinusoidl c output voltge. Sinusoidl PWM (SPWM) is eective in reducing lower order hrmonics while vrying the output voltge nd gone through mny revisions nd it hs history o three decdes [1-5]. The SPWM technique, however, exhibits poor perormnce with regrd to mximum ttinble voltge nd power. The undmentl mplitude in the SPWM output wveorm is smller thn or the rectngulr wveorm. In three-phse cse the rtio o the undmentl component o the utmost line-to-line voltge to the direct supply voltge is.866% nd this vlue indictes poor exploittion o the dc supply. 1 Pondicherry Engineering College Pondicherry, Indi

2 S. Jeevnnthn, R. Nndhkumr, P. Dnnjyn The reduced circuit complexity delt modultion suitble or hl-bridge inverter ws reported or smooth trnsition between the PWM nd single pulse mode (V/ control) in 1981 [3]. The third hrmonic injection PWM (THIPWM) method suitble or three-phse inverters ws proposed in which modulting wve is obtined by dding the third hrmonic component to undmentl sine in right proportion while the crrier is conventionl tringulr [6]. The triplen hrmonic injection PWM (TRIPWM) is vrition o the THIPWM, in which the modultion unction is obtined by dding the hrmonic components o integer multiples o three to the undmentl sine [7]. In the bove mentioned hrmonic injection PWM methods, it is possible to increse the undmentl bout 15% nd hence better utiliztion the dc power supply. Usge o stircse s modulting unction with high requency tringulr crrier or three-phse ppliction hd demonstrted nerly 1% undmentl improvement in the work reported in 1988 [8]. A modiied crrier PWM methods ws proposed in which ny two djcent cycles o crrier tringulr wve re grouped s either W shpe or M shpe nd then suitbly W nd M cycle group conversions re mde [9]. This type o crrier requires digitl pltorm or its implementtion nd gives bout 4% nd 19% improvements in undmentl component while working lone nd mlgmted with THIPWM reerence respectively. All the previous ttempts to chieve the sme objectives re either regulr smpled or mode-chnging methods. However, in regulr smpled PWM (digitlly bsed controller), the genertion o hrmonics is dominted by quntiztion eects even with requency rtios s low s 8:1 [1] nd hence they il to emulte the properties o (nturl) crrier nd reerence unctions. The nturl smpled solutions viz. THIPWM rely on mode chnging. The purpose o this pper is to propose nturl smpled single mode solution to undmentl restriction nd distortion through the modiiction o crrier unction. The proposed inverted sine crrier PWM (ISCPWM) control scheme or single-phse ull-bridge inverter, which elimintes some o the limittions o the conventionl SPWM viz. poor spectrl qulity o the output voltge, poor perormnce with regrd to mximum output voltge possible etc. This pper lso presents the theory nd mthemticl preliminries o the novel scheme long with the SPWM in ddition to computer simultion. 2 PWM Strtegy A Sinusoidl Pulse Width Modultion The bsic single-phse ull-bridge PWM inverter is shown in Fig. 1 in which S 1 nd S 2 will be given PWM pulses or irst (positive) output hl cycle nd S 3 nd S 4 re gted or the next (negtive) hl cycle. The unipolr PWM pulse genertion with resulting pttern is represented in Fig. 2 in which 172

3 Inverted Sine Crrier or Fundmentl Fortiiction in PWM Inverters tringulr crrier wve is compred with sinusoidl reerence wveorm to generte PWM gting pulses. All PWM wveorms presented in this pper re ssumed to be synchronous Unipolr PWM voltge switching. Fig. 1 Bsic single-phse inverter. Fig. 2 SPWM pulse genertion nd pttern. 173

4 S. Jeevnnthn, R. Nndhkumr, P. Dnnjyn B Mthemticl Anlysis The hrmonics present in the qusi-squre wve nd their reltive mplitudes lwys remin the sme. With PWM, however, the reltive mplitudes o the hrmonics chnge with the modultion index. The use o SPWM in inverters, or ll its technicl beneits, renders most complex clcultions relting to inverter behvior. It is generlly ccepted tht the perormnce o n inverter with ny switching strtegy cn be relted to the hrmonic content o its output voltge [11]. A precise vlue o the switching ngle nd hence duty cycle cn be obtined through the tringulr (crrier) nd the sinusoidl (reerence) equtions. The modultion pttern o the SPWM control (Fig. 2) indictes the switching ngles/ meeting points (p 1, p 2, p 3 p i ). The PWM control signl is obtined by compring high requency tringulr crrier o requency c nd mplitude 1 (per unit) nd low requency sine wve o requency m nd mplitude M (per unit). Equtions or sinusoidl reerence nd tringulr crrier re given by (1) nd (2) respectively. y = M sinx, (1) π rπ x±, y=, (2) 2M 2M where: M - modultion index; M - requency rtio; r-1 or irst pir o tringulr sections (stright lines), 3 or second pir, 5 or third pir nd so on; + - sign should be tken or odd number o line sections nd - - sign or should be tken or even number o line sections. The equtions describing the nturl smpled switching ngles re trnscendentl nd hve the generl distinct solutions or odd nd even meeting points. The condition or switching ngles is given in (3) nd (4) respectively or odd nd even switching ngles. 2M pi M sin p i + = i, i= 1,3,5..., (3) π 2M pi M sinpi = 1 i, i= 2,4,6..., (4) π where i is number o points nd p i is i-th switching ngle. 174

5 Inverted Sine Crrier or Fundmentl Fortiiction in PWM Inverters The pttern represented in Fig. 2 does hve eight switching ngles nd our PWM pulses. The duty cycle cn be clculted by simply dding the width o the individul pulses. The width o ny pulse cn be ound rom subtrcting one odd meeting point rom immedite even successor. Since the inverter output irrespective o control methods exhibits equl positive nd negtive hl cycles, which results in zero dc component ( = ), nd lso does not posses ny even hrmonics due to hl wve symmetry. Eqution (5) gives the generlized Fourier coeicients or the problem considered. In the eqution p i represents switching ngles corresponds to negtive hl cycle. V n n n n, i-1 dc ' ' n= {(sin pk+1 -sin p k)-(sin pk+ 1 -sin p k)} nπ 2 k =1 V b n n n n, (5) i-1 dc ' ' n= {(cos pk+1 -cos p k)-(cos pk+ 1 -cos p k)} nπ 2 k =1 c = + b. 2 2 n n n 3 Proposed ISCPWM The control strtegy uses the sme reerence (synchronized sinusoidl signl) s the conventionl SPWM while the crrier tringle is modiied one. The control scheme uses n inverted (high requency) sine crrier tht helps to mximize the output voltge or given modultion index. Enhnced undmentl component demnds greter pulse re. The dierence in pulse widths (hence re) resulting rom tringle wve nd inverted sine wve with the low (output) requency reerence sine wve in dierent sections cn be esily understood. In the gting pulse genertion o the proposed ISCPWM scheme shown in Fig. 3, the tringulr crrier wveorm o SPWM is replced by n inverter sine wveorm. For the ISCPWM pulse pttern, the switching ngles my be computed s the sme wy s SPWM scheme. The equtions o inverted sine wve is given by (6) nd (7) or its odd nd even cycles respectively. The intersections (q 1, q 2, q 3 q i ) between the inverted sine voltge wveorm o mplitude 1 p.u nd requency c nd the sinusoidl reerence wveorm o mplitude M p.u nd requency cn be obtined by substituting (1) in both (6) nd (7). The switching ngles or ISCPWM scheme cn be obtined rom (8) nd (9). 175

6 S. Jeevnnthn, R. Nndhkumr, P. Dnnjyn Fig. 3 Inverter sine crrier PWM pulse pttern. π y = 1 sin M x ( i 1) 2 π y = 1 sin M x ( i 2) 2 π Msinqi+ sin M q i ( i 1) = 1, i = 1,3, (6) (7) (8) π Msinqi+ sin M q i ( i 2) = 1, i = 2,4,6... (9) 2 It is worth while to note tht both in SPWM (considered) nd ISCPWM schemes, the number o pulses will be equl to M nd hence the constnt switching loss is gurnteed. To hve conceptul understnding o wider pulse re nd hence the dexterous input dc utiliztion in the ISCPWM, loction o switching ngles, duty cycle nd their dependence on M nd M re discussed. Fig. 4 depicts the inluence o M on dierent switching ngles (our ngles considered in both cses) t constnt M o 6. From this igure, it is observed tht the odd switching instnts vry with negtive slope nd even 176

7 Inverted Sine Crrier or Fundmentl Fortiiction in PWM Inverters switching instnts hve positive slope. Vrition o ll the switching instnts ginst M is stright line nd slope o ech one is more thn its previous one. All the odd switching ngles o ISCPWM method hppen erlier thn similr ngles o PWM method, while the sitution is reverse in cse o even switching ngles nd hence higher pulse re. Fig. 5 gives the position o irst switching ngle, p 1/ q 1 or vrious M t two M vlues.4 nd.8. Inluence o M over the switching ngles or M vlue bove 2 is negligible while or the rnge below 2 it lrgely depends on M. Both SPWM nd ISCPWM upshots nonliner reltionship in the lower M rnge. Fig. 6 shows the vrition o duty cycle or dierent M with constnt M. The igure demonstrtes tht duty cycle is higher or ISCPWM throughout the entire rnge o M nd the ustere liner reltionship o duty cycle in SPWM is violted in ISCPWM or lower vlues o M. In ddition, in ISCPWM cuses M dependency o duty. The ISCPWM gives higher duty cycle without ny pulse dropping t given modultion index while mkes the dependency little non-liner. Fig. 7 shows tht the dependence o duty cycle on M t ny M vlue is constnt or even the lowest typicl crrier requency o ppliction. Fig. 4 Inluence o modultion index on switching ngles. 177

8 S. Jeevnnthn, R. Nndhkumr, P. Dnnjyn 35 Point 1 ngle in degree ISCPWM M=.4 ISCPWM M=.8 SPWM M=.4 SPWM M= Crrier requency(m) Fig. 5 Inluence o crrier requency on switching instnt Duty cycle ISCPWM M=1 ISCPWM M=2 SPWM M=1 SPWM M= Modultion Index(M) Fig. 6 Modultion index vs duty cycle. 178

9 Inverted Sine Crrier or Fundmentl Fortiiction in PWM Inverters Duty cycle ISCPWM M=.4 ISCPWM M=.8 SPWM M=.4 SPWM M= Vrying M 4 Simultion Results Fig. 7 Frequency rtio vs duty cycle. To show the eectiveness o the proposed modultor simultion ws perormed or dierent modultion index nd crrier requency vlues. The ISCPWM scheme chieves undmentl voltge vlues o rnge which cn only be obtined by over modultion, i conventionl SPWM scheme is dopted. Fig. 8 shows the output voltge wveorms nd hrmonic spectrums o SPWM nd ISCPWM while Tble 1 nd Tble 2 compres the both methods or undmentl (h 1 ), lower order hrmonics (h 2 -h 9 ), side bnd hrmonics ( 2M ± 1, 2M ± 3,.etc) nd THD or M =.8, M = 15 nd V dc = 3V. The improved undmentl nd reduced THD re evident orm the igure, which gives 19.21% undmentl ortiiction thn SPWM. At M = 1 (verge on linerity), ISCPWM gives 9% higher undmentl thn SPWM, while the ortiiction obtined rom the hrmonic injection methods with pulse dropping nd mode chnging is 15%. The dditionl dvntge in the ISCPWM is, it does not require ny mode chnging like THIWPM. Regrettbly, the ISCPWM cuses mrginl increse in the lower order hrmonics, but except third hrmonics ll other hrmonics re in cceptble level (less thn 5%). It is worth noting tht or three-phse pplictions, the heightened third hrmonics need not be bothered. 179

10 S. Jeevnnthn, R. Nndhkumr, P. Dnnjyn Output voltge time (s) M=.8,M=15,Fc=15Hz,THD=72.19% Mg (% o 5 Hz component) Fundmentl Output(5 Hz)= V THD=57.67% Frequency (Hz) 4 () SPWM Output voltge time (s) Mg (% o 5 Hz component) Fundmentl Output (5 Hz)= V THD=57.67% Frequency (Hz) (b) ISCPWM Fig. 8 Output voltge wveorms nd their hrmonic spectrum. 18

11 Inverted Sine Crrier or Fundmentl Fortiiction in PWM Inverters Tble 1 Comprison o THD, undmentl nd lower order hrmonics. Method THD (%) h 1 (V) h 3 (V) h 5 (V) h 7 (V) h 9 (V) SPWM ISCPWM Method Tble 2 Comprison o higher order hrmonics. 2M 3 h 27 (V) 2M 1 h 29 (V) 2M + 1 h 31 (V) 2M + 3 h 33 (V) SPWM ISCPWM Method 4M 3 h 57 (V) 4M 1 h 59 (V) 4M + 1 h 61 (V) 4M + 3 h 63 (V) SPWM ISCPWM Fig. 9 Vrition o undmentl with modultion index. Fig. 9 shows the complete undmentl component working rnge s unction o M while the Fig. 1 presents the corresponding THD vlues. The 181

12 S. Jeevnnthn, R. Nndhkumr, P. Dnnjyn ISCPWM method gives higher undmentl throughout the inverter working rnge. Its perormnce is more pprecible in lower modultion index rnges. For instnce, t M =.1, ISCPWM gives undmentl component vlue three times o SPWM t the sme time the THD vlue 4% less. Fig. 11 shows the vrition o undmentl component with the THD. Hence, the ISCPWM scheme is more vorble thn the SPWM technique or use in the inverter Unipolr PWM Inverter Inverted sine crrier THD% (1.31, ) Modultion Index(M) Fig. 1 Vrition o THD with modultion index. 4 Fundmentl output voltge Rectiied sine Inverted sine THD% Fig. 11 Vlues o THD or vrious output undmentl. 182

13 Inverted Sine Crrier or Fundmentl Fortiiction in PWM Inverters A Overmodultion Output voltge in volts time (s) Output voltge in volts time (s) Mgnitude o undmentl Fundmentl voltge= V THD=33.84% Frequency (Hz) Mgnitude o undmentl Fundmentl Voltge= V THD=37.41% Frequency (Hz) () SPWM (b) ISCPWM Fig. 12 Output voltge nd requency spectrum-overmodultion. To increse the undmentl mplitude urther in the SPWM technique the only wy is incresing the M beyond 1., which is clled s n overmodultion. Overmodultion cuses the output voltge to contin mny more low order hrmonics (3, 5, 7 etc.) nd lso the mkes the undmentl component-modultion index reltion non-liner liner. As M increses the on-time become proportionlly lrger nd improves the vlue o the undmentl component in non-liner mnner. As the proposed ISCPWM gives improved undmentl component, to some extend it replces the overmodultion nd voids pulse dropping. For still higher vlues o undmentl, ISCPWM lso hs eqully good opportunity to work in the overmodulted region. To understnd the perormnce o the schemes in overmodultion rnge, the simulted spectrl outputs re presented in Fig. 12 or M = 1.8. The result shows tht though the ISCPWM works better thn the trditionl SPWM in overmodultion; its perormnce cn not pprecited to the extent s in liner rnge. B Amlgmtion The reerence modiiction in hrmonic injection PWM methods nd crrier modiiction in the proposed ISCPWM im t incresing the undmentl

14 S. Jeevnnthn, R. Nndhkumr, P. Dnnjyn through increse in the pulse re. As the im o both the modiictions is sme, mlgmtion o both reerence nd crrier modiictions will improve the sitution urther. On the bsis o this intuitive notion, it is logicl to mlgmte the inverted sine crrier with third hrmonic nd triplen hrmonic injected reerence wveorms my be mlgmted in the three-phse system to improve the system urther. Fig. 13 depicts such results obtined rom mlgmted opertion with third hrmonic injection reerence, which results in 19.73% enhncement in undmentl thn SPWM, which is greter thn the ortiiction obtined when triplen hrmonic injected reerence lone is used. Output voltge in volt time (s) Mgnitude % o undmentl 2 Fundmentl Voltge= V 15 THD%= Frequency (Hz) Fig. 13 Output voltge nd requency spectrum-mlgmted opertion. 5 Hrdwre Implementtion FPGA belongs to the wide mily o progrmmble logic components [13]. Their densities re now exceeding 1 million gtes [14]. The rchitecture is composed o mtrix o CLB, which is bordered by ring o conigurble input/output blocks (IOB). All these resources communicte mong themselves through progrmmble interconnection network nd lso it to PWM signl, where it is subjected into certin hrdwre-oriented constrints. The lgorithm uses the LUT or the sine reerence nd tringulr/inverter sine crrier unctions. The system (bord) clock is divided nd djusted with the dt count in LUT s. The crrier dt is repetedly clled or M times recursively nd compred with the sine reerence dt bsed on TRR lgorithm [15]. When the reerence is greter thn the crrier dt, pulse will be produced. The trget technology uses one o the Xilinx series o FPGA. The circuit hs been designed using VHDL, synthesized, plced nd routed using the Xilinx 184

15 Inverted Sine Crrier or Fundmentl Fortiiction in PWM Inverters integrted service environment. The unctionlity o the inl net list/design veriiction or the pulse genertion hs been completed using ModelSim SE- EE5.4e simultor in project nvigtor s evidenced in Fig. 14. Ater veriying the design by simultion, synthesis is crried out. Finlly plcement, routing nd timing optimiztions re perormed. A proto-type inverter hs been constructed using IRF84 MOSFET. Both SPWM nd ISCPWM modultors hve been tested with the help o SRAM-FPGA bsed Xilinx mily sprtn-3 XC3S4-4-pq28. The XC3S4-4 pq28 hs 4K logic gtes, logic cells 864, CLB is 896, distributed RAM bits 56K, nd mximum user input/output is 264. The representtive downloded pulses re cptured using luke scope (199C series) nd re shown in Fig. 15. Fig. 14 ModelSim Simultor Output Results. Pulse 1 Pulse 4 Fig. 15 FPGA generted Switching Pulses 1 nd

16 S. Jeevnnthn, R. Nndhkumr, P. Dnnjyn 6 Conclusion The pper presents novel PWM scheme or controlling the output o n inverter with improved undmentl component vlue. The min dvntge o this pproch is tht it dopts consistent strtegy or the entire rnge o modultion index i.e. it does not require ny mode chnge nd lso cuses exctly sme number o switching per cycle. The pprecible improvement in THD in the lower rnge o modultion depth ttrcts drive pplictions where low speed opertion is required. The reduced distortions even t low modultion depth provide scope or proposed scheme not only when higher undmentl demnded nd lso obtining low undmentl vlues. This pper lso presents systemtic wy to nlyticlly chrcterize both SPWM nd ISCPWM. The drwbcks o the proposed scheme re mrginl boost in the lower hrmonics nd non-liner undmentl nd M reltion. 7 Reerences [1] Michel A. Boost, Phoivos D. Ziogs: Stte-o-the-Art Crrier PWM Techniques: A Criticl Evlution: IEEE Trnsctions Industry Applictions, Vol. 24, No. 2, pp Mrch/April [2] Jochim Holtz: Pulse width Modultion-A Survey, IEEE Trnsction Industril Electronics, Vol. 39, No. 5, pp , Dec [3] Phoivos D. Ziogs: The Delt Modultion Technique in Sttic PWM Inverters, IEEE Trnsctions on Industry Appliction, Vol. 1 A-17, pp , Mrch/April [4] S. Jeevnnthn, P. Dnnjyn, A. Mohmed Asi Fisl: A HPWM Method or Therml Mngement in Full-Bridge Inverter with Loss Estimtion nd Electro-Therml Simultion, AMSE Periodicls o Modeling, Mesurement nd Control Series B: Vol. 73, No. 6, pp. 1-2, December 24. [5] P. Enjeti, P.D. Ziogs, J.F. Lindsy: Progrmmed PWM Techniques to Elimintes Hrmonics-A Criticl Evlution, IEEE IAS Conerence Record, pp , [6] J.A. Houldsworth, D.A. Grnt: The Use Hrmonic Distortion to Increse the Output Voltge o Three-Phse PWM Inverter, IEEE Trnsction on Industry Appliction, Vol. 1 IA-2, pp , Sept./Oct [7] K. Tniguchi, Y. Ogino, H. Irie: PWM Technique or Power MOSFET Inverter, IEEE Trnsctions on Power Electronics, Vol. 3, No. 2, p.p , July [8] Kjeld Thorborg, Ake Nystrom: Stircse PWM: An Uncomplicted nd Eicient Modultion Techniques or AC Motors Drives, IEEE Trnsctions on Power Electronics, Vol. 3, No. 4, pp , Oct [9] S. Jeevnnthn, P. Dnnjyn, S. Venktesn: A Novel Modiied Crrier PWM Switching Strtegy or Single-Phse Full-Bridge Inverter, Irnin Journl o Electricl nd Computer Engineering, Summer Fll - Specil Section on Power Engineering, Vol. 4, No. 2, pp , Tehrn, Irn, 25. [1] W.G. Dunord, J.D. Vn Wyk: The Clcultion o Sub-Hrmonics in n Asynchronous PWM Induction Motor Drive, Proceedings o IEEE PESC Conerence Record, pp ,

17 Inverted Sine Crrier or Fundmentl Fortiiction in PWM Inverters [11] S. Jeevnnthn, P. Dnnjyn, S. Venktesn: SPWM-An Anlyticl Chrcteriztion, nd Perormnce Apprisl o Power Electronic Simultion Sotwres, Proceedings o Interntionl Conerence on Power Electronics nd Drive Systems (PEDS25), Kull Lumpur, Mlysi, pp , Nov. 28-Dec. 1, 25. [12] Xilinx Dt Book, 26, vilble: [13] J.M. Reti, B. Allrd, X. Jord, A. Perez: Use o ASIC s in PWM Techniques or Power Converter, IEEE IECON Conerence Record, pp , [14] S. Jeevnnthn, S. Rkesh, P. Dnnjyn: A Uniied Time Rtio Recursion (TRR) Algorithm or SPWM nd TEHPWM Methods: Digitl Implementtion nd Mthemticl Anlysis, Technicl Review-Journl o The Institution o Electronics nd Telecommuniction Engineers, Vol. 22, No. 6, pp , Jn./Feb.,