ARN-21D Solid State Modulator - A/A mode

Transcription

1 ARN-D Solid State Modulator - A/A mode Power Requirements for the solid state air-to-air modulator shall not exceed the following under any combination of normal operating conditions: 0.5 volts RMS, 0 to 00 cps Vdc 0.6 0V dc.5 -0 or 80V dc Specifically, the solid state air-to-air modulator contains the following circuits: () Interrogation PRF Generator 7 Hz or 50 Hz () Interrogation Encoder µs interpulse time () Transmission Pulse Shaping Gaussian, µs at 50% height () A/A decoder Reply all double pulses except at early gate (5) A/A System delay 6 µs total (6) A/A AGC sec time constant for low pulse rate (7) A/A Over-Interrogation Countdown max. 50 pulses/s (8) Transmitter Muting also on A/A T/R switchover to protect mixer (9) First Pulse generator Dead Time 5 µs Automatic Gain Control (A/A) - An adjustable air-to-air AGC shall be provided such that it is possible to reject the weaker of two signals when they differ by an amount between 5 and 5dB. This AGC shall be generated by properly coded interrogations and shall require no more than seconds to reach 90% of the final value determined by any instantaneous change in the interrogation signal level. Transmitter Power (A/A) - When the total transmission rate is between and 0 pulse pairs per second, the peak power shall be the same as that transmitted in the normal mode when tracking a distance reply signal from a ground beacon. A maximum reduction in peak power of db is permissible when the total transmission rate is 50 pulses per second. Transmitter Muting Satisfactory muting of the transmitter shall be provided during channel selection in the air-to-air mode and in the T/R mode, as well as while switching from A/A to T/R or from T/R to A/A to protect the mixer diode. Over-interrogation The transmitter shall not be capable of transponding at a rate in excess of 50 pulses per second. System Delay (A/A) - The transponder reply pulse shall occur 6 ± microseconds after the receipt, at the antenna terminal, of the first pulse of a coded interrogation pair. The distance indicator of the interrogating Radio Set AN/ARN-D shall display 0 ± 0. miles upon receipt of a reply pulse at its antenna terminal 6 microseconds after transmission of the first interrogation pulse. Dead time gate All time shared random triggers, both interrogations and reply, shall be inhibited for 5 ± 5 microseconds after the generation of either the first interrogation pulse or an air-to-air reply pulse. Adjustments - Screwdriver adjustments shall be provided to set the interrogation PRF, the interrogation pulse pair spacing, the air-to-air system delay time, and the air-to-air AGC. Interrogation sync An interrogation sync terminal shall be provided on the modulator chassis. The terminal shall be readily accessible when the receiver-transmitter dust cover is removed for maintenance or test.

2 8 6 B A +8V A/A mode H K P70 5 Hi/Lo band C P70 F 5V ac 00Hz D J L E 9 7 opens at high altitude search +? khz channel motor -0 early gate RX B C D K F H 0Ω CR70 N57 90k 0k 0k M7 R76-50 k R75 50Ω R755 50Ω x.5uf M7 50k 0p 65 Q7 CR70 N57 00Hz jitter -V -50V k nf 8 B 69 CR75 N8 k 560k k n 0 k Q706 0k nf M 500pF 0k 70 Q707 blue: board node number P70 module connector pin P70 connector pin not connected 5 +0V 0 -V L70 Q70 67 E 5k +8V mh mh PRF GENERATOR 8 6 L70 a-b-c-d 9 +5V L70 mh R70 blue R70 Reverse engineered drawing Draft may contain errors nf 0k N A/A Q705 k nf k R758 50Ω Q709 each 0 Ω 9 5nF 0k PRF R k n agc 50V* Q708 0.uF 0µs 0.5uF J 5 dec 05 kb purple 7k +7 A/A * Shockley -layer diode E50 M-8 n TP uh Q70 N65 uh Q70 N65 M % k7 M 5pF MODE CONTROL? L70.5nF 8mH 9µs uf 6B k uf 55 TP 0 C7 0.7uF C75 0.uF C76 0.uF CR79 N57 8k Q70 9k C7 0.7uF uf T70 6 TP uf nf 0k 6 500p agc 0k ma +5 n T70 7 nf 7 0 k 50p 5 50V* 0 k 9A uf A/A AGC B 5us kv kv 5 00V 0 V Z7 MODULATOR, SOLID STATE MD-7 / ARN-7 A / A MODE 7 +0 All transistors N uF k 0.5uF nf Q70 8 0k k7 hold-off +5V 50k R7 nf 560 0nF TP Q70 5k6 80k 6 5 start phantastron pressure switch? +8V 0.u uf -50V

3 Description of circuit parts Pulse forming network uh 0.7uF 00V A 0V B mh 0.uF N65 9Ω L prim 0.mH Each PFN has two capacitors (0.uF and 0.7uF), both charged to twice the input voltage. After the pulse there is a negative voltage across the thyristor for commutation. The input voltage here was only 0Vdc, and the pulse output was minus 70V peak into a 9 Ω resistor that was used as dummy load instead of the HV xformer. The upper trace shows this output voltage at point "A" in the diagram above, while the lower trace "B" shows the input voltage after the saturating choke. The dotted line shows the simulated waveform when the main inductance of the primary is added. The capacitors of the pulse forming network (PFN) are recharged via an mh choke to twice the DC voltage, resulting in a 90us half cycle charging current with a peak value of A. Choke L70 isolates the thyristor discharge from the DC input circuit until us after the start of the first pulse, when choke L70 saturates from approx. H down to 0.mH. The stored energy in each PFN is 0.5 x 0.8uF x 00V = 6mJ, enough for a 5kW x us pulse. The peak thyristor current is 75A, a negative Vak is present for 0 us to recover the thyristor. Muting The transmitter is d when - pin is tied to -0V when the channel selector motor runs ( as in ARN-B and -C) - when the preselector cavity coils change state. This happens when the ch 6-6 border is passed, or when the A/A mode is switched on or off. A/A mode switching The change from normal mode to the Air-to-Air (A/A) mode requires the following actions: - Bypass the twin-pulse detection in the receiver (use only the us delayed video); - Enable the reply on any interrogation except the one that coincides with the early gate in the range tracking circuit ; - Swap the control wires to the prescaler cavity ; - Use slower Automatic Gain Control (AGC). For these functions, an extra connector P70 is added to the modulator.

4 +8V A/A mode k Enable A/A reply and AGC D Hi/Lo band K F H k R75 50Ω 69 R755 50Ω Q7 +8V Q707 E J Preselector cavity switch coils In normal mode, input F is made inoperative, and - when the hi-lo switch pulls H high, then Q707 conducts, so E is high ( and J is low) - when the hi-lo switch pulls F high, then Q707 conducts not, so E is low ( and J is high) In A/A mode, input H is made inoperative, so - when the hi-lo switch pulls H high, then Q707 conducts not, so E is low ( and J is high) - when the hi-lo switch pulls F high, then Q707 conducts, so E is high ( and J is low) When the new modulator is placed in an original ARNB or C chassis, then connector P70 stays in its storage position, and the hi/lo switch connects directly to the normal preselector cavity switch coils. Pulse Repetition Frequency (PRF) generator. The generator has a slowly charging capacitor and a blocking oscillator around Q70. When the capacitor voltage rises above +V then Q70 starts to conduct, and stays on due to positive feedback until the core of T70 saturates which blocks T70. During the (5µs) pulse, the timing capacitor gets a negative shot, and the cycle repeats. The pulse triggers thyristor Q70, and starts the range circuit in the ARN. Second pulse delay. The negative slope (00V in us) on the anode of thyristor Q70 starts a delay of 9us around L70, so the time from triggering Q70 until triggering of Q70 is µs. This gives the second pulse as required in normal Tacan operation. Received pulses. In A/A mode, the airborne set shall respond any received dual pulse with a single pulse such that the delay from the first received pulse until the response pulse is 6 µs. Only a received pulse that V +7 A/A coincides with the range gate shall not be retransmitted to prevent eternal retransmission. early gate RX B C 90k 0k -V -50V 560k k n Q70 Q705 k 9 The receive gate circuit has 5 diodes. The voltage between the diodes is -V with open inputs, and only the two output diodes conduct. Base voltage of Q70 is negative and both transistors are off. But how this works... A/A system delay The group delay in the IF strip is 5us, the video input delay line adds us, and the detection delay of the range circuit is us. The delay of the modulator is us, so the delay circuit around L70 of 9us was added to bring the total system delay to 6us.

5 AGC In A/A mode, only 0 single pulses per second may be received, instead of 700 twin pulses in normal Tacan operation. The normal ARN automatic gain control would fully open the IF amplifier, as if nothing was received. A special circuit in the ARND modulator was added to pull the AGC line negative with a sec averaging time Hold-off A circuit around Q70 prevents further triggers for 0us. The first pulse in normal operation is not affected. This is not needed, this thyristor is fired only 0 or 50 times per second. Coil data Inductors L70 a-b charger mh 0. Ω L70 c-6 pulseform uh 0 L70 us delay 8mH 6 Ω L70 5us delay mh 6 Ω L70 DC choke 7 H or 0uH 0. Ω saturates at 0V x 0us = mvs ( 5mA) turns ratio : Core reset bias : 0V/ 5kΩ = 8mA Pre selector cavity switch coils Ω and 0 Ω Transformers T 70 Blocking osc. - 0 Ω 0V pulse ( sec) Blocking osc. - 0 Ω 5V pulse (prim) Blocking osc Ω 0V pulse ( reset timing capacitor) T 70 Primary 0V 0. Ω HV kv Ω HV kv 8 Ω HV 00V Ω Primary impedance. mh // 66Ω // 7nF ( resonant at 7 khz)

6 Analysis of the half-cycle LC circuits The ARND modulator has many half-cycle LC- circuits: - Power circuits forming the first or second high voltage pulse; - The LC circuit making the us delay between them; - The LC circuit that makes the system delay in the A/A mode.. Pulse forming network +0V 0 -V L70 5k mh blue uh Q70 N65 second PFN identical 0.7uF 0.uF T70 kv The PFN of the ARN-D Solid State Modulator is simulated without the HV transformer, instead a 5Ω resistor is used as load, the peak output is (00Vp) / 5Ω =.6kW peak. The peak current in the thyristor is approx. 70A The peak current in the recharge inductor is A. To get in the simulation a positive pulse on the output, all diodes and the thyristor were inverted, and the source voltage was -0V. Available commutation time is us in the model, but 5us in reality?!

7 . The us delay circuit The us delay from first to second thyristor is needed to transmit the normal twin Tacan pulse Q70 nf 560 9µs.5nF 0.5uF L70 8mH TP Q70 500p 50 0k 50 Hold-off voltage The first thyristor (Q70) is periodically triggered by the PRF generator with approx. 0 or 50 pulses per second. Each triggering causes a sharp negative slope of the anode voltage of Q70. This negative slope causes a half cycle current surge in the 8mH and.5nf timing elements. After 9us, the current reverses, producing a 0V peak at testpoint TP, and a 0V peak above the hold-off voltage at node 50. With +0V hold-off voltage, this should fire the diac and the thyristor, but it doesn't. Simulation shows that the peak at node 50 is only V?! When Q70 does fire, then the hold-off voltage drops suddenly to say -0V, and this commutates the diac and the thyristor. Otherwise the gate pulse would stay high, and the thyristor would stay on, shorting the 0V power supply... Simulation The source wave emulates the anode waveform of Q70. This is the input to the "us" delay circuit. The large negative voltage (-0V) causes a negative half cycle current in the coil. When the current reverses, there is a moderate positive peak on the output. Another -layer diode is between the output of the 0us delay circuit and the gate of Q70, biased by the hold-off voltage. Once the -layer diode is triggered, a dc gate current to the thyristor starts until the negative slope of its anode voltage pulls down the hold-off voltage to -0V. This ends the gate pulse, and prevents a re-trigger within 5us until the hold-off voltage is back to at least +0V.

8 . The 50us delay circuit. k 0k Q706 nf 50V* 8 0k 5nF nf 0k TP L70 mh 500pF 0µs 50pF 0k +5V A/A The voltage on (input) node 8 shoots to -0V until the diac breaks down, and Ccap (5nF) is discharged in Ω x 5nF = 0.5us. (TP discharges in 0.6us from 5 to 5V which is not relevant for the timing). The negative pulse on node 8 is only 50ns wide. Then, Ccap re-charges in 0µs to +0V via the coil. The current in the coil is a half wave from right to left on the drawing. At the end of the half cycle, the current direction will reverse giving a damped oscillatory wave at 00 khz due to the 50pF capacitance of the probe and diodes at TP. Ccap is charged to approx. V above the +5V A/A line. On the screenshot, TP is the upper trace, node 8 is the lower trace. The small negative peak is not well visible on this scale. The bottom voltage from the TP waveform is the "+5 A/A" bus, which is +5V at 000 pulses/s, or +6.5V at 00 pulses/sec. The output circuit (500pF and diodes) is a peak rider, providing a waveform that can trigger the output -layer diode The rest of the cycle is described in the previous us paragraph. Simulation The start pulse is simulated by a pre-charged nf input capacitor.