A Low Loss Wide Swing Cascode Current Mirror in 0.18-μm CMOS Technology

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1 Journal of Applied Sciences Research, 8(8): , 2012 ISSN X This is a refereed journal and all articles are professionally screened and reviewed 4096 ORIGINAL ARTICLES A Low Loss Wide Swing Cascode Current Mirror in 0.18-μm CMOS Technology Khairul Affendi Rosli, Md. Mamun, Mohammad Arif Sobhan Bhuiyan, and Hafizah Husain Department of Electrical, Electronic and Systems Engineering, Universiti Kebangsaan Malaysia, Bangi, Selangor, Malaysia. ABSTRACT Current mirror is an essential component in analog integrated circuit design for biasing and constant current generation. In this paper a design of a wide swing cascode current mirror circuit (WSCCM) is proposed by using Mentor Graphics Design Architect and IC Station which is implemented by using CEDEC 0.18-μm CMOS process. The widths of the transistors are varied to obtain best performance current mirror. For a width of 6 µm, µa output saturated current is obtained. Besides, at this width the current reaches the saturation very quickly at a voltage of 0.44V. The results show that the circuit is able to obtain a minimum bias voltage, lower power dissipation and quicker saturation region than the previous works. Key words: CMOS, WSCCM, Current Mirror. Introduction A current mirror is a circuit designed to copy a current through one active device by controlling the current in another active device of a circuit, keeping the output current constant regardless of loading. Conceptually, an ideal current mirror is simply an ideal inverting current amplifier that reverses the current direction as well or it is a current-controlled current source (CCCS) (Hitesh and Goel, 2012; Reaz et al., 2006; Singh et al., 2009; Marufuzzaman et al., 2010; Akter et al., 2008; Reaz et al., 2007). It is a very useful building block in analog integrated circuit design and widely used in the biasing circuits in many analogue and digital systems as well as in constant current generation circuits (Reaz et al., 2005; Akter et al., 2008, Mohd-Yasin et al., 2004; Reaz et al., 2003). In many analog circuit applications, the performance of the current mirror focuses on the high accuracy, high output impedance, wide output voltage range, wide current mirroring range, and fast current switching time (Yang et al., 2008). Although there are several current mirror architectures demonstrated in different literatures (Sampietro et al., 2000; Sarao et al, 2002; Tseng et al., 2007; Kim et al., 2008; Azhari et al., 2011; Petrellis et al., 2012; Gupta and Sharma, 2012) but figure 1 shows the typical and most basic current mirror configuration using MOS devices. Fig. 1: Basic MOSFET current mirror. The studies and analyses on design and performance of Current mirror circuits are going on for the last couples of years (Tseng et al., 2007). In this paper an improved design of the wide swing cascode current mirror in purpose to reduce power dissipation and to increase performance through MOS devices width adjustment. Architecture Of Current Mirror: A high-swing current mirror includes a cascode current source and a current source bias circuit (Shukla et al., 2011). The current source includes first and second bias terminals and an output terminal whereas the bias circuit includes transistors Q 1, Q 2, Q 3 and Q 4. Transistor Q 1 has a gate, source, and drain, with the gate coupled to the drain. Transistor Q2 has a gate, source, and drain, with the gate and source of transistor Q 2 coupled to the Corresponding Author: Mohammad Arif Sobhan Bhuiyan, Department of Electrical, Electronic and Systems Engineering, Universiti Kebangsaan Malaysia, Bangi, Selangor, Malaysia. arifsobhan.bhuiyan@gmail.com

2 4097 gate and source, respectively, of transistor Q 1. Transistor Q 1 has a gate and drain coupled to one another and to the second bias terminal and a source coupled to the drain of transistor Q 3. Transistor Q 3 has a gate and drain coupled together and to the first bias terminal and a source coupled to the sources of transistors Q 3 and Q 4. The schematic diagram of proposed wide swing cascade current mirror is shown in figure 2. Fig. 2: Schematic diagram of typical wide swing cascade current mirror. The wide swing current mirror represents an excellent accuracy with high output swing. As the structure with high output impedance is more convenient so in the purposed design output impedance is kept high (Blazes, 1991). The wide-swing cascode current mirror is a variant on the cascode on a lower bias voltage. Its small-signal behaviour is identical to the regular cascode, but its biasing is quite different. The extra MOSFET Q 5 is simply to ensure the rest stay in saturation. The biasing voltage is usually minimum as it is the total drain to source voltage of Q 2 and Q 4 (Nojdelov and Nihtianov, 2009). The output voltage is given by the total of bias voltage and drain to source voltage of Q 2 and Q 4 respectively. So the special arrangement and sizing of the MOSFETs ensures that Q 3 is always just on the edge of saturation and never switches off. In other words, we have to ensure that V GS1 < 2V t. So Q 1 is not on automatically we must ensure it is switched on by keeping its V GS below 2V t. This is not difficult to do, and usually follows automatically from the arrangement and sizes of the devices. The drawback of standard cascode current mirror is its higher input and output compliance voltage (Fiocchi and Gatti, 1999). This high swing cascode topology shown in Figure 3 is better alternate as it provides the same output resistance as of standard cascode but it provides low input and output compliance voltage in comparison to standard cascode structure. An additional transistor M 5 is added in series with M 1 so as to make the drain voltages of M 1 and M 2 to be identical, thus eliminating any error because of channel length modulation. Fig. 3: High swing cascode current mirror (initial design without M5).

3 4098 Fig. 4: The schematic design of WSCCM using Design Architect software. The schematic diagram of the circuit is shown in Figure 4. After the schematic was checked and saved, then the symbol was generated for our test bench part for testing purposes. The layout for the circuit is then created in IC Layout of Mentor Graphics. Figure 5 shows the IC layout design for this circuit. Fig. 5: IC Layout for WSCCM. A single resistor placed between V DD and drain of M 4 -NMOS transistor as shown in the schematic plays an important role in decrement of saturation time of the proposed WSCCM. The resistor, R 1 actually helped the mirror side of NMOS to reach the threshold and became saturated within a shorter period. Continuing to use the cascode method to increase the DC gain of the circuit quickly destroys the output swing of the circuit as each transistor needs to have a threshold voltage across it. To overcome this, increase in the output resistance (decreasing lambda) of the circuit is needed (Kim et al, 2008). This can be done by using an extra transistor as an amplifying feedback loop to the cascading transistor as was done by M 5. Results And Discussions Simulation has been done with Mentor Graphics DA-IC for output current of the circuit as a function of different width sizes of NMOS transistors and the result is plotted in figure 8 below.

4 4099 Fig. 6: The output current obtained from different transistor width. From the figure it is found that the greater the width of NMOS the better the performance in the mirror side. The red colour line in the graph shows the most stable output compared to others. The 6.0 µm width of MOSFEt also enables a slight quicker saturation region than other sizes. The result is also represented in tabular form in table 1 below. Table 1: Transistor width and output saturated current. Transistors width Output saturated current 1.0 µm µa 3.0 µm µa 6.0 µm µa However, the M 5 -NMOS transistor should be exactly or closely to W/L ratio of 1 because this transistor supplies the gate bias of M 3 and M 4 transistors. However as the sizing rule limitation in IC layout design, we considered the minimum size of MOSFET devices which is 0.9 µm width for M 5 (Pennisi, 2005). For the other NMOS transistors M 1, M 2, M 3 and M 4, the width is 6.0 µm. Table 2: Transistor width and length used in this work. Transistors Width Length M1, M2, M3, M4 6.0 µm 0.18 µm M5 0.9 µm 0.18 µm There are several characteristics related to the current mirror design. This work of WSCCM consumed a typical small bias voltage compared to other current mirror circuits (Singh et al, 2009; Blazes, 1991). A performance comparison of current mirror circuits in different works is shown in Table 3. Table 3: Characteristics table of important role in current mirror design. This work (Fiocchi and Gatti, 1999) (Singh et al, 2009) Voltage supply (Vs) 1V 5V 2V 1.8V Power dissipation (P) 0.249mW 0.691mW 7.40mW 6.48mW Resistor (ohm) 1kΩ 1kΩ N/A 200kΩ (feedback) Minimum bias voltage (Vbias) 626mV N/A

5 4100 Fig. 7: The minimum bias voltage consumed. Usually greater transistor width result in consumption of more power (Fiocchi and Gatti, 1999). Therefore, power dissipated by the WSCCM design in this design is kept small by using least amount of transistors. It also provides stable and continuous current supply. Figure 9 and figure 10 represents the minimum bias voltage consumption and output current of the circuit, respectively. Fig. 8: Output Current characteristics of the proposed current mirror. Conclusion: This article proposes a best performance design of a wide swing cascode current mirror architecture. By attaching the resistor direct into the circuit, the output current will tend to saturate very quickly compared to other concurrent designs. The design also required a minimum bias voltage as less as 0.4V to operate and thus makes it compatible for application that require higher output impedance and where the voltage supply is critical.

6 4101 References Akter, M., M.B.I. Reaz, F. Mohd-Yasin and F. Choong, Hardware implementations of an image compressor for mobile communications.journal of Communications Technology and Electronics, 53(8): Akter, M., M.B.I. Reaz, F. Mohd-Yasin and F. Choong, A modified-set partitioning in hierarchical trees algorithm for real-time image compression. Journal of Communications Technology and Electronics, 53 (6): Azhari, S.J., Hassan Faraji Baghtash and Khalil Monfaredi, A novel ultra-high compliance, high output impedance low power very accurate high performance current mirror, Microelectronics Journal, 42(2): Blazes, M., Two Novel Fully Complementary Self-Biased CMOS Differential Amplifiers. IEEE Journal of Solid State Circuits, 26(2): Fiocchi, C. and U. Gatti, A very flexible BiCMOS low-voltage high-performance source follower. In the Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS '99), pp: Gupta, R. and S. Sharma, Quasi-floating gate MOSFET based low voltage current mirror, Microelectronics Journal, 43(7): Hitesh and A. Goel, Performance Parameters of Improved Swing, Wilson & Regulated Cascode Current Mirrors, International Journal of Advanced Research in Computer Science and Software Engineering, 2(3): Kim, J.Y., J.K. Yun, Y.K Lee and J.S Lee, A highly accurate BiCMOS cascode current mirror for wide output voltage range. In the Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS 2008), pp: Marufuzzaman Mohd., M.B.I. Reaz, M.S. Rahman and M.A.Mohd. Ali, Hardware prototyping of an intelligent current dq PI controller for FOC PMSM drive. In the Proceedings of the 6th International Conference on Electrical and Computer Engineering, pp: Mohd-Yasin, F., A.L. Tan and M.I. Reaz, The FPGA prototyping of Iris recognition for biometric identification employing neural network. Proceedings of the International Conference on Microelectronics, ICM, pp: Nojdelov, R. and S. Nihtianov, Capacitive-sensor interface with high accuracy and stability. IEEE Transactions on Instrumentation and Measurement, 58(5): Pennisi, S., High-performance and simple CMOS interface circuit for differential capacitive sensors. IEEE Transactions Circuits and Systems II: Express Briefs, 52(6): Petrellis, N., George Adam and Dimitrios Ventzas, A real-time self-calibrated current mirror for wide range current reference generation, signal reproduction and delaying, Microelectronics Journal, 43(3): Reaz, M.B.I., M.T. Islam, M.S. Sulaiman, M.A.M. Ali, H. Sarwar and S. Rafique, FPGA Realization Of Multipurpose FIR Filter, Parallel and Distributed Computing, Applications and Technologies, PDCAT Proceedings, pp: Reaz, M.B.I., F. Mohd-Yasin, S.L. Tan, H.Y. Tan and M.I. Ibrahimy, Partial encryption of compressed images employing FPGA. Proceedings - IEEE International Symposium on Circuits and Systems,, art. no , pp: Reaz, M.B.I., F. Choong and F. Mohd-Yasin, VHDL modeling for classification of power quality disturbance employing wavelet transform, artificial neural network and fuzzy logic. Simulation. 82(12): Reaz, M.B.I., M.I. Ibrahimy, F. Mohd-Yasin, C.S. Wei and M. Kamada, Single core hardware module to implement encryption in TECB mode.informacije MIDEM, 37(3): Sampietro, M., G. Bertuccio and L. Fasoli, Current mirror reset for low-power BiCMOS charge amplifier, Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment, 439(2): Sarao, J., Z.J. Wang, Y.L. Wu and H.L. Kwok, An improved regulated cascode current mirror, Solid-State Electronics, 46(2): Shukla, D.S., N.M. Devashrayee and A. Naik, Design and Development of Self Biased Cascode Circuit with its Implementation using 0.35µm Technology. International Journal on Electronics and Communication Technology, 2(2): Singh, T., T. Sæther and T. Ytterdal, Current-Mode Capacitive Sensor Interface Circuit with Single- Ended to Differential Output Capability. IEEE Transaction on Instrumentation and Measurement, 58(11):

7 4102 Tseng, S.C., C. Meng and G.W. Huang, High Gain CMOS Gilbert Downconverter with Wide-Swing Cascode Current-Mirror Transconductor and Load. In the Proceedings of the IEEE Antennas and Propagation Society International Symposium- 2007, pp: Yang, B.D., Jang-Su Kim, Jin-Kuk Yun, Yong-Kyu Lee and Jee-Sue Lee, A Highly Accurate BiCMOS Cascode Current Mirror for Wide Output Voltage Range. In the Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS 2008), pp: