On Dual-Rail Control Logic for Enhanced Circuit Robustness

Size: px
Start display at page:

Download "On Dual-Rail Control Logic for Enhanced Circuit Robustness"

Transcription

1 On Dul-Ril ontrol Logic for Enhnced ircuit Roustness Andrey Mokhov, Victor Khomenko, Dnil Sokolov, Ale Ykovlev School of omputing Science, Newcstle University, UK School of Electricl, Electronic nd omputer Engineering, Newcstle University, UK Astrct Ultr low-power design nd energy hrvesting pplictions require digitl systems to operte under etremely low voltges pproching the point of lnce etween dynmic nd sttic power consumption which is ttined in the su-threshold opertion mode. Dely vritions re etremely lrge in this mode, which clls for the use of synchronous circuits tht re speed-independent or qusi-dely-insensitive. However, even these clsses of synchronous logic ecome vulnerle ecuse certin timing ssumptions commonly ccepted under norml operting conditions re no longer vlid. In prticulr, the dely of inverters, often used s the so-clled input ules, cn no longer e neglected nd they hve to e either removed or properly cknowledged to ensure speed-independence. This pper presents n utomted pproch to synthesis of roust controllers for su-threshold digitl systems sed on dul-ril implementtion of control logic which elimintes inverters completely. This nd other importnt properties re nlysed nd compred to the stndrd single-ril solutions. Dul-ril controllers re shown not to hve significnt overheds in terms of re nd power consumption nd re even fster in some cses due to the elimintion of inverters from criticl pths. The presented utomted synthesis techniques re very efficient nd cn e pplied to very lrge controllers s demonstrted in enchmrks. I. INTRODUTION Recent reserch (e.g., [7][17][1][37]) revels tht for the mjority of logic nd sttic memory locks the optiml energyper-opertion voltge lies ner or elow the threshold voltge of MOSFET device, where the point of lnce etween dynmic nd sttic power consumption is found. This mode is commonly known s su-threshold mode. A comprehensive nlysis, using the EKV model, of the su-threshold opertion of sttic logic cn e found in [36]. The decision t which Vdd level the circuit should operte to meet its optimum in terms of energy efficiency nd gurntee the cceptle level of opertionl roustness requires considering process nd environmentl vriility. Notly, dely vritions re etremely lrge in the su-threshold mode. This clls for the use of synchronous circuits tht re speed-independent (SI) or qusi-dely-insensitive (QDI) [3][5]. These clsses of synchronous logic operte on the principles of cuslity nd completion detection rther thn mtched dely nd fundmentl mode, which mkes them inherently roust to vritions in the delys of their gtes. Additionlly, the performnce of such circuits is determined y ctul, rther thn worst cse ltency. Recent studies in [6] nd [] show the high potentil of synchronous SI nd QDI circuits to uild energy-efficient circuits. Moreover, for power hrvesting pplictions, where Vdd cn e unstle nd vrying, this is even more the cse (cf. [4] nd [9]). The design of SI nd QDI circuits for deep-sumicron cn e performed using eisting AD support, provided y tools such s Hste nd Bls [30] or desynchroniztion methods [35], which use the principle of single-ril logic nd undled-dely for the dt-pth, ut use hndshke QDI circuits for control. ontrol logic usully determines the roustness of the overll system to vritions nd trnsient errors ecuse it forms its opertionl kernel. While errors in the dt-pth cn e tolerted using conventionl (e.g. error-correction codes) pproches, ny error in control logic (e.g. unspecified trnsition or spurious pulse on request or cknowledgement line) cn e ftl for the entire system. It hs een demonstrted tht power reduction through voltge scling increses the soft error rte (SER) eponentilly [8]. It is therefore importnt to support design of roust synchronous controllers for suthreshold mode with tools for their efficient synthesis from ehviourl specifictions. A. ontrol circuit synthesis techniques There re two sufficiently mture control synthesis methodologies: one is sed on Petri nets [11] nd produces SI/QDI controllers, while the other is sed on urst-mode finite stte mchines [7] nd produces controllers working under the fundmentl mode of interction with environment. Since the pper focuses on roust controllers working under etremely lrge vritions we follow the Petri net synthesis flow to hve s few ssumptions on environment s possile. The flow ccepts event-sed specifictions in terms of interpreted Petri nets, clled Signl Trnsition Grphs (STGs), nd converts them into logic equtions for comple gtes in the implementtion circuit. By construction, this circuit is n SI circuit with respect to the delys ssocited with the outputs of the comple gtes. Designers usully prefer using comple gtes, which cn e implemented s the so-clled generlised (or symmetric) -elements [30]. This wy mny control circuits pulished to dte, such s controllers for pipeline stges [30], No routers [13], s well s controllers for ltches for suthreshold logic [1], hve een constructed. However, in the su-threshold mode, even these SI/QDI implementtions my ecome vulnerle to the effects of vriility or susceptiility to noise (cross-tlk) nd trnsient fults. For emple, the

2 ecessive dely vritions under low Vdd mke certin timing ssumptions tht re commonly ccepted under norml Vdd no longer vlid. In prticulr, most of the comple gtes in the implementtions produced y SI/QDI synthesis contin the so-clled ules. These re input inverters, whose dely is typiclly neglected, or t lest regrded to e much smller thn the dely of certin ( rcing ) pth pssing through other logic gtes. In su-threshold opertion these ules cn no longer e ignored. Strodoutsev hs developed method of ehviourl refinement for the synthesis of the SI/QDI clss of circuits from STGs [31], which produces circuits in simple monotonic gtes (free from ules). Unfortuntely, this technique tckles oth prolems, otining monotonic functions of the gtes nd decomposition of gtes into simple gtes, t the sme time, which mkes it quite comple in prctice (see lso discussion of normlcy in Section III). As result it hs not een utomted to dte nd leds to circuits with long cknowledgement pths, therey incresing their ltency. To fcilitte the vilility of tools for designing efficient nd roust su-threshold circuits it would e eneficil to mimlly use the eisting logic synthesis frmeworks, such s tht of PETRIFY, to generte monotonic SI/QDI circuits. It would e desirle to otin reltively simple synthesis flow, similr in its spirit to the one used in NL-D/NL-X [16][0] for dt-pth logic. Fortuntely, the wy to such n pproch origintes in the ide of perfect implementtion for semimodulr circuit from [14]. The theory for this pproch is sed on deriving seprte Boolen covers for the set nd reset functions for ech signl in the circuit specifiction. Those cn e otined from the ecittion nd quiescent regions [11] for. This is equivlent to finding net stte functions for two seprte rils nd of ech inry signl. The originl theory of [14] ws developed for the so-clled closed circuits, without input choice, nd hence is not directly pplicle to the types of controllers designed in prctice tody. Lter this pproch ws etended to work for open circuits in the technique for monotonic cover implementtion [19], however the focus of tht work ws not specificlly on finding dul-ril control implementtions; esides it ws not fully utomted to work with specifictions of comple controllers. B. ontriution nd orgnistion of the pper In this pper, we ddress the prolem of roust control logic synthesis with specific requirement of finding n SI/QDI implementtion which will meet the needs of su-threshold mode of opertion nd will e otined utomticlly from specifiction which my e s comple s hundreds of logic signls. We pursue the pproch of dul-ril synthesis, using the theoreticl sis of [14] s well s monotonic cover techniques of [19] to support the decomposition of comple dul-ril gtes into seprte logic for set nd reset functions nd stndrd RS ltches. This comintion offers rnge of dul-ril rchitectures, clled here grs nd stdrs, which cn e implemented using sttic logic lirries s well s custom trnsistor-level circuits. We implement the synthesis lgorithms using efficient methods of coping with huge stte spces tht re sed on Petri net unfoldings (PUNF/MPSAT tool chin [18]). One of the importnt enefits of these dulril implementtions of comple controllers is tht the control logic cn e distriuted, i.e. the pproprite gtes producing control signls cn e plced net to the dt-pth sections. This distriution my led to the need to use long wires, ut this risk of violting dely-insensitivity due to wire delys will e mitigted y the inherent roustness of dul-ril implementtions. Specil dul-ril repeters will e used where necessry, ginst trnsient fults nd violtions of signl integrity. Besides monotonicity (no ules), other enefits of these implementtions compred to single-ril control include: less gte compleity, fewer isochronic forks; esier testility (RS-ltches insted of -elements). The pper illustrtes these dvntges in reltively simple cse study nd set of enchmrks whose compleity scles up to lrge quntities of control gtes. Our min contriutions in this pper cn e summrised s follows. An in-depth study of dul-ril control methodology is crried out: gte- nd trnsistor-level implementtions of stndrd dul-ril control structures re presented; the implementtions re nlysed in terms of roustness, re nd ltency; we demonstrte vulnerility of single-ril controllers due to input inverters; numer of single-ril nd dul-ril controllers re compred in terms of re, power consumption, s well s required post-synthesis effort in logic decomposition nd isochronic fork lncing. A sclle synthesis method for dul-ril control, which is sed on Petri net unfoldings, is presented nd evluted. The pper is orgnised s follows. Section II presents the min foundtion ehind dul-ril control logic, including its motivtion, dvntges nd possile penlties. Section III descries the sic synthesis process. Section IV presents detiled cse study nd Section V covers the eperiments on set of stndrd synchronous controllers. II. DUAL-RAIL ONTROL Dul-ril code uses pir of physicl wires, nd ˆ, per logicl signl. There re two vlid signl comintions, 01 nd 10, which encode vlues 0 nd 1, respectively. This code is employed to represent dt in self-timed circuits [1], where specific protocol of switching helps to void hzrds. The protocol llows only the monotonic switching from ll-zeroes 00, which is non-code word, to code word nd ck to ll-zeroes s shown in Figure 1. The ll-zeroes stte, which is clled spcer, indictes the sence of dt nd seprtes one code word from nother. Trditionlly the dul-ril switching protocol is used in synchronous dt-pth logic due to its roustness nd simplicity of circuit construction, s in [0] where the stndrd

3 code word "0" spcer Figure 1: Dul-ril signlling protocol code word "1" ˆ code word <01> spcer <00> code word <10> ˆ () NL-D ˆ ˆ inversion () NL-X Figure : Dul-ril dt-pth on AND-gte emple RTL-sed design flow is etended y converting singleril circuits into dul-ril. Within this pproch, clled Null- onvention Logic [15] one cn follow either of two min implementtion styles: NL-D, which integrtes completion detection into the dul-ril logic or NL-X, which relies on seprte completion detection circuitry nd/or on some timing ssumptions. The former is more conservtive with respect to dely sensitivity while the ltter is more re nd speed efficient. For emple, n AND gte implemented in NL-D nd NL-X styles is shown in Figure. The inherent property of the dul-ril circuits is tht the opertion of Boolen negtion corresponds to the ril swpping, which llows to chieve rce-free opertion under ny single trnsition. Another feture of the dul-ril logic is its lnced power consumption which fcilittes circuit resistnce to the power nlysis ttcks. Security spects of the dul-ril circuits hve een further improved y introducing specil lternting spcer protocol [9] it gurnties ll gtes of the circuit switch ectly once in ech computtion cycle, thus mking circuit power consumption invrint to the processed dt. A. ost of dul-ril control The mjor drwck of the dul-ril dt-pth logic is (t lest) twofold increse in re nd power consumption compred to the single-ril implementtion. Since dt-pth circuits constitute dominnt prt of the whole system, this restricts the doption of dul-ril methodology to the firly specific domin of security pplictions nd to uilding truly self-timed systems. However, re nd power penlties should not impose significnt overhed on the reltively smll control circuits eing implemented in dul-ril style. A fr more importnt issue for control is ltency: switching through the ll-zeroes stte in dul-ril dt-pth doules the computtion cycle unless etr logic is inserted to concurrently prechrge the comintionl logic to spcer [34], see illustrtion in Figure 3(). By contrst, dul-ril control does not require cknowledgement of the spcer stte, so the ltter cn e trnsient s shown in Figure 3(), therey chieving ltency of single-ril implementtion. ˆ ˆ long enough to propgte through ll levels of comintionl logic () Dt-pth: cknowledged spcer spcer <00> code word <01> code word <10> very short (trnsient) () ontrol: trnsient spcer Figure 3: Spcer stte: dul-ril dt-pth vs dul-ril control The synchronous control is usully dominted y - elements which perform generic function of signl synchronistion ( -element output goes high when ll its inputs re high, nd goes low when ll the inputs re low). While enjoying ll the enefits of dul-ril switching protocol, dul-ril -element cn ctully e mde comprle in size, power consumption nd ltency to the single-ril one. For emple, typicl single-ril comple-gte -element shown in Figure 4() (s synthesised y MPSAT or PETRIFY tools) requires 1 trnsistors in sttic MOS implementtion. An equivlent dul-ril circuit in Figure 4() hs the sme trnsistor count nd is uilt out of simpler gtes, which re more likely to e present in the technology lirry. Avilility of the comple gtes is prticulrly importnt to void hzrdfree decomposition of the -element set/reset functions [19], which is not trivil nd often results in significnt re, power nd ltency penlties. () Single-ril ˆ () Dul-ril negtion Figure 4: omple gte implementtion of -element For custom design the dul-ril -element is lso similr in size to the stndrd trnsistor-level single-ril implementtion (8 trnsistors), s illustrted in Figure 5. The stte of the -element is held in keeper logic level holding circuit which consists of two inverters connected ck to ck. Note tht for single-ril implementtion the feedck inverter hs to e wek (mde out of smll trnsistors), so tht the pull-up nd pull-down trnsistor stcks re le to enforce the keeper stte. When = 1 nd the keeper stte is supported ˆ

4 negtion ˆ ˆ keeper () Gte-level () Trnsistor-level () Single-ril ˆ S R Q ˆQ ˆ δ 1 δ 1 3 S Q S Q R ˆQ R ˆQ ˆ () Dul-ril Figure 5: ustom implementtion of -element y wek PMOS trnsistor only nd therefore is vulnerle to single event upset (SEU), such s voltge pulse cused y chrge-induced prticles or electromgnetic rdition. The corresponding dul-ril solution is sed on cross-coupled inverters nd pull-down NMOS networks for oth set nd reset. Under the sme conditions this implementtion is more roust to SEUs ecuse its stte holding element is symmetric nd oth inverters re strong, hence the criticl chrge from the prticle strike is required to e higher to pull down the middle point sufficiently low [33]. Note tht dul-ril -element is most eposed to SEUs when neither set nor reset function is evluted to 1 nd its stte cn e toggled y prticle strike. Therefore, to improve circuit roustness one cn eplore trdeoff etween the compleity of the set/reset functions nd minimistion of the dngerous time intervl when oth functions evlute to 0. The ove -element implementtions comine the set/reset functions nd the stte holding ltch. Often it my e necessry to seprte the set nd/or reset logic from the ltch, e.g. to reduce the implementtion compleity or to mp the ltch into stndrd lirry RS-ltch. Such decomposition must preserve the hzrd-free opertion nd is chieved y uilding the set/reset functions stisfying the condition of monotonic cover, s descried in Section III. The use of stndrd RSltches is dvntgeous for comptiility with the stndrd design prctice s it helps to void comintionl loops which often cuse prolems for EDA tools. ircuit testility cn lso e ddressed y etending the RS-ltches with synchronous scn interfce nd pplying stndrd testing techniques for level-sensitive scn design (LSSD) [8]. With this scn structure the circuit opertes synchronously in mission mode, while it is synchronised with the test clock signls when in test mode. (c) RS-ltch B. Roust dul-ril repeters > 1 +δ 1 + +δ + 3 Figure 6: Dul-ril repeters (d) Repeter insertion A -element with trivil set/reset functions, s shown in Figure 6, is clled repeter nd is employed to mintin signl integrity in long wires. Similrly to single-ril uffers, the dul-ril repeters cn e used to reduce the time dely ssocited with long wires y inserting them long the switching lines. This technique, known s repeter insertion, is well studied [3][6] nd cn e directly pplied for dul-ril control logic s shown in Figure 6(d). Dul-ril repeters re very roust to SEUs ecuse their inputs go through the dngerous spcer stte only for short period of time nd switch ck into stle code word stte immeditely see Figure 3(). If single wire distortion occurs while in code word stte the repeter recovers from the error the informtion redundncy of dulril code words plys its role; spcer stte, on the other hnd, does not provide sufficient informtion for recovery. This is demonstrted y simultion 1 of two SEUs s0 nd s1 on output wires ˆ nd, respectively, which is shown in Figure 7(). SEUs were modelled s 5ps pulses nd the full recovery took round 100ps. In the unlikely event of SEU occurring during the spcer stte, the repeter still recovers from s1 ut cnnot recover from s0 s illustrted in Figure 7(). The notorious penlties of dul-ril dt-pth, power consumption nd cycle time, re irrelevnt to the dul-ril control logic. In dul-ril control the switching ctivity doules s ll the wire pirs go through spcer stte (similr to the dul-ril dt-pth). However, the lod of the wires is roughly hlved compred to the corresponding single-ril circuit nd therefore the power consumption increse is insignificnt (not twofold s in dt-pth logic). Also the spcer stte is trnsient in dul- 1 All simultions in this pper hve een performed in SPETRE using Frdy stndrd gte lirry sed on UM 90nm technology.

5 c+ + + d c 0010 c d+ order of signls in encodins:,, c, d inputs:, outputs: c, d Figure 8: A circuit specifiction from [5] () In code word stte () In spcer stte Figure 7: Recovery of dul-ril repeter from SEUs ril control nd does not require dedicted prechrge stge s in NL, therefore the cycle time remins the sme s in single-ril control. To summrise, the penlties ssocited with the dul-ril dt-pth circuits do not show in the control logic. In prticulr, the key uilding lock of synchronous control, the dul-ril -element, is similr in size nd speed to the stndrd single-ril implementtion, while its opertion t su-threshold voltge is more roust to noise nd chrge-induced prticles. A synthesis method nd hzrd-free decomposition of set/reset functions is presented in Section III nd circuit compleity, size nd power consumption is nlysed on set of lrge enchmrks in Section V. III. SYNTHESIS We wnt to uild speed-independent (SI) circuits, ssuming tht their ehviour is specified using stte grphs (SGs), which re finite stte mchines with nnottions, cf. Figure 8 (SGs cn e constructed from higher-level specifictions, such s STGs [11] or HDLs). We further ssume tht ll the sttes in the SG re rechle from the initil stte. With ech stte s of the SG we ssocite vector of inries ode(s) representing the vlues of ll the circuit signls t this stte; moreover, ode z (s) will denote the component of ode(s) corresponding to signl z. Ech rc of the SG is lelled y z + orz, wherez is signl. We ssume tht the specifiction is consistent, i.e. if n rc (s, s ) is lelled y z + (resp. z ) then ode z (s) = 0 (resp. 1), ode z (s ) = 1 (resp. 0), nd ode z (s) = ode z (s ) for ll z z. Furthermore, we ssume tht the SG is deterministic, i.e. no two rcs with the sme source re lelled y the sme signl. The circuit signls re prtitioned into inputs nd outputs (the ltter lso include internl signls). Input signls re ssumed to e generted y the environment, while output signls re produced y the circuit. We ssume tht the SG is output-persistent, i.e. n output cnnot e disled y firing ny other trnsition (i.e. choices re llowed only etween inputs). For ech output signl z, the Boolen functions Out z +, Out z ndout z re defined s follows:out z + /z /z(s) is 1 if sttesenlesz + /z /z ±, nd 0 otherwise. The Boolen netstte function Nt z is then defined s Nt z (s) = df ode z (s) Out z (s), where is the eclusive or opertion. Similrly, the set nd reset functions Set z nd Reset z re defined s follows: 1 if Out z + /z (s) = 1 Set z /Reset z (s) = df 0 if Nt z (s) = 0/1 otherwise, where denotes the don t cre vlue (i.e. the vlue of the function cn e chosen ritrrily, with the view of simplifying the resulting implementtion). Vrious rchitectures re used to implement speed-independent circuits; the following re proly the most wellknown [11][19] (see Figure 9): omple-gte (G) implementtion: Every output is implemented s single (possily very complicted) tomic gte [10]. Generlised- (g) implementtion: Every output is implemented using pseudo-sttic ltch clled generlised element (g element) which is ssumed to e tomic [3]. A In some pplictions choice etween outputs is llowed, which cn e implemented y specil element clled riter tht internlly uses some nlog circuitry to hndle the rising metstility; however, riters cn e fctored out into the environment, so tht the remining prt of the specifiction is output-persistent.

6 d c () omple-gte c _ d c (c) orrect std implementtion (e) grs implementtion d () g implementtion _ d _ c (d) Nïve std implementtion (f) stdrs implementtion Figure 9: Implementtions of signl c of the SG in Figure 8 g implementtion is specified y the set nd reset functions for ech output, which re implemented y pull-up nd pulldown trnsistor networks. In the sttes where oth set nd reset functions evlute to 0, keeper element is used to ensure tht the output keeps its current vlue (it is n error if in some rechle stte oth functions evlute to 1 this cn led to short circuit). This is similr to the implementtion of single-ril -element from Figure 5(). Stndrd- (std) implementtion: Every output is implemented using -ltch controlled y set nd reset signls, which we ssume re implemented s comple-gtes [5]. This rchitecture is superficilly similr to the previous one, ut one should er in mind tht g element is ssumed to e tomic, while in the std implementtion the gtes controlling -ltch hve delys. Hence nïve trnsformtion of g implementtion into n std one cn result in hzrdous circuit (see elow). Generlised-RS (grs) nd stndrd-rs (stdrs) implementtions: These two rchitectures correspond to g nd std ones, in prticulr the sme set nd reset functions re used, ut n RS-ltch is used s the stte holding element [19]. Furthermore, the dul-ril representtion of ech signl is used, nd so there re no inverters nywhere in the circuit (ecept those hidden inside the ltch). For the circuit to e implementle in the G rchitecture, the vlue of Nt z must e uniquely determined y the encoding of ech rechle stte, i.e. it should e function of ode(s) rther thn s: Nt z (s) = F z (ode(s)) for some Boolen function F z, which is eventully implemented s comple-gte. Similrly, for g rchitecture the vlues of Set z nd Reset z must e functions of ode(s) rther thn s: Set z /Reset z (s) = S z /R z (ode(s)) for some Boolen functions S z nd R z, which will determine the corresponding g element. In cse of std rchitecture, S z nd R z must in ddition stisfy the Monotonic over condition (M) [5][11], in order to provide hzrd-free circuit. M sttes tht cover must e entered only vi the sttes enling the output z. As M reduces the fleiility in choosing S z nd R z, they cn e more complicted thn those for g rchitecture, cf. Figure 9(,c). To illustrte the importnce of M, consider the implementtion shown in Figure 9(d), which does not stisfy it, since the stte 0110 (which is covered y the set function d nd does not enle c) cn e reched from the stte 1110 (which is not covered y this set function nd does not enle c). onsider the sequence of sttes 1111 d The gte computing the set function is high t Firing of d drives its output low, ut efore it reches 0, cn fire, driving its output high; similrly, efore it reches 1, cn fire, driving it low. Hence, this gte cn ehiit runt non-digitl pulses cusing the circuit to mlfunction. It turns out tht the notion of implementility of signl is invrint cross the G/g/std/gRS/stdRS rchitectures, 3 i.e. if signl is implementle in one of them, it is implementle in the other rchitectures s well; moreover, given the mentioned ove ssumptions on the SG, the implementility of the specifiction in either rchitecture is equivlent to the omplete Stte oding (S) property, which sttes tht for every circuit output z, no two sttes s nd s of the SG stisfy ode(s) = ode(s ) nd Out z (s) Out z (s ) [11]. In wht follows, we ssume tht the SG stisfies the S property. Normlcy [3] is property of SGs, which is necessry condition for their implementility in the G rchitecture using gtes without input inversions, i.e. whose chrcteristic function is either monotonic or negtion of monotonic function. Normlcy violtions cn e detected y model checking, nd sometimes resolved y insertion of new signls []. However, the ltter is not lwys possile, s the sought signl insertions might not eist or cuse further normlcy violtions, nd even if this is possile, the circuit ecomes more complicted due to the dditionl logic needed to implement the new signls. There re numer of tools tht support synchronous synthesis, e.g. PETRIFY nd MPSAT. They oth support complegte synthesis nd derivtion of set nd reset functions, including monotonic covers, nd so cn e used to utomte ny of the descried synchronous rchitectures. The min prolem in synthesis is the stte spce eplosion: reltively smll specifiction cn (nd often does) yield huge stte grph; 3 The result is well-known for the former three rchitectures, nd grs nd stdrs implementtions use the sme set nd reset functions s g nd std, respectively.

7 () Initil STG () S conflicts resolved Figure 10: STG specifiction of the emple controller Ai Ri csc0 S R Q csc1 S R Q^ Q 3 Q^ Ao S Q R Q Ro S R Figure 13: stdrs implementtion Q Q^ Ao Ro this puts prcticl limit on the size of circuits tht cn e synthesised. To llevite this prolem, PETRIFY uses BDDs, nd usully cn synthesise circuits with up to 0-30 signls. MPSAT voids generting the stte grph ltogether, nd works on STG unfoldings insted; it usully cn synthesise circuits with up to signls. IV. ASE STUDY Figure 10() shows n STG specifiction of typicl synchronous pipeline controller from [11] which synchronises two hndshkes (Ri, Ao) nd (Ro, Ai) mnging djcent pipeline stges. Request Ri + informs the controller out vilility of dt in the current pipeline stge. In response, the controller immeditely prompts the net stge to ltch the dt (Ro + ) nd sends n cknowledgement ck to the current stge (Ao + ). Then the hndshkes re reset concurrently (Ri Ao nd Ai + Ro Ai ) for the net dt trnsfer round. In order to stisfy the S property it is necessry to introduce two internl signls csc0 nd csc1 s shown in Figure 10(); this is done utomticlly see detils in [11]. Ri Ai i4 i5 i csc1 csc0 4 4 i1 i3 Ao Ro Figure 11: omple-gtes implementtion Now it is possile to use PETRIFY or MPSAT synthesis tool to generte G implementtion of the STG. The otined circuit is presented in Figure 11; note tht input ules of the derived comple-gtes re eplicitly shown s inverters i1 i5. In norml operting mode it is commonly ssumed tht these inverters re fster thn ny other gte. However, if the controller opertes under su-threshold voltge the 3 4 Ao Ro incresed dely vritions cn esily violte this ssumption, thus reking the speed-independence of the circuit. onsider the following sequence of events: Ri +, Ro +, Ao +, i, i3, csc0 i4 +, Ai +, i5, csc1, i1 +, Ro, i + Ri, Ao, i3 +, Ai, i5 +, csc1 + At this point there is rce etween events i1 nd csc0 + : if inverter i1 hppens to e slower thn gte csc0, there will e n unspecified enling of Ao + which cretes hzrd on wire Ao nd reks the environment protocol. At the system level this cn esily led to glol dedlock. Figure 1 shows simultion of the circuit ehviour under different supply voltges. At nominl 1V power supply we get no sign of the hzrd. This hzrd-free ehviour continues ll the wy down to 600mV. The hzrd ecomes visile t 575mV nd reches incorrect voltge levels for output Ao t out 550mV. This is perfect illustrtion of how quickly things cn go wrong in the su-threshold domin. The prolem cn e solved y pplying the dul-ril epnsion to ll signls, thus removing ll the dngerous inverters. The stdrs implementtion of the controller is shown in Figure 13; s epected, it contins no inverters. Another importnt dvntge is tht it is uilt of much simpler gtes which re very likely to e present in most technology lirries. Lrge 4- nd 5-input gtes of the G implementtion will proly require decomposition into smller gtes, potentilly introducing new sources of hzrds nd dding more overheds. A. Anlysis of wire forks Note tht lthough the numer of wires in the dul-ril implementtion hs douled, ech wire hs less lod s it hs ecome distriuted over two rils. For emple, signl csc0 in the single-ril implementtion hs 4 gtes in its fnout (this fct is denoted s 4 in Figure 11), while oth signls csc0 nd csc0 in the dul-ril controller hve fnout, thus jointly consuming the sme mount of energy ut switching fster. This lso decreses the degree of forking : insted of hving to lnce 4 wire delys to stisfy the isochronic fork ssumption during circuit lyout, one hs to lnce only two pirs of wires, which is considerly esier.

8 () Supply voltge = 600mV () Supply voltge = 575mV (c) Supply voltge = 550mV Figure 1: Simultion of hzrd in single-ril implementtion Overll, in the G implementtion there re wire forks of the following degrees:, 3, 4, 4, 4. The fork degrees of the stdrs implementtion re,,,,,,, 3. In order to compre the controllers in terms of the effort required for fork lncing we introduce the following mesure. onsider fork with k rnches. There re ( ) k = k(k 1) pirs of wires nd ech pir, if unlnced, cn led to hzrd in the controller. Therefore, the overll fork lncing effort will e proportionl to f() = ( kw ) w, where is given controller nd w itertes over ll its wires. For the emple t hnd the comprison mesure gives the following result: ( ) ( ) ( ) 3 4 f(g) = + +3 = ( ) ( ) 3 f(stdrs) = 7 + = 10 Hence, one cn conclude tht the single-ril version of the controller requires roughly twice s much effort for fork lncing s the dul-ril one. In the net section we will demonstrte tht this is typicl sitution. V. EXPERIMENTS Tle I presents summry of eperimentl results. We hve tken severl stndrd synchronous controllers, some of which re sclle, nd synthesised their implementtions using PUNF nd MPSAT synthesis tools. Despite the lrge stte spces (up to sttes) the processing times were in the order of severl seconds. Ech enchmrk controller is descried with three prmeters: I, O nd S eing counts of the circuit inputs, outputs nd sttes, respectively. olumns Inv. report numers of input inverters in G nd std single-ril implementtions; dulril stdrs nd grs implementtions re ule-free. Are of prticulr implementtion is estimted s its size in terms of literls ( gte ule is lso counted s literl ecuse it hs to e implemented seprtely from the gte, hence occupying dditionl re). Power consumption is estimted similrly, with the eception tht ule is given smller weight of 0.5, ecuse n input inverter drives only single wire nd thus consumes less power thn n verge circuit gte. Power nd re estimtes re normlised over the G implementtion for esier comprison; verge vlues cross ll enchmrks re given in the ottom row. L m represents compleity of the lrgest gte in n implementtion in terms of literls (note tht L m for std nd stdrs implementtions re the sme). Lrger vlues of L m correspond to circuits which re more difficult for technology mpping. Roughly speking ny gte contining more thn 6 literls is very unlikely to e present in technology lirry; some lirries re even limited to 3-literl gtes only. One cn see tht dul-ril implementtions tend to hve simpler gtes, therefore eing esier for decomposition. Another relevnt prmeter L vg (verge gte compleity) is not shown in the tle due to lck of spce, ut we oserved tht in generl L vg is twice lrger for single-ril implementtions. Figure 14 shows comprison of G, grs nd stdrs implementtions in terms of the fork lncing effort. One cn see tht single-ril controllers re consistently more epensive in this respect: on verge, the effort of lncing forks in grs (resp. stdrs) implementtion is only 50% (resp. 54%) of tht of the G implementtion. This lso mens tht the verge lod on single-ril wire is the doule of tht on dul-ril wire. Intuitively, this is ecuse single-ril wire is used y oth positive nd negtive vlue consumers. Overll we cn conclude tht dul-ril grs implementtion hs no penlty in terms of power nd only 15% overhed in terms of re in comprison to G single-ril implementtion. Dul-ril is more roust though s there re no potentilly dngerous inverters nd wires hve less lod nd forks. Moreover

9 Benchmrk Single-ril implementtions Dul-ril implementtions circuit G std stdrs grs Nme I / O S Inv. L m Power Are Inv. L m Power Are Power Are L m Power Are LzyRing 5/ % 34.8% 165.8% 190.9% % 139.4% Ring 11/ % 170.% 118.4% 138.1% % 108.3% Dup4phsc 1/ % 175.5% 13.6% 143.8% % 115.0% Dup4phMtrsc 10/ % 190.0% 13.7% 155.9% % 13.8% DupMtrModsc 10/ % 17.0% 114.5% 138.8% 1 89.% 108.1% fasymsca 8/ % 196.1% 13.0% 154.7% % 13.3% fasymscb 8/ % 185.0% 1.9% 145.7% % 117.9% fsymsca 8/ % 161.5% 110.5% 19.6% % 107.3% fsymscb 8/ % 193.9% 135.7% 155.1% % 118.4% fsymsc 8/ % 167.4% 110.5% 13.6% 7 91.% 109.5% fsymscd 4/ % 313.3% 3.5% 53.3% % 180.0% PpWksc(,3) 0/ % 03.1% 140.5% 16.5% 10.7% 118.8% PpWksc(,6) 0/ % 183.8% 16.6% 147.1% 93.7% 108.8% PpWksc(,9) 0/19 > % 177.9% 1.3% 14.3% 90.9% 105.8% PpWksc(,1) 0/5 > % 176.3% 11.7% 141.0% 90.7% 105.0% PpWksc(3,3) 0/ % 00.0% 138.% 160.0% % 117.9% PpWksc(3,6) 0/19 > % 18.3% 15.4% 145.8% 3 93.% 108.4% PpWksc(3,9) 0/8 > % 176.8% 11.5% 141.5% % 105.5% PpWksc(3,1) 0/37 > % 175.5% 11.% 140.4% % 104.8% PpArsc(,3) / % 194.4% 134.1% 154.9% % 115.5% PpArsc(,6) /19 > % 185.0% 17.4% 147.7% 6 95.% 110.3% PpArsc(,9) /5 > % 181.7% 15.6% 145.1% % 108.5% PpArsc(,1) /31 > % 178.7% 13.3% 14.7% 6 9.% 106.7% PpArsc(3,3) 3/ % 189.8% 131.0% 150.% 9 99.% 113.8% PpArsc(3,6) 3/8 > % 18.3% 15.5% 144.7% % 109.3% PpArsc(3,9) 3/37 > % 179.7% 14.% 14.9% % 107.8% PpArsc(3,1) 3/46 > % 177.1% 1.% 141.0% 9 9.1% 106.% Averge 100% 100% 180.7% 189.0% 130.4% 151.4% 99.0% 115.0% Tle I: Summry of eperimentl results dul-ril controllers contin simpler gtes nd re esier for hzrd-free technology mpping. stdrs implementtion gives even simpler gtes (s they re seprted from RS-ltches), ut hs lrger overheds: 30% nd 51% in terms of power consumption nd re, respectively. orresponding single-ril controllers (std) hve the lrgest overheds (81% nd 89%, respectively). VI. ONLUSIONS This pper presented n utomted pproch to synthesis of roust controllers for su-threshold digitl systems. The pproch is sed on dul-ril implementtion of control logic which elimintes inverters, reduces forks nd wire lod without introducing significnt overheds in terms of re, ltency nd power consumption. Future work includes optimistion of set/reset functions for roustness (to minimise the period in which oth functions re zero), nd further in-depth nlysis of testility of RS-ltch sed design. Acknowledgement This work ws supported y EPSR grnts EP/G037809/1 (VERDAD), EP/J008133/1 (TrAmS-) nd EP/I038306/1 (GAELS). REFERENES [1] O.. Akgun, J. Rodrigues, nd J. Sprsoe nd. Minimum-energy suthreshold self-timed circuits: Design methodology nd cse study. In Symposium on Asynchronous ircuits nd Systems (ASYN), 010. [] Omer n Akgun nd Yusuf Leleici. Energy Efficiency omprison of Asynchronous nd Synchronous ircuits Operting in the Su-Threshold Regime. Journl of Low Power Electronics, 3:30 336, 008. [3] H. Bkoglu nd Jmes Meindl. Optiml interconnection circuits for VLSI. IEEE Trnsctions on Electron Devices, 3(5): , [4] A. Bz, D. Shng, F. Xi, nd A. Ykovlev. Self-Timed SRAM for energy hrvesting pplictions. In PATMOS, 010. [5] P.A. Beerel,.J. Myers, nd T.H.-Y. Meng. overing onditions nd Algorithms for the Synthesis of Speed-Independent ircuits. IEEE Trns. on AD, [6] Peter A. Beerel nd Mrly Roncken. Low power nd energy efficient synchronous design. J. Low Power Electronics, 3(3):34 53, 007. [7] Dvid Bol, Din Kmel, Denis Flndre, nd Jen-Didier Legt. Nnometer MOSFET effects on the minimum-energy point of 45nm suthreshold logic. In ISLPED 09: Proceedings of the 14th AM/IEEE interntionl symposium on Low power electronics nd design, pges 3 8, 009. [8] Viks hndr nd Roert. Aitken. Impct of voltge scling on nnoscle SRAM reliility. In DATE 09: Proceedings of the conference on Design, utomtion nd test in Europe, pges , 009. [9] J.F. hristmnn, E. Beigne nd,. ondemine, N. Lelond, P. Vivet, G. Wltisperger, nd J. Willemin. Bringing roustness nd power efficiency to utonomous energy hrvesting microsystems. In Symposium on Asynchronous ircuits nd Systems (ASYN), 010. [10] T.-A. hu. Synthesis of Self-Timed VLSI ircuits from Grph-Theoretic Specifictions. PhD thesis, L. for omp. Sci., MIT, [11] J. ortdell, M. Kishinevsky, A. Kondrtyev, L. Lvgno, nd A. Ykovlev. Logic synthesis of synchronous controllers nd interfces. Advnced Microelectronics. Springer-Verlg, 00. [1] I. Dvid, R. Ginosr, nd M. Yoeli. An efficient implementtion of oolen functions s self-timed circuits. IEEE Trnsctions on omputers, 41: 11, 199. [13] Rostislv (Reuven) Dokin, Rn Ginosr, nd Avinom Kolodny. QNo synchronous router. Integr. VLSI J., 4(): , 009. [14] Victor I. Vrshvsky (Editor). Self-Timed ontrol of oncurrent Processes. Kluwer Acdemic Pulishers, [15] K. Fnt nd S.A. Brndt. Null conventionl logic: A complete nd

10 G grs stdrs Figure 14: Anlysis of fork lncing effort consistent logic for synchronous digitl circuit synthesis. In Proc. Int l onf. Appliction-Specific Systems, Architectures, nd Processors, [16]. Jeong nd S.M. Nowick. Technology mpping nd cell merger for synchronous threshold networks. IEEE Trns. on AD, 008. [17] Sen Keller, Siddrth Bhrgv, hris Moore, nd Alin J. Mrtin. Relile Minimum Energy MOS ircuit Design. In Vri 11: nd Europen Workshop on MOS Vriility, 011. [18] Victor Khomenko, Mciej Koutny, nd Alendre Ykovlev. Logic Synthesis for Asynchronous ircuits Bsed on STG Unfoldings nd Incrementl SAT. Fundment Informtice, 70(1-):49 73, 006. [19] A. Kondrtyev, M. Kishinevsky, nd A. Ykovlev. Hzrd-free implementtion of speed-independent circuits. IEEE Trnsctions on AD of Integrted ircuits nd Systems, 17(9): , sep [0] Ale Kondrtyev nd Kelvin Lwin. Design of synchronous circuits using synchronous AD tools. IEEE Trnsctions on omputers, 00. [1] J.P. Kulkrni, K. Kim, nd K. Roy. A 160 mv Roust Schmitt Trigger Bsed Suthreshold SRAM. IEEE Journl of Solid-Stte ircuits, 4(10): , 007. [] Agnes Mdlinski. Interctive Synthesis of Asynchronous Systems sed on Prtil Order Semntics. PhD thesis, Newcstle University, 006. [3] A.J. Mrtin. Progrmming in VLSI: From ommunicting Processes to Dely-Insensitive ircuits. In Developments in oncurrency nd ommuniction, UT Yer of Prog. Series, pges 1 64, [4] A. Mokhov, V. Khomenko, D. Sokolov, nd A. Ykovlev. On Dul- Ril ontrol Logic for Enhnced ircuit Roustness. Technicl Report NL-EEE-MSD-TR , Newcstle University, 010. [5] D. Muller nd W. Brtky. A Theory of Asynchronous ircuits. In Proc. Int. Symp. of the Theory of Switching, pges 04 43, [6] Ankireddy Nlmlpu nd Wyne Burleson. Repeter insertion in deep su-micron cmos: Rmp-sed nlyticl model nd plcement sensitivity nlysis. In In IEEE Interntionl Symposium on ircuits nd Systems, pges , 000. [7] Steven Nowick. Automtic Synthesis of Burst-Mode Asynchronous ontrollers. PhD thesis, Stnford University, [8] M.-D. Shieh,.-L. Wey, nd P.D. Fisher. A scn design for synchronous sequentil logic circuits using SR-ltches. In Symposium on ircuits nd Systems, volume, pges , [9] Dnil Sokolov, Julin Murphy, Alender Bystrov, nd Ale Ykovlev. Design nd nlysis of dul-ril circuits for security pplictions. IEEE Trnsctions on omputers, 54: , 005. [30] Jens Sprsoe nd Steve Furer. Principles of Asynchronous ircuit Design: A Systems Perspective. Kluwer Acdemic Pulishers, 001. [31] N. Strodoutsev nd S. Bystrov. Behvior nd synthesis of two-inputgte synchronous circuits. In Symposium on Asynchronous ircuits nd Systems (ASYN 005), pges , 005. [3] N. Strodoutsev, S. Bystrov, M. Gonchrov, I. Klotchkov, nd A. Smirnov. Towrds synthesis of monotonic synchronous circuits from signl trnsition grphs. In Proceedings of the Second Interntionl onference on Appliction of oncurrency to System Design, 001. [33] Z.Al Trwneh, G.Russell, nd A.Ykovlev. An nlysis of SEU roustness nd performnce of -element structures implemented in ulk MOS nd SOI technologies. Technicl report, Newcstle University, 010. [34] Kris Tiri nd Ingrid Veruwhede. A Logic Level Design Methodology for Secure DPA Resistnt ASI or FPGA Implementtion. In DATE 04: Proceedings of the conference on Design, utomtion nd test in Europe, pge IEEE omputer Society, 004. [35] E. Tuncer, J. ortdell, nd L. Lvgno. Enling dptility through elstic clocks. In DA 09: Proceedings of the 46th Annul Design Automtion onference, pges 8 10, 009. [36] E. Vittoz. Low Power electronics design, hpter 16. R Press, 004. [37] A. Wng nd A. hndrksn. A 180mV FFT processor using suthreshold circuit techniques. In Solid-Stte ircuits onference, 004.

CHAPTER 2 LITERATURE STUDY

CHAPTER 2 LITERATURE STUDY CHAPTER LITERATURE STUDY. Introduction Multipliction involves two bsic opertions: the genertion of the prtil products nd their ccumultion. Therefore, there re two possible wys to speed up the multipliction:

More information

Mixed CMOS PTL Adders

Mixed CMOS PTL Adders Anis do XXVI Congresso d SBC WCOMPA l I Workshop de Computção e Aplicções 14 20 de julho de 2006 Cmpo Grnde, MS Mixed CMOS PTL Adders Déor Mott, Reginldo d N. Tvres Engenhri em Sistems Digitis Universidde

More information

CHAPTER 3 AMPLIFIER DESIGN TECHNIQUES

CHAPTER 3 AMPLIFIER DESIGN TECHNIQUES CHAPTER 3 AMPLIFIER DEIGN TECHNIQUE 3.0 Introduction olid-stte microwve mplifiers ply n importnt role in communiction where it hs different pplictions, including low noise, high gin, nd high power mplifiers.

More information

Dataflow Language Model. DataFlow Models. Applications of Dataflow. Dataflow Languages. Kahn process networks. A Kahn Process (1)

Dataflow Language Model. DataFlow Models. Applications of Dataflow. Dataflow Languages. Kahn process networks. A Kahn Process (1) The slides contin revisited mterils from: Peter Mrwedel, TU Dortmund Lothr Thiele, ETH Zurich Frnk Vhid, University of liforni, Riverside Dtflow Lnguge Model Drsticlly different wy of looking t computtion:

More information

ISSCC 2006 / SESSION 21 / ADVANCED CLOCKING, LOGIC AND SIGNALING TECHNIQUES / 21.5

ISSCC 2006 / SESSION 21 / ADVANCED CLOCKING, LOGIC AND SIGNALING TECHNIQUES / 21.5 21.5 A 1.1GHz Chrge-Recovery Logic Visvesh Sthe, Jung-Ying Chueh, Mrios Ppefthymiou University of Michign, Ann Aror, MI Boost Logic is chrge-recovery circuit fmily cple of operting t GHz-clss frequencies

More information

Sequential Logic (2) Synchronous vs Asynchronous Sequential Circuit. Clock Signal. Synchronous Sequential Circuits. FSM Overview 9/10/12

Sequential Logic (2) Synchronous vs Asynchronous Sequential Circuit. Clock Signal. Synchronous Sequential Circuits. FSM Overview 9/10/12 9//2 Sequentil (2) ENGG5 st Semester, 22 Dr. Hden So Deprtment of Electricl nd Electronic Engineering http://www.eee.hku.hk/~engg5 Snchronous vs Asnchronous Sequentil Circuit This Course snchronous Sequentil

More information

Geometric quantities for polar curves

Geometric quantities for polar curves Roerto s Notes on Integrl Clculus Chpter 5: Bsic pplictions of integrtion Section 10 Geometric quntities for polr curves Wht you need to know lredy: How to use integrls to compute res nd lengths of regions

More information

MAXIMUM FLOWS IN FUZZY NETWORKS WITH FUNNEL-SHAPED NODES

MAXIMUM FLOWS IN FUZZY NETWORKS WITH FUNNEL-SHAPED NODES MAXIMUM FLOWS IN FUZZY NETWORKS WITH FUNNEL-SHAPED NODES Romn V. Tyshchuk Informtion Systems Deprtment, AMI corportion, Donetsk, Ukrine E-mil: rt_science@hotmil.com 1 INTRODUCTION During the considertion

More information

Digital Design. Sequential Logic Design -- Controllers. Copyright 2007 Frank Vahid

Digital Design. Sequential Logic Design -- Controllers. Copyright 2007 Frank Vahid Digitl Design Sequentil Logic Design -- Controllers Slides to ccompny the tetook Digitl Design, First Edition, y, John Wiley nd Sons Pulishers, 27. http://www.ddvhid.com Copyright 27 Instructors of courses

More information

& Y Connected resistors, Light emitting diode.

& Y Connected resistors, Light emitting diode. & Y Connected resistors, Light emitting diode. Experiment # 02 Ojectives: To get some hndson experience with the physicl instruments. To investigte the equivlent resistors, nd Y connected resistors, nd

More information

Kirchhoff s Rules. Kirchhoff s Laws. Kirchhoff s Rules. Kirchhoff s Laws. Practice. Understanding SPH4UW. Kirchhoff s Voltage Rule (KVR):

Kirchhoff s Rules. Kirchhoff s Laws. Kirchhoff s Rules. Kirchhoff s Laws. Practice. Understanding SPH4UW. Kirchhoff s Voltage Rule (KVR): SPH4UW Kirchhoff s ules Kirchhoff s oltge ule (K): Sum of voltge drops round loop is zero. Kirchhoff s Lws Kirchhoff s Current ule (KC): Current going in equls current coming out. Kirchhoff s ules etween

More information

Experiment 3: Non-Ideal Operational Amplifiers

Experiment 3: Non-Ideal Operational Amplifiers Experiment 3: Non-Idel Opertionl Amplifiers Fll 2009 Equivlent Circuits The bsic ssumptions for n idel opertionl mplifier re n infinite differentil gin ( d ), n infinite input resistnce (R i ), zero output

More information

On the Description of Communications Between Software Components with UML

On the Description of Communications Between Software Components with UML On the Description of Communictions Between Softwre Components with UML Zhiwei An Dennis Peters Fculty of Engineering nd Applied Science Memoril University of Newfoundlnd St. John s NL A1B 3X5 zhiwei@engr.mun.c

More information

Experiment 3: Non-Ideal Operational Amplifiers

Experiment 3: Non-Ideal Operational Amplifiers Experiment 3: Non-Idel Opertionl Amplifiers 9/11/06 Equivlent Circuits The bsic ssumptions for n idel opertionl mplifier re n infinite differentil gin ( d ), n infinite input resistnce (R i ), zero output

More information

CS 135: Computer Architecture I. Boolean Algebra. Basic Logic Gates

CS 135: Computer Architecture I. Boolean Algebra. Basic Logic Gates Bsic Logic Gtes : Computer Architecture I Boolen Algebr Instructor: Prof. Bhgi Nrhri Dept. of Computer Science Course URL: www.ses.gwu.edu/~bhgiweb/cs35/ Digitl Logic Circuits We sw how we cn build the

More information

A New Algorithm to Compute Alternate Paths in Reliable OSPF (ROSPF)

A New Algorithm to Compute Alternate Paths in Reliable OSPF (ROSPF) A New Algorithm to Compute Alternte Pths in Relile OSPF (ROSPF) Jin Pu *, Eric Mnning, Gholmli C. Shoj, Annd Srinivsn ** PANDA Group, Computer Science Deprtment University of Victori Victori, BC, Cnd Astrct

More information

Multi-beam antennas in a broadband wireless access system

Multi-beam antennas in a broadband wireless access system Multi-em ntenns in rodnd wireless ccess system Ulrik Engström, Mrtin Johnsson, nders Derneryd nd jörn Johnnisson ntenn Reserch Center Ericsson Reserch Ericsson SE-4 84 Mölndl Sweden E-mil: ulrik.engstrom@ericsson.com,

More information

Area-Time Efficient Digit-Serial-Serial Two s Complement Multiplier

Area-Time Efficient Digit-Serial-Serial Two s Complement Multiplier Are-Time Efficient Digit-Seril-Seril Two s Complement Multiplier Essm Elsyed nd Htem M. El-Boghddi Computer Engineering Deprtment, Ciro University, Egypt Astrct - Multipliction is n importnt primitive

More information

A Practical DPA Countermeasure with BDD Architecture

A Practical DPA Countermeasure with BDD Architecture A Prcticl DPA Countermesure with BDD Architecture Toru Akishit, Msnou Ktgi, Yoshikzu Miyto, Asmi Mizuno, nd Kyoji Shiutni System Technologies Lortories, Sony Corportion, -7- Konn, Minto-ku, Tokyo 8-75,

More information

Asynchronous Data-Driven Circuit Synthesis

Asynchronous Data-Driven Circuit Synthesis Asynchronous Dt-Driven Circuit Synthesis Sm Tylor, Doug Edwrds, Luis A Pln, Senior Memer, IEEE nd Luis A. Trzon D., Student Memer, IEEE Astrct A method is descried for synthesising synchronous circuits

More information

Design and implementation of a high-speed bit-serial SFQ adder based on the binary decision diagram

Design and implementation of a high-speed bit-serial SFQ adder based on the binary decision diagram INSTITUTE OFPHYSICS PUBLISHING Supercond. Sci. Technol. 16 (23) 1497 152 SUPERCONDUCTORSCIENCE AND TECHNOLOGY PII: S953-248(3)67111-3 Design nd implementtion of high-speed it-seril SFQ dder sed on the

More information

Discontinued AN6262N, AN6263N. (planed maintenance type, maintenance type, planed discontinued typed, discontinued type)

Discontinued AN6262N, AN6263N. (planed maintenance type, maintenance type, planed discontinued typed, discontinued type) ICs for Cssette, Cssette Deck ANN, ANN Puse Detection s of Rdio Cssette, Cssette Deck Overview The ANN nd the ANN re the puse detection integrted circuits which select the progrm on the cssette tpe. In

More information

The Discussion of this exercise covers the following points:

The Discussion of this exercise covers the following points: Exercise 4 Bttery Chrging Methods EXERCISE OBJECTIVE When you hve completed this exercise, you will be fmilir with the different chrging methods nd chrge-control techniques commonly used when chrging Ni-MI

More information

Solutions to exercise 1 in ETS052 Computer Communication

Solutions to exercise 1 in ETS052 Computer Communication Solutions to exercise in TS52 Computer Communiction 23 Septemer, 23 If it occupies millisecond = 3 seconds, then second is occupied y 3 = 3 its = kps. kps If it occupies 2 microseconds = 2 6 seconds, then

More information

(1) Non-linear system

(1) Non-linear system Liner vs. non-liner systems in impednce mesurements I INTRODUCTION Electrochemicl Impednce Spectroscopy (EIS) is n interesting tool devoted to the study of liner systems. However, electrochemicl systems

More information

MOS Transistors. Silicon Lattice

MOS Transistors. Silicon Lattice rin n Width W chnnel p-type (doped) sustrte MO Trnsistors n Gte Length L O 2 (insultor) ource Conductor (poly) rin rin Gte nmo trnsistor Gte ource pmo trnsistor licon sustrte doped with impurities dding

More information

Math Circles Finite Automata Question Sheet 3 (Solutions)

Math Circles Finite Automata Question Sheet 3 (Solutions) Mth Circles Finite Automt Question Sheet 3 (Solutions) Nickols Rollick nrollick@uwterloo.c Novemer 2, 28 Note: These solutions my give you the nswers to ll the prolems, ut they usully won t tell you how

More information

A Development of Earthing-Resistance-Estimation Instrument

A Development of Earthing-Resistance-Estimation Instrument A Development of Erthing-Resistnce-Estimtion Instrument HITOSHI KIJIMA Abstrct: - Whenever erth construction work is done, the implnted number nd depth of electrodes hve to be estimted in order to obtin

More information

To provide data transmission in indoor

To provide data transmission in indoor Hittite Journl of Science nd Engineering, 2018, 5 (1) 25-29 ISSN NUMBER: 2148-4171 DOI: 10.17350/HJSE19030000074 A New Demodultor For Inverse Pulse Position Modultion Technique Mehmet Sönmez Osmniye Korkut

More information

Computing Logic-Stage Delays Using Circuit Simulation and Symbolic Elmore Analysis

Computing Logic-Stage Delays Using Circuit Simulation and Symbolic Elmore Analysis Computing Logic-Stge Delys Using Circuit Simultion nd Symolic Elmore Anlysis Clyton B. McDonld Rndl E. Brynt Deprtment of Electricl nd Computer Engineering Crnegie Mellon University, Pittsurgh, PA 15213

More information

Homework #1 due Monday at 6pm. White drop box in Student Lounge on the second floor of Cory. Tuesday labs cancelled next week

Homework #1 due Monday at 6pm. White drop box in Student Lounge on the second floor of Cory. Tuesday labs cancelled next week Announcements Homework #1 due Mondy t 6pm White drop ox in Student Lounge on the second floor of Cory Tuesdy ls cncelled next week Attend your other l slot Books on reserve in Bechtel Hmley, 2 nd nd 3

More information

Engineer-to-Engineer Note

Engineer-to-Engineer Note Engineer-to-Engineer Note EE-297 Technicl notes on using Anlog Devices DSPs, processors nd development tools Visit our Web resources http://www.nlog.com/ee-notes nd http://www.nlog.com/processors or e-mil

More information

Localization of Latent Image in Heterophase AgBr(I) Tabular Microcrystals

Localization of Latent Image in Heterophase AgBr(I) Tabular Microcrystals Interntionl ymposium on ilver Hlide Technology Locliztion of Ltent Imge in Heterophse AgBr(I) Tulr Microcrystls Elen V. Prosvirkin, Aigul B. Aishev, Timothy A. Lrichev, Boris A. echkrev Kemerovo tte University,

More information

Understanding Basic Analog Ideal Op Amps

Understanding Basic Analog Ideal Op Amps Appliction Report SLAA068A - April 2000 Understnding Bsic Anlog Idel Op Amps Ron Mncini Mixed Signl Products ABSTRACT This ppliction report develops the equtions for the idel opertionl mplifier (op mp).

More information

The Design and Verification of A High-Performance Low-Control-Overhead Asynchronous Differential Equation Solver

The Design and Verification of A High-Performance Low-Control-Overhead Asynchronous Differential Equation Solver he Design nd Verifiction of A High-Performnce Low-Control-Overhed Asynchronous Differentil Eqution Solver Kenneth Y. Yun, Memer, IEEE, Peter A. Beerel, Memer, IEEE, Vid Vkilotojr, Student Memer, IEEE,

More information

Use of compiler optimization of software bypassing as a method to improve energy efficiency of exposed data path architectures

Use of compiler optimization of software bypassing as a method to improve energy efficiency of exposed data path architectures Guzm et l. EURASIP Journl on Emedded Systems 213, 213:9 RESEARCH Open Access Use of compiler optimiztion of softwre ypssing s method to improve energy efficiency of exposed dt pth rchitectures Vldimír

More information

A COMPARISON OF CIRCUIT IMPLEMENTATIONS FROM A SECURITY PERSPECTIVE

A COMPARISON OF CIRCUIT IMPLEMENTATIONS FROM A SECURITY PERSPECTIVE A COMPARISON OF CIRCUIT IMPLEMENTATIONS FROM A SECURITY PERSPECTIVE Mster Thesis Division of Electronic Devices Deprtment of Electricl Engineering Linköping University y Timmy Sundström LITH-ISY-EX--05/3698--SE

More information

High Speed On-Chip Interconnects: Trade offs in Passive Termination

High Speed On-Chip Interconnects: Trade offs in Passive Termination High Speed On-Chip Interconnects: Trde offs in Pssive Termintion Rj Prihr University of Rochester, NY, USA prihr@ece.rochester.edu Abstrct In this pper, severl pssive termintion schemes for high speed

More information

Magnetic monopole field exposed by electrons

Magnetic monopole field exposed by electrons Mgnetic monopole field exposed y electrons A. Béché, R. Vn Boxem, G. Vn Tendeloo, nd J. Vereeck EMAT, University of Antwerp, Groenenorgerln 171, 22 Antwerp, Belgium Opticl xis Opticl xis Needle Smple Needle

More information

LATEST CALIBRATION OF GLONASS P-CODE TIME RECEIVERS

LATEST CALIBRATION OF GLONASS P-CODE TIME RECEIVERS LATEST CALIBRATION OF GLONASS P-CODE TIME RECEIVERS A. Fos 1, J. Nwroci 2, nd W. Lewndowsi 3 1 Spce Reserch Centre of Polish Acdemy of Sciences, ul. Brtyc 18A, 00-716 Wrsw, Polnd; E-mil: fos@c.ww.pl; Tel.:

More information

ABB STOTZ-KONTAKT. ABB i-bus EIB Current Module SM/S Intelligent Installation Systems. User Manual SM/S In = 16 A AC Un = 230 V AC

ABB STOTZ-KONTAKT. ABB i-bus EIB Current Module SM/S Intelligent Installation Systems. User Manual SM/S In = 16 A AC Un = 230 V AC User Mnul ntelligent nstlltion Systems A B 1 2 3 4 5 6 7 8 30 ma 30 ma n = AC Un = 230 V AC 30 ma 9 10 11 12 C ABB STOTZ-KONTAKT Appliction Softwre Current Vlue Threshold/1 Contents Pge 1 Device Chrcteristics...

More information

Chapter 2 Literature Review

Chapter 2 Literature Review Chpter 2 Literture Review 2.1 ADDER TOPOLOGIES Mny different dder rchitectures hve een proposed for inry ddition since 1950 s to improve vrious spects of speed, re nd power. Ripple Crry Adder hve the simplest

More information

Network Theorems. Objectives 9.1 INTRODUCTION 9.2 SUPERPOSITION THEOREM

Network Theorems. Objectives 9.1 INTRODUCTION 9.2 SUPERPOSITION THEOREM M09_BOYL3605_13_S_C09.indd Pge 359 24/11/14 1:59 PM f403 /204/PH01893/9780133923605_BOYLSTAD/BOYLSTAD_NTRO_CRCUT_ANALYSS13_S_978013... Network Theorems Ojectives Become fmilir with the superposition theorem

More information

The Math Learning Center PO Box 12929, Salem, Oregon Math Learning Center

The Math Learning Center PO Box 12929, Salem, Oregon Math Learning Center Resource Overview Quntile Mesure: Skill or Concept: 300Q Model the concept of ddition for sums to 10. (QT N 36) Model the concept of sutrction using numers less thn or equl to 10. (QT N 37) Write ddition

More information

S1 Only VEOG HEOG. S2 Only. S1 and S2. Computer. Subject. Computer

S1 Only VEOG HEOG. S2 Only. S1 and S2. Computer. Subject. Computer The Eects of Eye Trcking in VR Helmet on EEG Recordings Jessic D. Byliss nd Dn H. Bllrd The University of Rochester Computer Science Deprtment Rochester, New York 14627 Technicl Report 685 My 1998 Astrct

More information

Fuzzy Logic Controller for Three Phase PWM AC-DC Converter

Fuzzy Logic Controller for Three Phase PWM AC-DC Converter Journl of Electrotechnology, Electricl Engineering nd Mngement (2017) Vol. 1, Number 1 Clusius Scientific Press, Cnd Fuzzy Logic Controller for Three Phse PWM AC-DC Converter Min Muhmmd Kml1,, Husn Ali2,b

More information

Improved Ensemble Empirical Mode Decomposition and its Applications to Gearbox Fault Signal Processing

Improved Ensemble Empirical Mode Decomposition and its Applications to Gearbox Fault Signal Processing IJCSI Interntionl Journl of Computer Science Issues, Vol. 9, Issue, No, Novemer ISSN (Online): 9- www.ijcsi.org 9 Improved Ensemle Empiricl Mode Decomposition nd its Applictions to Gerox Fult Signl Processing

More information

Three-Phase Synchronous Machines The synchronous machine can be used to operate as: 1. Synchronous motors 2. Synchronous generators (Alternator)

Three-Phase Synchronous Machines The synchronous machine can be used to operate as: 1. Synchronous motors 2. Synchronous generators (Alternator) Three-Phse Synchronous Mchines The synchronous mchine cn be used to operte s: 1. Synchronous motors 2. Synchronous genertors (Alterntor) Synchronous genertor is lso referred to s lterntor since it genertes

More information

Engineer-to-Engineer Note

Engineer-to-Engineer Note Engineer-to-Engineer Note EE-236 Technicl notes on using Anlog Devices DSPs, processors nd development tools Contct our technicl support t dsp.support@nlog.com nd t dsptools.support@nlog.com Or visit our

More information

PRACTICE NO. PT-TE-1414 RELIABILITY PAGE 1 OF 6 PRACTICES ELECTROSTATIC DISCHARGE (ESD) TEST PRACTICES

PRACTICE NO. PT-TE-1414 RELIABILITY PAGE 1 OF 6 PRACTICES ELECTROSTATIC DISCHARGE (ESD) TEST PRACTICES PREFERRED PRACTICE NO. PT-TE-1414 RELIABILITY PAGE 1 OF 6 ELECTROSTATIC DISCHARGE (ESD) TEST Prctice: Test stellites for the ility to survive the effects of electrosttic dischrges (ESDs) cused y spce chrging

More information

Design and Development of 8-Bits Fast Multiplier for Low Power Applications

Design and Development of 8-Bits Fast Multiplier for Low Power Applications IACSIT Interntionl Journl of Engineering nd Technology, Vol. 4, No. 6, Decemer 22 Design nd Development of 8-Bits Fst Multiplier for Low Power Applictions Vsudev G. nd Rjendr Hegdi, Memer, IACSIT proportionl

More information

Back to the Future: Digital Circuit Design in the FinFET Era

Back to the Future: Digital Circuit Design in the FinFET Era Copyright 2017 Americn Scientific Pulishers All rights reserved Printed in the United Sttes of Americ Journl of Low Power Electronics Vol. 13, 1 18, 2017 Bck to the Future: Digitl Circuit Design in the

More information

Implementation of Different Architectures of Forward 4x4 Integer DCT For H.264/AVC Encoder

Implementation of Different Architectures of Forward 4x4 Integer DCT For H.264/AVC Encoder Implementtion of Different Architectures of Forwrd 4x4 Integer DCT For H.64/AVC Encoder Bunji Antoinette Ringnyu, Ali Tngel, Emre Krulut 3 Koceli University, Institute of Science nd Technology, Koceli,

More information

Pennsylvania State University. University Park, PA only simple two or three input gates (e.g., AND/NAND,

Pennsylvania State University. University Park, PA only simple two or three input gates (e.g., AND/NAND, High-throughput nd Low-power DSP Using locked-mos ircuitry Mnjit Borh Robert Michel Owens Deprtment of omputer Science nd Engineering Pennsylvni Stte University University Prk, PA 16802 Mry Jne Irwin Abstrct

More information

10.4 AREAS AND LENGTHS IN POLAR COORDINATES

10.4 AREAS AND LENGTHS IN POLAR COORDINATES 65 CHAPTER PARAMETRIC EQUATINS AND PLAR CRDINATES.4 AREAS AND LENGTHS IN PLAR CRDINATES In this section we develop the formul for the re of region whose oundry is given y polr eqution. We need to use the

More information

Synchronous Machine Parameter Measurement

Synchronous Machine Parameter Measurement Synchronous Mchine Prmeter Mesurement 1 Synchronous Mchine Prmeter Mesurement Introduction Wound field synchronous mchines re mostly used for power genertion but lso re well suited for motor pplictions

More information

Control of high-frequency AC link electronic transformer

Control of high-frequency AC link electronic transformer Control of high-frequency AC link electronic trnsformer H. Krishnswmi nd V. Rmnrynn Astrct: An isolted high-frequency link AC/AC converter is termed n electronic trnsformer. The electronic trnsformer hs

More information

Module 9. DC Machines. Version 2 EE IIT, Kharagpur

Module 9. DC Machines. Version 2 EE IIT, Kharagpur Module 9 DC Mchines Version EE IIT, Khrgpur esson 40 osses, Efficiency nd Testing of D.C. Mchines Version EE IIT, Khrgpur Contents 40 osses, efficiency nd testing of D.C. mchines (esson-40) 4 40.1 Gols

More information

METHOD OF LOCATION USING SIGNALS OF UNKNOWN ORIGIN. Inventor: Brian L. Baskin

METHOD OF LOCATION USING SIGNALS OF UNKNOWN ORIGIN. Inventor: Brian L. Baskin METHOD OF LOCATION USING SIGNALS OF UNKNOWN ORIGIN Inventor: Brin L. Bskin 1 ABSTRACT The present invention encompsses method of loction comprising: using plurlity of signl trnsceivers to receive one or

More information

(CATALYST GROUP) B"sic Electric"l Engineering

(CATALYST GROUP) Bsic Electricl Engineering (CATALYST GROUP) B"sic Electric"l Engineering 1. Kirchhoff s current l"w st"tes th"t (") net current flow "t the junction is positive (b) Hebr"ic sum of the currents meeting "t the junction is zero (c)

More information

Proceedings of Meetings on Acoustics

Proceedings of Meetings on Acoustics Proceedings of Meetings on Acoustics Volume 19, 2013 http://cousticlsociety.org/ ICA 2013 Montrel Montrel, Cnd 2-7 June 2013 Signl Processing in Acoustics Session 4SP: Sensor Arry Bemforming nd Its Applictions

More information

Synchronous Machine Parameter Measurement

Synchronous Machine Parameter Measurement Synchronous Mchine Prmeter Mesurement 1 Synchronous Mchine Prmeter Mesurement Introduction Wound field synchronous mchines re mostly used for power genertion but lso re well suited for motor pplictions

More information

Direct Current Circuits. Chapter Outline Electromotive Force 28.2 Resistors in Series and in Parallel 28.3 Kirchhoff s Rules 28.

Direct Current Circuits. Chapter Outline Electromotive Force 28.2 Resistors in Series and in Parallel 28.3 Kirchhoff s Rules 28. P U Z Z L E R If ll these pplinces were operting t one time, circuit reker would proly e tripped, preventing potentilly dngerous sitution. Wht cuses circuit reker to trip when too mny electricl devices

More information

Software for the automatic scaling of critical frequency f 0 F2 and MUF(3000)F2 from ionograms applied at the Ionospheric Observatory of Gibilmanna

Software for the automatic scaling of critical frequency f 0 F2 and MUF(3000)F2 from ionograms applied at the Ionospheric Observatory of Gibilmanna ANNALS OF GEOPHYSICS, VOL. 47, N. 6, Decemer 2004 Softwre for the utomtic scling of criticl frequency f 0 F2 nd MUF(3000)F2 from ionogrms pplied t the Ionospheric Oservtory of Giilmnn Michel Pezzopne nd

More information

Exercise 1-1. The Sine Wave EXERCISE OBJECTIVE DISCUSSION OUTLINE. Relationship between a rotating phasor and a sine wave DISCUSSION

Exercise 1-1. The Sine Wave EXERCISE OBJECTIVE DISCUSSION OUTLINE. Relationship between a rotating phasor and a sine wave DISCUSSION Exercise 1-1 The Sine Wve EXERCISE OBJECTIVE When you hve completed this exercise, you will be fmilir with the notion of sine wve nd how it cn be expressed s phsor rotting round the center of circle. You

More information

Experimental Application of H Output-Feedback Controller on Two Links of SCARA Robot

Experimental Application of H Output-Feedback Controller on Two Links of SCARA Robot INTERNATIONAL JOURNAL OF CONTROL, AUTOMATION AND SYSTEMS VOL.5 NO. Jnury 6 ISSN 65-877 (Print) ISSN 65-885 (Online) http://www.reserchpu.org/journl/jc/jc.html Experimentl Appliction of H Output-Feedck

More information

Testing Delay Faults in Asynchronous Handshake Circuits

Testing Delay Faults in Asynchronous Handshake Circuits Testing Dely Fults in Asynchronous Hnshke Circuits Feng Shi Electricl Engineering Dept. Yle University New Hven, Connecticut feng.shi@yle.eu Yiorgos Mkris Electricl Engineering Dept. Yle Univerisity New

More information

Timing Macro-modeling of IP Blocks with Crosstalk

Timing Macro-modeling of IP Blocks with Crosstalk Timing Mcro-modeling of IP Blocks with Crosstlk Ruiming Chen nd Hi Zhou Electricl nd Computer Engineering Northwestern Universit Evnston, IL 60208 Astrct With the increse of design compleities nd the decrese

More information

Study on SLT calibration method of 2-port waveguide DUT

Study on SLT calibration method of 2-port waveguide DUT Interntionl Conference on Advnced Electronic cience nd Technology (AET 206) tudy on LT clibrtion method of 2-port wveguide DUT Wenqing Luo, Anyong Hu, Ki Liu nd Xi Chen chool of Electronics nd Informtion

More information

Algorithms for Memory Hierarchies Lecture 14

Algorithms for Memory Hierarchies Lecture 14 Algorithms for emory Hierrchies Lecture 4 Lecturer: Nodri Sitchinv Scribe: ichel Hmnn Prllelism nd Cche Obliviousness The combintion of prllelism nd cche obliviousness is n ongoing topic of reserch, in

More information

PRO LIGNO Vol. 11 N pp

PRO LIGNO Vol. 11 N pp THE INFLUENCE OF THE TOOL POINT ANGLE AND FEED RATE ON THE DELAMINATION AT DRILLING OF PRE-LAMINATED PARTICLEBOARD Mihi ISPAS Prof.dr.eng. Trnsilvni University of Brsov Fculty of Wood Engineering Address:

More information

Lab 8. Speed Control of a D.C. motor. The Motor Drive

Lab 8. Speed Control of a D.C. motor. The Motor Drive Lb 8. Speed Control of D.C. motor The Motor Drive Motor Speed Control Project 1. Generte PWM wveform 2. Amplify the wveform to drive the motor 3. Mesure motor speed 4. Mesure motor prmeters 5. Control

More information

Automatic Synthesis of Compressor Trees: Reevaluating Large Counters

Automatic Synthesis of Compressor Trees: Reevaluating Large Counters Automtic Snthesis of Compressor Trees: Reevluting Lrge Counters Aj K. Verm AjKumr.Verm@epfl.ch Polo Ienne Polo.Ienne@epfl.ch Ecole Poltechnique Fédérle de Lusnne (EPFL) School of Computer nd Communiction

More information

INSTITUTE OF AERONAUTICAL ENGINEERING (Autonomous) Dundigal, Hyderabad

INSTITUTE OF AERONAUTICAL ENGINEERING (Autonomous) Dundigal, Hyderabad Hll Ticket No Question Pper Code: AEC009 INSTITUTE OF AERONAUTICAL ENGINEERING (Autonomous) Dundigl, Hyderd - 500 043 MODEL QUESTION PAPER Four Yer B.Tech V Semester End Exmintions, Novemer - 2018 Regultions:

More information

Example. Check that the Jacobian of the transformation to spherical coordinates is

Example. Check that the Jacobian of the transformation to spherical coordinates is lss, given on Feb 3, 2, for Mth 3, Winter 2 Recll tht the fctor which ppers in chnge of vrible formul when integrting is the Jcobin, which is the determinnt of mtrix of first order prtil derivtives. Exmple.

More information

EE Controls Lab #2: Implementing State-Transition Logic on a PLC

EE Controls Lab #2: Implementing State-Transition Logic on a PLC Objective: EE 44 - Controls Lb #2: Implementing Stte-rnsition Logic on PLC ssuming tht speed is not of essence, PLC's cn be used to implement stte trnsition logic. he dvntge of using PLC over using hrdwre

More information

Interference Cancellation Method without Feedback Amount for Three Users Interference Channel

Interference Cancellation Method without Feedback Amount for Three Users Interference Channel Open Access Librry Journl 07, Volume, e57 ISSN Online: -97 ISSN Print: -9705 Interference Cncelltion Method without Feedbc Amount for Three Users Interference Chnnel Xini Tin, otin Zhng, Wenie Ji School

More information

Lecture 16: Four Quadrant operation of DC Drive (or) TYPE E Four Quadrant chopper Fed Drive: Operation

Lecture 16: Four Quadrant operation of DC Drive (or) TYPE E Four Quadrant chopper Fed Drive: Operation Lecture 16: Four Qudrnt opertion of DC Drive (or) TYPE E Four Qudrnt chopper Fed Drive: Opertion The rmture current I is either positive or negtive (flow in to or wy from rmture) the rmture voltge is lso

More information

FPGA Based Five-Phase Sinusoidal PWM Generator

FPGA Based Five-Phase Sinusoidal PWM Generator 22 IEEE Interntionl Conference on Power nd Energy (PECon), 25 Decemer 22, Kot Kinlu Sh, Mlysi FPGA Bsed FivePhse Sinusoidl PWM Genertor Tole Sutikno Dept. of Electricl Engineering Universits Ahmd Dhln

More information

Available online at ScienceDirect. Procedia Engineering 89 (2014 )

Available online at   ScienceDirect. Procedia Engineering 89 (2014 ) Aville online t www.sciencedirect.com ScienceDirect Procedi Engineering 89 (2014 ) 411 417 16th Conference on Wter Distriution System Anlysis, WDSA 2014 A New Indictor for Rel-Time Lek Detection in Wter

More information

Soft switched DC-DC PWM Converters

Soft switched DC-DC PWM Converters Soft switched DC-DC PWM Converters Mr.M. Prthp Rju (), Dr. A. Jy Lkshmi () Abstrct This pper presents n upgrded soft switching technique- zero current trnsition (ZCT), which gives better turn off chrcteristics

More information

Research Letter Investigation of CMOS Varactors for High-GHz-Range Applications

Research Letter Investigation of CMOS Varactors for High-GHz-Range Applications Reserch Letters in Electronics Volume 29, Article ID 53589, 4 pges doi:1.1155/29/53589 Reserch Letter Investigtion of CMOS Vrctors for High-GHz-Rnge Applictions Ming Li, Rony E. Amy, Roert G. Hrrison,

More information

Eliminating Non-Determinism During Test of High-Speed Source Synchronous Differential Buses

Eliminating Non-Determinism During Test of High-Speed Source Synchronous Differential Buses Eliminting Non-Determinism During of High-Speed Source Synchronous Differentil Buses Abstrct The t-speed functionl testing of deep sub-micron devices equipped with high-speed I/O ports nd the synchronous

More information

Alternating-Current Circuits

Alternating-Current Circuits chpter 33 Alternting-Current Circuits 33.1 AC Sources 33.2 esistors in n AC Circuit 33.3 Inductors in n AC Circuit 33.4 Cpcitors in n AC Circuit 33.5 The LC Series Circuit 33.6 Power in n AC Circuit 33.7

More information

5 I. T cu2. T use in modem computing systems, it is desirable to. A Comparison of Half-Bridge Resonant Converter Topologies

5 I. T cu2. T use in modem computing systems, it is desirable to. A Comparison of Half-Bridge Resonant Converter Topologies 74 EEE TRANSACTONS ON POER ELECTRONCS, VOL. 3, NO. 2, APRL 988 A Comprison of Hlf-Bridge Resonnt Converter Topologies Abstrct-The hlf-bridge series-resonnt, prllel-resonnt, nd combintion series-prllel

More information

Calculation of Off-Core Inductance in Dual-Circuit Model of Transformer

Calculation of Off-Core Inductance in Dual-Circuit Model of Transformer Clcultion of Off-Core Inductnce in Dul-Circuit Model of Trnsformer As Lotfi NTNU Trondheim, Norwy s.lotfi@ntnu.no Hns Kr. Hoidlen NTNU Trondheim, Norwy hns.hoidlen@ntnu.no Nicol Chies Sttoil Trondheim,

More information

POWER QUALITY IMPROVEMENT BY SRF BASED CONTROL USING DYNAMIC VOLTAGE RESTORER (DVR)

POWER QUALITY IMPROVEMENT BY SRF BASED CONTROL USING DYNAMIC VOLTAGE RESTORER (DVR) Interntionl Journl of Electricl Engineering & Technology (IJEET) Volume 9, Issue 1, Jn-Fe 2018, pp. 51 57, rticle ID: IJEET_09_01_005 ville online t http://www.ieme.com/ijeet/issues.sp?jtype=ijeet&vtype=9&itype=1

More information

EET 438a Automatic Control Systems Technology Laboratory 5 Control of a Separately Excited DC Machine

EET 438a Automatic Control Systems Technology Laboratory 5 Control of a Separately Excited DC Machine EE 438 Automtic Control Systems echnology bortory 5 Control of Seprtely Excited DC Mchine Objective: Apply proportionl controller to n electromechnicl system nd observe the effects tht feedbck control

More information

Th ELI1 09 Broadband Processing of West of Shetland Data

Th ELI1 09 Broadband Processing of West of Shetland Data Th ELI 9 Brodnd Processing of West of Shetlnd Dt R. Telling* (Dolphin Geophysicl Limited), N. Riddlls (Dolphin Geophysicl Ltd), A. Azmi (Dolphin Geophysicl Ltd), S. Grion (Dolphin Geophysicl Ltd) & G.

More information

Joanna Towler, Roading Engineer, Professional Services, NZTA National Office Dave Bates, Operations Manager, NZTA National Office

Joanna Towler, Roading Engineer, Professional Services, NZTA National Office Dave Bates, Operations Manager, NZTA National Office . TECHNICA MEMOANDM To Cc repred By Endorsed By NZTA Network Mngement Consultnts nd Contrctors NZTA egionl Opertions Mngers nd Are Mngers Dve Btes, Opertions Mnger, NZTA Ntionl Office Jonn Towler, oding

More information

April 9, 2000 DIS chapter 10 CHAPTER 3 : INTEGRATED PROCESSOR-LEVEL ARCHITECTURES FOR REAL-TIME DIGITAL SIGNAL PROCESSING

April 9, 2000 DIS chapter 10 CHAPTER 3 : INTEGRATED PROCESSOR-LEVEL ARCHITECTURES FOR REAL-TIME DIGITAL SIGNAL PROCESSING April 9, 2000 DIS chpter 0 CHAPTE 3 : INTEGATED POCESSO-LEVEL ACHITECTUES FO EAL-TIME DIGITAL SIGNAL POCESSING April 9, 2000 DIS chpter 3.. INTODUCTION The purpose of this chpter is twofold. Firstly, bsic

More information

University of Dayton Research Institute Dayton, Ohio, Materials Laboratory Wright Patterson AFB, Ohio,

University of Dayton Research Institute Dayton, Ohio, Materials Laboratory Wright Patterson AFB, Ohio, LEAKY PLATE WAVE INSPECTION OF BIAXIAL COMPOSITES Richrd W. Mrtin University of Dyton Reserch Institute Dyton, Ohio, 45469-0001 Dle E. Chimenti Mterils Lortory Wright Ptterson AFB, Ohio, 45433-6533 INTRODUCTION

More information

EY-AM 300: novanet BACnet application master, modunet300

EY-AM 300: novanet BACnet application master, modunet300 Product dt sheet 96.010 EY-AM 300: novnet BACnet ppliction mster, modunet300 How energy efficiency is improved Open communiction for interoperle opertion of the entire optimised plnt. Fetures Prt of the

More information

D I G I TA L C A M E R A S PA RT 4

D I G I TA L C A M E R A S PA RT 4 Digitl Cmer Technologies for Scientific Bio-Imging. Prt 4: Signl-to-Noise Rtio nd Imge Comprison of Cmers Yshvinder Shrwl, Solexis Advisors LLC, Austin, TX, USA B I O G R A P H Y Yshvinder Shrwl hs BS

More information

Research on Local Mean Decomposition Algorithms in Harmonic and Voltage Flicker Detection of Microgrid

Research on Local Mean Decomposition Algorithms in Harmonic and Voltage Flicker Detection of Microgrid Sensors & Trnsducers 23 by IFSA http://www.sensorsportl.com Reserch on Locl Men Decomposition Algorithms in Hrmonic nd Voltge Flicer Detection of Microgrid Wensi CAO, Linfei LIU School of Electric Power,

More information

Open Access A Novel Parallel Current-sharing Control Method of Switch Power Supply

Open Access A Novel Parallel Current-sharing Control Method of Switch Power Supply Send Orders for Reprints to reprints@enthmscience.e 170 The Open Electricl & Electronic Engineering Journl, 2014, 8, 170-177 Open Access A Novel Prllel Current-shring Control Method of Switch Power Supply

More information

Experiment 8 Series DC Motor (II)

Experiment 8 Series DC Motor (II) Ojectives To control the speed of loded series dc motor y chnging rmture voltge. To control the speed of loded series dc motor y dding resistnce in prllel with the rmture circuit. To control the speed

More information

THE STUDY OF INFLUENCE CORE MATERIALS ON TECHNOLOGICAL PROPERTIES OF UNIVERSAL BENTONITE MOULDING MATERIALS. Matej BEZNÁK, Vladimír HANZEN, Ján VRABEC

THE STUDY OF INFLUENCE CORE MATERIALS ON TECHNOLOGICAL PROPERTIES OF UNIVERSAL BENTONITE MOULDING MATERIALS. Matej BEZNÁK, Vladimír HANZEN, Ján VRABEC THE STUDY OF INFLUENCE CORE MATERIALS ON TECHNOLOGICAL PROPERTIES OF UNIVERSAL BENTONITE MOULDING MATERIALS Mtej BEZNÁK, Vldimír HANZEN, Ján VRABEC Authors: Mtej Beznák, Assoc. Prof. PhD., Vldimír Hnzen,

More information

Exponential-Hyperbolic Model for Actual Operating Conditions of Three Phase Arc Furnaces

Exponential-Hyperbolic Model for Actual Operating Conditions of Three Phase Arc Furnaces Americn Journl of Applied Sciences 6 (8): 1539-1547, 2009 ISSN 1546-9239 2009 Science Publictions Exponentil-Hyperbolic Model for Actul Operting Conditions of Three Phse Arc Furnces 1 Mhdi Bnejd, 2 Rhmt-Allh

More information

Characterization of 3x3 and 4x4 multimode interference couplers in InP generic photonic integration technology

Characterization of 3x3 and 4x4 multimode interference couplers in InP generic photonic integration technology Chrcteriztion of x nd x multimode interference couplers in InP generic photonic integrtion technology Cittion for pulished version (APA): Pustkhod, D., Jing, X., vn Vliet, E. M., Willims, K. A., & Leijtens,

More information