VOUT = 5V VIN = 8V COUT CIN SENSE RPG EN/ UVLO OFF GND VOUT = 5V VIN = 8V CIN ADJ RPG EN/ UVLO OFF GND
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1 VIN = 8V OFF ON CIN 1µF R1 1kΩ R2 1kΩ + VIN EN/ UVLO GND VOUT SENSE PG + COUT 1µF VOUT = 5V RPG 1kΩ PG VIN = 8V OFF ON CIN 1µF R3 1kΩ R4 1kΩ + VIN EN/ UVLO GND VOUT ADJ PG R1 4.2kΩ R2 13kΩ VOUT = 5V + COUT 1µF RPG 1kΩ PG
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6 ADP712 Data Sheet PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS VOUT 1 SENSE/ADJ 2 GND 3 NC 4 ADP712 TOP VIEW (Not to Scale) 8VIN 7PG 6GND 5 EN/UVLO VOUT 1 SENSE/ADJ 2 GND 3 NC 4 ADP712 TOP VIEW (Not to Scale) VIN PG GND EN/UVLO NOTES 1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN. 2. IT IS HIGHLY RECOMMENDED THAT THE EXPOSED PAD ON THE BOTTOM OF THE PACKAGE BE CONNECTED TO THE GROUND PLANE ON THE BOARD. Figure 3. LFCSP Package NOTES 1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN. 2. IT IS HIGHLY RECOMMENDED THAT THE EXPOSED PAD ON THE BOTTOM OF THE PACKAGE BE CONNECTED TO THE GROUND PLANE ON THE BOARD. Figure 4. Narrow Body SOIC Package Table 5. Pin Function Descriptions Pin No. Mnemonic Description 1 VOUT Regulated Output Voltage. Bypass VOUT to GND with a 1 μf or greater capacitor. 2 SENSE/ADJ Sense (SENSE). Measures the actual output voltage at the load and feeds it to the error amplifier. Connect SENSE as close as possible to the load to minimize the effect of IR drop between the regulator output and the load. This function applies to fixed voltages only. Adjust Input (ADJ). An external resistor divider sets the output voltage. This function applies to adjustable voltages only. 3 GND Ground. 4 NC Do Not Connect to this Pin. 5 EN/UVLO Enable Input (EN). Drive EN high to turn on the regulator; drive EN low to turn off the regulator. For automatic startup, connect EN to VIN. Programmable Undervoltage Lockout (UVLO). When the programmable UVLO function is used, the upper and lower thresholds are determined by the programming resistors. 6 GND Ground. 7 PG Power Good. This open-drain output requires an external pull-up resistor to VIN or VOUT. If the part is in shutdown, current limit, thermal shutdown, or falls below 9% of the nominal output voltage, PG immediately transitions low. If the power good function is not used, the pin may be left open or connected to ground. 8 VIN Regulator Input Supply. Bypass VIN to GND with a 1 μf or greater capacitor. EPAD Exposed Pad. Exposed paddle on the bottom of the package. The EPAD enhances thermal performance and is electrically connected to GND inside the package. It is highly recommended that the EPAD be connected to the ground plane on the board. Rev. D Page 6 of 28
7 GROUND CURRENT (µa) GROUND CURRENT (µa) GROUND CURRENT (µa) LOAD = 1µA LOAD = 3mA LOAD = 1µA LOAD = 3mA C 5 C 25 C 85 C 125 C 4 C 5 C 25 C 85 C 125 C T J ( C) T J ( C) I LOAD (ma) I LOAD (ma) LOAD = 1µA LOAD = 3mA LOAD = 1µA LOAD = 3mA V IN (V) V IN (V)
8 DROPOUT (mv) SHUTDOWN CURRENT (µa) GROUND CURRENT (µa) V 4.V 6.V 8.V 12.V 2.V LOAD = 5mA 2 LOAD = 2mA LOAD = 3mA TEMPERATURE ( C) V IN (V) V OUT = 3.3V T A = 25 C LOAD = 1µA LOAD = 3mA C 5 C 25 C 85 C 125 C I LOAD (ma) T J ( C) LOAD = 1µA 2.95 LOAD = 3mA V IN (V) I LOAD (ma)
9 GROUND CURRENT (µa) GROUND CURRENT (µa) DROPOUT (mv) GROUND CURRENT (µa) LOAD = 1µA LOAD = 3mA LOAD = 1µA LOAD = 3mA V IN (V) V IN (V) LOAD = 1µA LOAD = 3mA V OUT = 5V T A = 25 C C 5 C 25 C 85 C 125 C T J ( C) I LOAD (ma) I LOAD (ma) LOAD = 5mA 4.7 LOAD = 2mA LOAD = 3mA V IN (V)
10 GROUND CURRENT (µa) GROUND CURRENT (µa) GROUND CURRENT (µa) LOAD = 1µA LOAD = 3mA LOAD = 5mA LOAD = 2mA LOAD = 3mA V IN (V) V IN (V) LOAD = 1µA LOAD = 3mA LOAD = 1µA LOAD = 3mA C 5 C 25 C 85 C 125 C T J ( C) 4 C 5 C 25 C 85 C 125 C T J ( C) I LOAD (ma) I LOAD (ma)
11 I OUT SHUTDOWN CURRENT (µa) GROUND CURRENT (µa) 12 1 LOAD = 1µA LOAD = 3mA LOAD = 1µA LOAD = 3mA V IN (V) V IN (V) LOAD = 1µA LOAD = 3mA V 4V 5V 6V 8V 1V 12V 15V 18V 2V C 5 C 25 C 85 C 125 C T J ( C) TEMPERATURE ( C) LOAD = 3mA I LOAD (ma) k 1k 1k 1M 1M FREQUENCY (Hz)
12 LOAD = 3mA 1 2 LOAD = 3mA k 1k 1k 1M 1M k 1k 1k 1M 1M FREQUENCY (Hz) FREQUENCY (Hz) 1 2 LOAD = 3mA 1 2 LOAD = 3mA k 1k 1k 1M 1M k 1k 1k 1M 1M FREQUENCY (Hz) FREQUENCY (Hz) 1 2 LOAD = 3mA 1 2 LOAD = 3mA k 1k 1k 1M 1M k 1k 1k 1M 1M FREQUENCY (Hz) FREQUENCY (Hz)
13 LOAD = 3mA 1 2 LOAD = 3mA k 1k 1k 1M 1M k 1k 1k 1M 1M FREQUENCY (Hz) FREQUENCY (Hz) 1 2 LOAD = 3mA 1 2 LOAD = 3mA k 1k 1k 1M 1M FREQUENCY (Hz) HEADROOM VOLTAGE (V) 1 2 LOAD = 3mA 1 2 LOAD = 3mA k 1k 1k 1M 1M FREQUENCY (Hz) HEADROOM VOLTAGE
14 NOISE (µv rms) µv/ Hz 1 2 LOAD = 3mA 1 3.3V 5V 5V ADJ 5V ADJ NR k 1k 1k HEADROOM VOLTAGE (V) FREQUENCY (Hz) LOAD = 3mA LOAD CURRENT OUTPUT VOLTAGE HEADROOM VOLTAGE (V) CH1 2mA Ω B W CH2 5mV B W M 2µs A CH1 76mA T 1.4% 3 LOAD CURRENT OUTPUT VOLTAGE 3.3V 5 1.8V 5V 5V ADJ 5V ADJ NR LOAD CURRENT (A) Ω B W B W CH1 2mA CH2 5mV M 2µs A CH1 168mA T 1.2%
15 LOAD CURRENT INPUT VOLTAGE 1 2 OUTPUT VOLTAGE 2 OUTPUT VOLTAGE 1 Ω B W B W CH1 2mA CH2 5mV M 2µs A CH1 216mA T 1.2% CH1 1V B W CH2 1mV B W M 4µs A CH4 1.56V T 9.8% INPUT VOLTAGE INPUT VOLTAGE 2 OUTPUT VOLTAGE 2 OUTPUT VOLTAGE 1 CH1 1V B W CH2 1mV B W M 4µs A CH4 1.56V T 9.8% 1 CH1 1V B W CH2 1mV B W M 4µs A CH4 1.56V T 9.8%
16 INPUT VOLTAGE INPUT VOLTAGE 2 OUTPUT VOLTAGE 2 OUTPUT VOLTAGE 1 CH1 1V B W CH2 1mV B W M 4µs A CH4 1.56V T 9.8% 1 CH1 1V B W CH2 1mV B W M 4µs A CH4 1.56V T 9.8% INPUT VOLTAGE 2 OUTPUT VOLTAGE 1 CH1 1V B W CH2 1mV B W M 4µs A CH4 1.56V T 9.8%
17 Data Sheet THEORY OF OPERATION The ADP712 is a low quiescent current, low-dropout linear regulator that operates from 3.3 V to 2 V and provides up to 3 ma of output current. Drawing a low 75 μa of quiescent current (typical) at full load makes the ADP712 ideal for battery-operated portable equipment. Typical shutdown current consumption is 4 μa at room temperature. Optimized for use with small 1 μf ceramic capacitors, the ADP712 provides excellent transient performance. VIN GND EN/ UVLO VIN GND EN/ UVLO VREG 1µA SHORT-CIRCUIT, THERMAL PROTECT SHUTDOWN PGOOD R1 R2 1.22V REFERENCE Figure 6. Fixed Output Voltage Internal Block Diagram VREG 1µA SHORT-CIRCUIT, THERMAL PROTECT SHUTDOWN PGOOD 1.22V REFERENCE VOUT PG SENSE VOUT PG SENSE Figure 61. Adjustable Output Voltage Internal Block Diagram Internally, the ADP712 consists of a reference, an error amplifier, a feedback voltage divider, and a PMOS pass transistor. Output current is delivered via the PMOS pass device, which is controlled by the error amplifier. The error amplifier compares the reference voltage with the feedback voltage from the output and amplifies the difference. If the feedback voltage is lower than the reference voltage, the gate of the PMOS device is pulled lower, allowing more current to pass and increasing the output voltage. If the feedback voltage ADP712 is higher than the reference voltage, the gate of the PMOS device is pulled higher, allowing less current to pass and decreasing the output voltage. The ADP712 is available in 7 fixed output voltage options, ranging from 1.8 V to 9 V and in an adjustable version with an output voltage that can be set to between 1.22 V and 19 V by an external voltage divider. The output voltage can be set according to the following equation: VOUT = 1.22 V(1 + R1/R2) VIN = 8V OFF ON CIN 1µF R3 1kΩ R4 1kΩ + VIN VOUT R1 4.2kΩ ADJ EN/ UVLO GND PG R2 13kΩ RPG 1kΩ VOUT = 5V + COUT 1µF Figure 62. Typical Adjustable Output Voltage Application Schematic The value of R2 should be less than 2 kω to minimize errors in the output voltage caused by the ADJ pin input current. For example, when R1 and R2 each equal 2 kω, the output voltage is 2.44 V. The output voltage error introduced by the ADJ pin input current is 2 mv or.8%, assuming a typical ADJ pin input current of 1 na at 25 C. The ADP712 uses the EN/UVLO pin to enable and disable the VOUT pin under normal operating conditions. When EN/UVLO is high, VOUT turns on, when EN is low, VOUT turns off. For automatic startup, EN/UVLO can be tied to VIN. The ADP712 incorporates reverse current protections circuitry that prevents current flow backwards through the pass element when the output voltage is greater than the input voltage. A comparator senses the difference between the input and output voltages. When the difference between the input voltage and output voltage exceeds 55 mv, the body of the PFET is switched to VOUT and turned off or opened. In other words, the gate is connected to VOUT. PG Rev. D Page 17 of 28
18 CAPACITANCE (µf) LOAD CURRENT VOLTAGE (V) 2 OUTPUT VOLTAGE CH1 2mA Ω B W CH2 5mV B W M 2µs A CH1 76mA T 1.4%
19 VIN = 8V OFF ON CIN 1µF R1 1kΩ R2 1kΩ + VIN EN/ UVLO VOUT SENSE PG + COUT 1µF VOUT = 5V RPG 1kΩ PG GND V OUT, EN RISE V OUT, EN FALL V V 2 ENABLE TIME (µs)
20 PG (V) PG (V) 6 5 PG 4 C PG 5 C PG +25 C PG +85 C PG +125 C 4 3 VIN = 8V CIN 1µF + VIN VOUT R FB1 4.2kΩ ADJ + C NR 1nF VOUT = 5V + COUT 1µF 2 1 OFF ON 1kΩ 1kΩ EN/ UVLO GND PG R FB2 13kΩ R NR 13kΩ 1kΩ PG PG 4 C PG 5 C PG +25 C PG +85 C PG +125 C
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22 JUNCTION TEMPERATURE ( C) JUNCTION TEMPERATURE ( C) JUNCTION TEMPERATURE ( C) JUNCTION TEMPERATURE ( C) JUNCTION TEMPERATURE ( C) JUNCTION TEMPERATURE ( C) mm 2 5mm mm 2 T J MAX TOTAL POWER DISSIPATION (W) 45 64mm 2 5mm mm 2 T J MAX TOTAL POWER DISSIPATION (W) mm 2 6 5mm 2 25mm 2 T J MAX mm 2 6 5mm 2 25mm 2 T J MAX TOTAL POWER DISSIPATION (W) TOTAL POWER DISSIPATION (W) mm mm 2 25mm 2 T J MAX mm mm 2 25mm 2 T J MAX TOTAL POWER DISSIPATION (W) TOTAL POWER DISSIPATION (W)
23 JUNCTION TEMPERATURE (T J ) JUNCTION TEMPERATURE (T J ) TB = 25 C TB = 5 C 2 TB = 65 C TB = 85 C T J MAX TOTAL POWER DISSIPATION (W) TB = 25 C TB = 5 C 2 TB = 65 C TB = 85 C T J MAX TOTAL POWER DISSIPATION (W)
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25 Data Sheet ADP712 OUTLINE DIMENSIONS SQ SEATING PLANE INDEX AREA TOP VIEW.8 MAX.55 NOM.5 BSC EXPOSED PAD MIN BOTTOM VIEW PIN 1 INDICATOR (R.2).5 MAX FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO.2 NOM THE PIN CONFIGURATION AND COPLANARITY FUNCTION DESCRIPTIONS.8 SECTION OF THIS DATA SHEET..2 REF COMPLIANT TOJEDEC STANDARDS MO-229-WEED-4 Figure Lead Lead Frame Chip Scale Package [LFCSP_WD] 3 mm 3 mm Body, Very Very Thin, Dual Lead (CP-8-5) Dimensions shown in millimeters B SEATING PLANE 1.27 BSC TOP VIEW REF MAX.5 NOM COPLANARITY BOTTOM VIEW COMPLIANT TO JEDEC STANDARDS MS-12-AA Figure Lead Standard Small Outline Package, with Exposed Pad [SOIC_N_EP] Narrow Body (RD-8-2) Dimensions shown in millimeters REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET B Rev. D Page 25 of 28
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