DeviceNet Physical Layer Design and Conformance Testing

Transcription

1 DeviceNet Physical Layer Design and Conformance Testing Kiah Hion Tang, Richard T. McLaughlin DeviceNet Europe Technical Support Centre, University of Warwick, U.K. Abstract DeviceNet defines a more tightened specification on the physical layer implementation than. It includes the power-supply specification, bit timing specification, connector requirement, etc. Because of this, its physical layer implementation is very much different from other based fieldbuses. Some vendors are having difficulties in implementing the physical layer that conforms to the DeviceNet Specification. This paper describes and analyses the concept and architecture of the DeviceNet Physical Layer, the implementation considerations, and the physical layer testing developed by the University of Warwick for the ODVA. 1 Introduction To ensure a proper design of the physical layer the DeviceNet Physical Layer Special Interest Group (Physical SIG) has documented a few chapters [i] within the DeviceNet Specification explaining and describing the need and requirement of the physical layer design. This includes the design of the power supply, transceiver, connector, as well as the LED section. Nonetheless, much confusion still arises on these topics, as feedback by the vendors, that the document does not fully describe in detail the requirement and the functions of each component. We will discuss these in this paper, and give some guidelines on the design of the physical layer, as well as how the conformance test will be carried out on the physical payer. In addition, to ensure data consistency and safety over long distance, the bit timing settings on the controller is also an important issue, and will be addressed in this paper too. 2 Design Consideration As specified in the DeviceNet Specification, every DeviceNet conformed device must has its physical layer ( transceiver) powered from the network. This is because unpowered transceivers have low output impedance, which will affect the total impedance of the network, and is not desirable in any based network. Therefore the design of the internal power supply section is very important. Failure to design according to the specification leads to the failure in passing the Physical Layer Conformance Test, and more important ly, failure to interoperate with (or jeopardise) other devices on the same network. 2.1 Power Supply To address the power supply section design issue, the example power supply circuit in Figure 9.4, Volume I of the DeviceNet Specification is reproduced here, as seen in Figure 1 [ii]. The following discussions will be based on this circuit diagram. V BE Vi IC1 +5V D1 : Transceiver Figure 1 Example power supply design Voltage Regulator DeviceNet requires the support of the standard industrial voltage ranges from 11 to 25 Volts (DC). Since the operating voltage within the device is normally 5 Volts, a voltage regulator is required to step down the voltage from 11 to 25 Volts down to 5 Volts. Several regulation methods are commonly used here: 1. Linear regulator. This is the simplest method. The advantage of the linear regulator is that, unlike switch mode power supply, there is no high frequency interference, thus designing the power supply section is easier. The disadvantage, on the other hand, is the efficiency. This is particularly important

2 because of the need to support a wide range of input voltages. From the power dissipation equation, P = I out ( V V ) If a typical system draws a current of 50 ma, then the power dissipated by the regulator will be in the range of 0.30 to 0.95 Watts for input voltage ranges from 11 to 25 Volts. This value is not negligibly low. A heat sink is normally required in this case. Therefore this type of power supply design is not suitable for a circuit that needs to source large current, unless one is willing to fit a large heat sink on the regulator. 2. Switch mode power supply. Modern switch mode power supplies are becoming cheaper and cheaper, although not as cheap as the linear type. Therefore its use is increasingly popular. The advantage is that, it does not dissipate large amount of power. This increases the efficiency. In addition, because it does not require heat sink, the size can be fairly small, thus suitable for compact design Transistor Switch in out Referring to Figure 1, the primary function of the transistor switch is to prevent the mis -wiring of and terminals (in conjunction with D1, more detail about this diode can be found in Section 2.1.3). As can be seen, if and terminals are reversed, transistor will not be turned on (reversed biased), hence there will be no power supplied to the system circuit. The secondary function of the transistor switch, which is not documented, is to distribute the load (voltage drop) of regulator IC1, in case IC1 is a linear regulator (or other type of regulators that prefer to have as little voltage drop as possible). By distributing the load, IC1 can draw larger current without overheating. Of course will then need to be able to take such load without overheating as well. In order for the Step-down voltage regulator (see Section 2.1.1) to correctly supply 5 Volts (a typical voltage for TTL components) to the circuit, the output voltage of the transistor switch (Vi) needs to be higher than 6.5 Volts (typically) [iii]. The higher this input voltage is, the larger the voltage drops on IC1, which represents undesired power dissipation. Therefore the base-emitter bias voltage of, VBE, formed by the potential divider and, should be sufficient to supply Vi of 6.5 Volts with an input voltage,, of 11 Volts. However, doing so will cause the transistor switch to swing to the saturation region at = 24V, i.e. fully turn on the transistor. This means Vi will be 24V. The regulator IC1 will then have a voltage drop of 24-5 = 19V, as seen in Figure 2. Vi Figure 2 Relation between and Vi This implies that a small current drawn by the system will cause large power dissipation on the regulator IC1, see Section Therefore care must be taken when designing circuits with the linear regulator Protection Diode Section 9-2.2, Volume I of the DeviceNet Specification states that [iv] : The Schottky diode is inserted in the ground path to prevent accidental connection of the signal to the terminal. A transistor switch inserted into the supply path prevents damage which can occur due to a loss of connection. The above sentence does not fully describe the function of the diode D1, causing many vendors to ignore the diode in order to reduce cost. First of all, the loss of ground protection cannot be achieved without the Schottky diode D1 in place, see Figure 3. = 24V = 11V Vi IC1 +5V : Transceiver Figure 3 Loss of Ground protection cannot be achieved without the Schottky diode In Figure 3, it can be seen that, if the Schottky diode D1 is not present, and the terminal is disconnected (loss-of-ground), current will flow

3 from the terminal to the terminals (dotted line). This creates a bias voltage to transistor, hence turns on, and supplies the voltage to the system. The reference ground of this system, in this case, is therefore higher than the nominal ground (). As a result, the voltage of _H and _L will be pulled up to a level beyond the nominal value, thus destroying the whole network. The critical path of this design is the ground point of the transceiver. Until the protection diode is built into the ground path of the transceiver, the Schottky diode should always be in place. status of the network power, and avoid transmitting unacknowledged signals when there is no network power. A common mistake made in the design is that, the power sensing point is taken either directly from the terminals or the Collector terminal of, as seen in Figure 5. sensor IC1 To controller Isolation For any type of isolator used, the isolation voltage between the system circuit and the physical layer circuit must be at least ±500 VDC. There are many isolation methods available, one of the most commonly adopted one is the opto-isolator, which is shown in Figure 4. : Transceiver Figure 5 Example mistake Node / App Specific up / HCPL 7101 Opto HCPL 7101 Opto Isolated Phys Layer Reg. In this case, the power will still be detected even when either or IC1 is not functioning. Since the primary reason of sensing the bus power is to prevent the microcontroller from unnecessary transmission (and entering passive or bus-off state) when the transceiver is not powered, sensing the regulated output voltage is more appropriate. Therefore, it is suggested the bus power sensor should be placed after the regulator IC1, as seen in Figure 6. 82C250 Transceiver Reg. To controller sensor IC1 R4 Figure 4 DeviceNet recommended isolated physical layer design [v] : Transceiver When opto-isolator is used in the design, beside the isolation voltage, one of the major concerns is the propagation speed. More detail about the propagation delay can be found in Section Network Power Sensor When a device s system circuit is powered from a separate power supply (isolated physical layer), it is recommended to have a network power sensor circuit built in. This allows the device to detect the Figure 6 Suggested implementation of bus power sensor 2.2 Transceiver Effective Output Impedance Because DeviceNet specifies the requirements of output impedance, which should be typically 40KΩ, it is usually not recommended to add extra

4 components at the _H and _L pins, either passive or active, as it reduces the effective output impedance of the node, as seen in Figure 7. The physical layer and media layer spec defined by DeviceNet are sufficient to avoid the interference from the external noise under normal manufacturing environment. Transceiver These circuits are not required Figure 7 Filtering circuit is not required Auto-baud When designing a device with the auto-baud feature, care must be taken to avoid the transmission of error frames. The very basic idea is to listen to the bus activity, and check the receiveerror register. Until a correct frame is captured, the device should not go online. The question here is, how to avoid a controller from transmitting error frames when wrong bit-rate is used? Some new controllers, such as SJA1000, offers this feature down to the silicon layer. This simplifies the job very much. Some controllers allow developers to programmatically set the output control to high impedance, preventing the chip from transmitting error frames when wrong bit rate is used. For those controllers that do not offer this feature, additional logic is required before the transceiver, as seen in Figure 8. Gate Control Tx OR Rx transceiver Figure 8 Additional logic for auto-baud The truth table can be seen as in Table 1. During power cycle or hard reset, the gate is set to logic 1, the output will be recessive regardless of the Tx value. In this way, during the baud rate selection period, any error frames transmitted by the controller will not be broadcast on the bus. When the correct baud rate is selected, the gate is set to logic 0. In this case the bit level follows the Tx value. The propagation time of this gate should be chosen as short as possible. For example, wire-or formed by discrete components can be used. Gate Tx (NAND) 0 0 Dominant 0 1 Recessive 1 0 Recessive 1 1 Recessive Table 1 Output Control Logic 2.3 Connector As specified in the specification that all semipermanent connector must be gold plated. This is because the plug-unplug operation will oxidise the connector if it is not gold-plated. DB-9 connector has not been published in the specification at the time of writing this paper, therefore the use of DB-9 connector is not allowed yet. 3 Conformance Testing The DeviceNet Physical Layer conformance testing is carried out with the black-box approach. This means all internal hardware architecture will be ignored. The measurements will be taken from the external visible parts, such as the connectors, LED, etc. It is encouraged, although not required, that the vendors to submit the schematic diagram of the physical layer circuit to the test labs as soon as the test order is submitted to ODVA. This allows the lab to review the possible physical design bug that might affect the test result. The following will highlight some of the important area covered by the ODVA Physical Layer Conformance Testing. 3.1 LEDs Behaviour DeviceNet specifies the behaviour of the Network, Module, and Status LEDs. If any of these are implemented, it must be a bicolour (RED/GREEN) LED. The LED will be insp ected visually during power up, normal operation, and bus off. Any other forms of LED behaviour can be implemented, simply do not label it with a DeviceNet specified name.

5 3.2 Supply Voltage Range The DUT will be tested against the network voltage ranges from 11 to 25 Volts. In conjunction with this, the current drawn at these voltage levels will also be recorded. 3.3 levels _H and _L levels are verified according to the DeviceNet Specification, as seen in Table 2. Parameters Recessive _H 2.0 to 3.6 _L 2.0 to 3.6 _H _L Range (Volt) 0.45 maximum Dominant _H dominant 2.75 to 5.1 _L dominant 0.5 to 2.86 _H _L 0.95 minimum Table 2 levels It is important to note that the voltage drop of the Schottky diode in Figure 1 is taken into account. This forward voltage drop should be 0.6 volt maximum. 3.4 Bit Timing The bit time is measured to the accuracy of 99.9%. This accuracy is generally achievable using crystal oscillator. transmits the duplicate MAC ID check message [1], and captures the whole message frame. An instrument called scope [vi], as seen in Figure 9, is used for this purpose. With this instrument, the time-difference between the reference and measure lines can be captured, and the bit time tolerance can be calculated. The accuracy of the calculated value depends strongly on the sampling frequency. In this case, a 32 MHz frequency is used, thus the accuracy is ± ηs. In the example shown in Figure 9, the oscillator tolerance is calculated as: time difference between N bit OD = 100% number of bit, N bit period t1 t0 1 = 100% N 2us us = 100% 99 2us = 99.98% This figure falls within the tolerance specified in the DeviceNet specification. 3.5 Mis-wiring This is the most hazardous test. The mis-wiring test simply mis-wires the five DeviceNet wires to see if any of these leads to the permanent damage to the DUT or other devices on the same network. Figure 9 Duplicate MAC ID Check message captured by scope In the University of Warwick, this test is carried out by connecting the device on the test network as a sole occupant, power up the device so that it 1 For devices that implement the listen-only feature during power-up, some mechanism needs to be used to trigger the device to transmit the duplicate MAC ID check messages, which is beyond the topic, and will not be discussed here.

6 This means that during mis-wiring, the DUT should also behave as expected, the voltages at each terminal should stay within allowed limits. Due to the fact that some existing transceiver cannot sustain more than 18Volts, the mis-wiring test on the _H and _L pin is carried out at 18 Volts instead of 25 Volts. 3.6 System Propagation Delay Because a receiver has to participate in the acknowledgement slot, the slower the propagation speed of the system, the later the acknowledgement bit insertion. The system propagation delay is the contribution of the transceiver, controller, and optionally the opto-isolator. The system propagation delay is measured to ensure the device is capable of working under maximum cable distance of the corresponding bit rate. Controller 62.5ηs 40ηs Optoisolator Optoisolator 40ηs Figure 10 System Delay Referring to Figure 10, a standard DeviceNet approved cable has propagation delay of 450ηs over 100 meters. A standard controller has internal propagation delay of 62.5ηs. The transceiver propagation delay is 170ηs. The optoisolator delay is 80ηs (40ηs 2) The total delay introduced by these components are 762.5ηs. For a sender to send a message over 100 meter and get an acknowledgement back, the total time is double of this value, i.e µs. This value is 76.25% of a bit time. Therefore it is critically important that: 90ηs transceiver 80ηs The sum of the component propagation delays must not exceed the specified value. The sampling point of the receiver has to be set to more than 80% of a bit time. should not exceed eight amperes at any length of time. 4 Summary The intention of this paper is not to teach the vendors how to design the DeviceNet physical layer, but to give some design guidelines, as well as describing some of the rules and common pitfalls. As long as these pitfalls are avoided, and the design rules are followed exactly, vendors are free to adopt their preferred hardware concepts. DeviceNet vendors are encouraged to discuss with the ODVA for any problems found in their physical layer design. European vendors can send to: kiah.tang@warwick.ac.uk or call +44 (0) References [i] These are in Chapter 2, 8, 9, 10, and Appendix A, B, C, D, E, F of Volume I of the ODVA DeviceNet Specification. [ii] This can be found in Figure 9.4, Page 9-5, Volume I of the ODVA DeviceNet Specification. [iii] This is based on the National Semiconductors data-sheet, see page 1-197, Power IC s Databook, [iv] See page 9-4, Volume I of the ODVA DeviceNet Specification. [v] The complete description of the isolated physical layer design can be found in the DeviceNet Specification 2.0, Volume I, page 9-8. [vi] scope is a collaborated product of G.i.N and Vector Informatik. 3.7 Inrush Current Inrush current is tested during the power cycle time. A maximum value will be taken. This value