A Self-Contained Large-Scale FPAA Development Platform

Transcription

1 A SelfContained LargeScale FPAA Development Platform Christopher M. Twigg, Paul E. Hasler, Faik Baskaya School of Electrical and Computer Engineering Georgia Institute of Technology, Atlanta, Georgia Abstract Analog circuits and systems research and education can significantly benefit from the computational flexibility provided by largescale FPAAs. The component density of these devices is sufficient to synthesize large systems in a short period of time. However, this level of reconfigurable and programmable complexity requires a development platform and CAD tools to demonstrate the capabilities of largescale FPAAs before they will be widely accepted. To address this need, a selfcontained FPAA setup has been developed along with an integrated software design flow. With only an ethernet connection and an AC power outlet, a researcher or student can explore the numerous analog circuit possibilities provided by largescale FPAAs. I. FPAAS IN RESEARCH AND EDUCATION Field programmable analog arrays (FPAAs) present a great opportunity for analog systems research and education by significantly reducing development time. Traditional analog design techniques require months of IC layout and fabrication, which can slow the progress of analog hardware research. This also restricts analog VLSI courses to using prefabricated ICs for laboratory exercises, unless the course spans multiple terms. FPAAs allow researchers and students to synthesize analog circuits and systems in a matter of hours or days, like FPGAs do for digital systems. Some FPAAs are even capable of dynamic reconfiguration [1], which enables these analog systems to be adapted or modified while running. Researchers can implement and test their design ideas in silicon without lengthy delays, and students can design and test their own analog hardware configurations while taking the related course. Largescale FPAAs, such as the reconfigurable analog signal processor (RASP) ICs [2], provide the reconfigurable analog component density needed to implement large and complex systems. These devices contain large arrays of computational analog blocks (s) connected by various levels of routing networks, as depicted in Fig. 1. Each contains a number of circuits and primitive elements, such as OTAs with programmable biases, transistors, and capacitors. Including the floating gate switches as computational elements [3], there are over 50,000 programmable analog components on these largescale FPAAs. This level of complexity provides great flexibility for analog systems implementation, but it illustrates the need for a CAD tool design flow and a hardware platform for developing new ideas. Many FPGA companies provide development kits, like Altera [4] and Xilinx [5], which feature numerous interfaces and displays for demonstrating the capabilities of their devices. For largescale FPAAs to be successfully adopted, a similar platform is needed to promote Fig. 1. The RASP 2.x FPAAs feature a twodimensional array of s interconnected by local and global routing buses. Fig. 2. Selfcontained FPAA setup housed within a portable box. and enable the use of these devices for analog circuits and system research and education. II. SELFCONTAINED FPAA SETUP The selfcontained FPAA setup, as seen in Fig. 2, was developed to fill the need for a largescale FPAA demonstration platform. It is composed of a commercial FPGA development board, a custom FPAA board, and a power module. This development platform is selfcontained in that it only requires a single AC power connection and an ethernet connection to a PC. The original test bench setup for FPAAs, as depicted in /07 $ IEEE. 1187

2 PC ethernet, GPIB, RS232 FPGA Connector DACs s<8> s<10> s<12> s<14> J19 agnd vb<0> vb<1> vb<2> MATLAB ADC / DAC Card ethernet Oscilloscope FPGA (a) Picoammeter FPAA Lockin Amplifier Supply J5 J6 ADC agnd dgnd LA V D PA I2V J13 ADC DAC s<1> s<3> s<5> s<7> J15 d<11> d<10> d<9> d<8> * * J18 d<9> d<8> RASP 2.7 IC d<7> d<6> d<5> d<4> J4 J20 d<7> d<6> d<5> d<4> J21 J22 J14 s<15> vdd vdd s<9> s<11> s<13> J16 J23 s<0> s<2> s<4> s<6> * d<0> d<1> d<2> d<3> J17 in out right left left right in out jacks PC MATLAB ethernet, GPIB, RS232 Bench Equipment box Fig. 4. FPAA board components of the selfcontained setup. ethernet FPGA Supply FPAA Audio, Sensors, etc (b) Fig. 3. Laboratory setup. (a) Original setup using bench equipment and an FPAA interface board. (b) Setup using selfcontained FPAA box. Fig. 3a, was constructed using components from an analog IC test bench. A very primitive FPAA board, composed of level shifters, buffers, and a minimal set of DACs, was used simply to interface with the FPAA IC for programming purposes. An offtheshelf FPGA board was used to control the timing of the FPAA board s programming circuits and to facilitate communication with a PC. Once the FPAA was programmed, testing was performed using several pieces of bench equipment that included picoammeters, oscilloscopes, and lockin amplifiers. Biases were generated using a power supply and a DAC card within the PC. The entire system was then unified through MATLAB software running on the PC. Although this setup was good for demonstrating the capabilities of largescale FPAAs, it was too large and expensive to encourage widespread applications development. To address these issues, the selfcontained setup was designed to integrate as much of the test instrumentation as practical onto the FPAA board. As seen in Fig. 3b, the new setup retains the commercial FPGA board for interface simplicity and to encourage future applications development using cooperative analog and digital signal processing. A power module is also included to reduce the number of power supply connections that need to be made. With the modifications made to the FPAA board, this new setup requires just one AC power outlet and an ethernet connection to perform most testing. However, bench equipment or other forms of input and output interfaces may also be used for advanced features. The modified FPAA board design is depicted in Fig. 4. Just as before, the FPGA board is used for digital control of all 1188 Fig. 5. MATLAB GUI integrating the complete design flow. components on the FPAA board and for facilitating communication to the PC over ethernet. The board still contains the level shifters, DACs, and buffers for programming, but it also contains a number of DACs for biases to eliminate the need for external biasing sources. To replace the function of the oscilloscope and lockin amplifier, an ADC and DAC pair are included and controlled by synchronized digital hardware synthesized on the FPGA. Onboard current measurement is performed using a logarithmic currenttovoltage (I2V) converter along with an ADC to measure programming and signal currents between 10 pa and 20 ma. Since processing is a common application of these FPAAs, jacks and interface circuitry are also included to connect MP3 players and other sources. III. DESIGN FLOW The success of any development platform is highly dependent upon the quality of the available CAD tools. An integrated development environment is commonly used to efficiently generate the programming files that define the configuration of the FPGA or FPAA. Since the software interface of the previous test bench setups had been written in MATLAB, a GUI interface, as seen in Fig. 5, was created to integrate the various design flow steps in MATLAB. The first step of the design flow is to define the circuit

3 V DD V in.5 V Fig. 6. Source follower example drawn in XCircuit. %Bias Switches: %Switch Elements: %Programming Switches: Fig. 7. FPAA programmer file for the source follower example circuit. The number pairs represent floating gate transistor addresses within the array V in (a) time (ms) (b) Fig. 8. Measurements of the source follower example circuit. (a) DC response (b) Step response.5 V V DD using some entry method, whether graphical or description language. XCircuit [6], an open source schematic capture program, is used for this setup because it is simple, free, and generates SPICE netlists. A component library corresponding to the analog components within the RASP were added to XCircuit enabling the user to place and connect components within the schematic. Fig. 6 shows a simple source follower schematic drawn in XCircuit. With the schematic drawn and the SPICE netlist generated, the next step is to place and route the circuit. The RASPER 1 tools [7] were developed to perform this task for the RASP line of FPAAs. RASPER reads the SPICE netlist created by XCircuit and generates a programming file, as seen in Fig. 7, and a postsynthesis SPICE netlist. User defined constraints, such as input/output pins, are entered as comment string sequences to maintain SPICE netlist compatibility, which allows the netlist to be simulated prior to physical synthesis. The simplest components, transistors and capacitors, appear in the netlist as standard SPICE primitive elements. However, the larger components are implemented as subcircuits. In a similar fashion, RASPER also supports a nested hierarchical description of the circuit. The second RASPER output file, the postsynthesis SPICE 1 The RASPER tool was partially funded by NSF grant CNS netlist, is used to simulate the circuit with interconnect parasitics. This gives the user valuable insight into the impact of switches on the overall circuit performance as well as a means for troubleshooting and compensating for the parasitic effects before device programming. There is also an effort toward using SPICE as a synthesis optimization guide within the RASPER to automatically compensate for, or at least balance, the parasitic effects on circuit paths. The programmer file, Fig. 7, is passed to the midlevel MATLAB programming routines, which interpret the switch positions and biasing information and controls the various signals used to configure and program the FPAA. For the standard user, this involves simple MATLAB commands that require very little understanding of the underlying technology of the FPAA, which is important for encouraging individuals, such as digital signal processing engineers, to use these reconfigurable and programmable analog devices. For more advanced FPAA interfacing, lowlevel MATLAB routines are also available that provide a means of interacting with individual floating gate transistors within the array. This can be particularly useful for floating gate transistor education in class laboratories.

4 V bias V in1 V in2 V ref Fig. 9. Capacitively coupled voltage summation circuit example. Due to the topology, the summed voltages are also inverted at the output IV. DEMONSTRATION TEST CIRCUITS Any development platform requires example circuits that demonstrate the capabilities of the target device while showing the user possible applications that could be developed around such devices. The FPAA board features several components intended to demonstrate basic functionality as well as application space specific interfacing. Using the onboard DACs and current measurement hardware, circuit primitives, such as transistors, can be characterized using IV sweeps. At the circuit level, the onboard ADC can be utilized to perform DC voltage sweeps and step responses, as seen in the source follower examples of Fig. 8a and Fig. 8b. To demonstrate a potential application, jacks were included on the FPAA board to facilitate signal processing. Fig. 9 illustrates an example circuit that adds the left and right input channels to form a mono output signal, which can be played through the jack to any powered speaker. Fig. 10 shows the results of this circuit when connected to the output of a PC. A 1 khz sinusoid was played through the PC s left output and 2 khz sinusoid through the right. The summed output of the circuit was captured using an oscilloscope, and it played using a set of powered speakers. Although this example is rather simple, it does demonstrate that a level of signal processing can be performed on these ICs using real world input sources, such as MP3 players or any other stereo source. In a similar fashion, much larger demonstration systems could be constructed around the interface circuitry. Using the onchip bandpass filters, the input signal can be spectrally decomposed into any number of channels. Various transforms and analog functions can be performed on each channel in parallel. For output circuits, the individual channels are then recombined using a voltage summation circuit similar to that in Fig. 9. However, more advanced processing systems, such as the feature extraction frontend of a speech recognition system, can use vectormatrix multipliers to perform weighted summations of any number of channel combinations. This information could then be passed on to the FPGA board for further processing Time (ms) Fig. 10. Measured results of the voltage summation circuit. The third waveform is the inverted summation of the first two sinusoids. V. CONCLUSION A viable demonstration and development platform has been introduced for the RASP line of largescale FPAAs. These selfcontained setups provide a means for investigating the potential research applications of largescale FPAAs to analog signal processing. In addition, educational laboratory exercises can utilize this platform for analog circuit design and signal processing courses. The proposed CAD tool flow, although rather primitive, is sufficient to enable engineers with varying levels of reconfigurable and programmable analog experience to interact with the FPAAs using only an ethernet connection to a PC running MATLAB. VI. ACKNOWLEDGEMENTS The authors would like to thank Tyson S. Hall and Jordan D. Gray for their contributions to the RASP line of FPAAs, David V. Anderson and Sung Kyu Lim for their support of the RASPER tool development, and Jeremy White and Alvin Yates for their contributions to the FPAA library used in XCircuit. REFERENCES [1] AN231E04 Datasheet, Dynamically Reconfigurable DSASP, Anadigm, doc/ds U001.pdf, Aug. 2006, product description. [2] C. M. Twigg and P. Hasler, A large scale reconfigurable analog signal processor (RASP) IC, in IEEE Proceedings of the Custom Integrated Circuits Conference, 2006, pp [3] C. M. Twigg, J. D. Gray, and P. E. Hasler, Programmable floating gate FPAA switches are not dead weight, in IEEE Proceedings of the International Symposium on Circuits and Systems, 2007, p. accepted. [4] Development Kits, Altera R, platforms.jsp, Oct. 2006, product description. [5] Development s, Xilinx, Oct. 2006, product description. [6] XCircuit, Tim Edwards, Oct. 2006, software description. [7] F. Baskaya, S. Reddy, S. K. Lim, and D. V. Anderson, Placement for large scale floating gate field programable analog arrays, IEEE Transactions on Very Large Scale Integration Systems, vol. 14, no. 8, 2006.

5 VII. DEMO DESCRIPTION This demonstration will illustrate the use of the selfcontained FPAA setup as a development platform. The entire design flow from schematic capture to hardware testing will be displayed. The demonstration circuits will range in complexity from simple transistor IV sweeps to an processing circuit utilizing the onboard jack interface. A portable source, such as an MP3 player, will be used in conjunction with a pair of powered speakers to demonstrate this circuit using real world signals. Additionally, participants will be encouraged to interact with the system by drawing circuits, synthesizing them for the FPAA, and downloading the resulting configuration to the board. Using simple MATLAB routines, these users will be able to then test these designs using the onboard test hardware. 1191