GENERALIZED PWM TECHNIQUE FOR DUAL INVERTER FED INDUCTION MOTOR DRIVE

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1 28 Acta Electrotechnica et Inforatica, ol. 14, No. 1, 2014, 28 36, DOI: /aeei GENERALIZED PWM TECHNIQUE FOR DUAL INERTER FED INDUCTION MOTOR DRIE M. HARSHAARDHAN REDDY *, T. BRAHMANANDA REDDY *, B. RAINDRANATH REDDY ** M. SURYA KALAATHI ** * Departent of Electrical and Electronics Engineering, G. Pulla Reddy Engineering College (Autonoous) Kurnool, Andhra Pradesh, India, e-ail: arareddyharsha@gail.co, tbnr@rediffail.co ** Departent of Electrical and Electronics Engineering, JNTUH, Hyderabad, Andhra Pradesh, India ABSTRACT This paper presents a siplified Generalized Pulse Width Modulation (GPWM) algorith to obtain various continuous and discontinuous PWM algoriths for a four-level inverter topology. The proposed four-level inverter is achieved by feeding the induction otor fro both ends by a three-level cascade inverter fro one side and by two-level inverter fro other side. The proposed inverter configuration is capable to produce an output voltage of two-level, three-level and four-level in entire odulation range. In the proposed inverter topology neutral point fluctuations are absent and neutral claping diodes are absent. With the application of various discontinuous PWM algoriths to the proposed inverter topology the switching losses are reduced when copared with continuous PWM algorith. The siulation analyses are carried out in MATLAB/siulink environent and the results are presented. Keywords: Cascade inverter, GPWM, open end winding induction otor, SPWM 1. INTRODUCTION oltage Source Inverters (SI) are getting popularized in adjustable speed drive applications. To control the output voltage and output frequency of SI, the pulse width odulation (PWM) techniques are eployed. The switching fashion eployed in PWM techniques reduces haronics in the output voltage. Based on switching fashion different PWM techniques are proposed in literature [1-5]. Aong arious PWM techniques space vector pulse width odulation (SPWM) technique proposed in [4-5] gives superior perforance for a voltage source inverter. SPWM discussed in [4], in a given sapling tie (T s ) the switching ties for which active voltage vectors and zero voltage vectors ties are given by (1). In conventional SPWM algorith, the zero vector tie (T z ) is divided equally aong the two possible zero states. The calculation of switching ties (T 1, T 2, T z ) require angular inforation (α) and agnitude of reference voltage ( ref ) at each instant, which akes the SPWM algorith coplex. 2 3 T1 = M i sin π 2 3 T2 = M i sin π TZ = Ts T1 T2 0 ( 60 α ) ( α ) Ts Ts where M i is the odulation index πref M i =. 2 dc In [5], the authors proposed a siplified algorith where no need to calculate the angular inforation by using the concept of iaginary switching ties. Along with siplification of algorith, various discontinuous PWM algoriths have been presented in [7-8] by unequal division of zero state ties. (1) However, the two-level inverters produce ore haronic distortion. In two-level inverter topologies as switching frequency increases the haronic content in line current gets reduced. In order to have low haronic content at low switching frequency ultilevel inverter topologies are eployed. Different ultilevel inverter topologies are presented in literature [9-10]. Conventional Multilevel inverter topologies like diode claped and H-bridge topologies discussed in [9-11] require claping diodes, separate DC-link voltages sources for their. Multilevel inverter topologies have the drawbacks of neutral point fluctuations and coplexity increases as nuber of levels increases. To overcoe these drawbacks and reduce coplexity cascade and dual inverter topologies are presented in literature. As ultilevel inverter topologies can synthesis output voltage wavefor fro sall individual voltage sources. Two two-level inverters are cascaded to generated three level output voltage, this configuration is called cascade inverter topology proposed in literature [12]. Siilarly two two-level inverter topologies feed the load fro both ends called dual inverter configuration is proposed in literature [13]. Both cascade and dual inverter topologies are cobined as shown in Fig.1 to generate four-level output voltage [14-15]. In this paper, a siplified and ore generalized approach is presented to generate all possible continuous and discontinuous PWM (DPWM) signals by adding a zero sequence voltage to the coanded reference signals. The haronic content in the output voltage is low at low switching frequency by eploying proposed topology. But the switching losses can also be reduced by eploying various DPWM algoriths. 2. PROPOSED INERTER TOPOLOGY The proposed circuit topology is obtained by feeding induction otor fro both ends by three-level cascade inverter and two-level inverter as shown in Fig. 1.

2 Acta Electrotechnica et Inforatica, ol. 14, No. 1, Fig. 3 Modulation signal position during two-level Fig. 1 Proposed inverter topology A1o, B1o, C1o represents the pole voltage of inverter- I. As two inverters are cascaded inverter-i can generate three level output voltage. A2o', B2o', C2o' are the pole voltages of Inverter-II. A1A2, B1B2, C1C2 are the effective phase voltages. The cobined pole voltage of proposed ulti level inverter are given by All the phases of inverter-i produces a two-level output voltage ( dc /3 or 2 dc /3) by operating switches (S 1, S 3, S 5 ) and (S 2, S 4, S 6 ) and claping the switches (S 7, S 9, S 11 ) to a voltage of positive voltage of dc /3. The corresponding pole voltages, phase voltages and line voltages are shown in Fig. 4. A B C = = = A1O B1O C1O A2O B2O C2O (2) To control the output voltage and frequency of proposed inverter topology, various carrier based PWM algoriths are presented in this paper. In ultilevel inverter topologies to generate N-level output voltage (N- 1) level shifting triangles are required. So for the proposed topology, to generate four-level output, three level shifting triangles are required. The level shifting triangles are divided into three regions R1, R2 and R3 as shown in Fig. 2. Fig. 4 oltage plots during two-level by using the SPWM algorith Fig. 2 Different regions in carrier coparison approach Let us consider c be the aplitude of triangle wave and be the aplitude of reference wave. Now we define odulation index as M i = (3) ( N 1) C If the odulation signal lies within the region R 1 as shown in Fig. 3, only Inverter-I is in and inverter-ii is claped. As the cobined pole voltage of the proposed inverter produces two-level output the ode of is called as two-level. If the odulating wave is present in both regions R 1 and R 2 as shown in Fig. 5, all the switches in inverter-i operate continuously to produce output voltage. When switches (S 1, S 3, S 5 ) and (S 7, S 9, S 11 ) are ON Inverter-I produces an output voltage of (2 dc /3). When (S 2, S 4, S 6 ) and (S 7, S 9, S 11 ) are ON inverter-i produces an output voltage of ( dc /3). When (S 8, S 10, S 12 ) are ON, inverter-i produces zero output voltage. Siilarly, all the switches in inverter-ii are claped to produce a zero voltage.

3 30 Generalized PWM Technique for Dual Inverter Fed Induction Motor Drive pole voltages, phase voltages and line voltages during four level s are shown in Fig. 7. Fig. 5 Modulating signal during three-level Therefore the effective pole voltage of proposed ultilevel inverter contains three levels (2 dc /3, dc /3, 0). So this ode of is known as three-level ode of. The corresponding pole voltages, phase voltages and line voltages are shown in Fig. 6 during three-level ode of. Fig. 7 oltage plots during four-level by using the SPWM algorith Table 1 Different voltages during four-level Pole voltage of inverter-i a10 Pole voltage of Inverter-II a20 Effective pole voltage a dc /3 - dc /3 dc /3 0 + dc /3 dc /3 dc /3 0 2 dc / dc /3 2 dc /3 dc /3 + dc /3 Fig. 6 oltage plots during three-level by using the SPWM algorith When the odulating signal is present in all the three regions as shown in Fig.2 all the switches in proposed ultilevel inverter topology operate continuously to produce an output voltage. During this ode of inverter-i produce three-level output voltage and inverter- II produce two-level output voltage. The corresponding pole voltages of inverter-i and inverter-ii during this ode of are given in Table-1 along with their effective pole voltages. Thus a three phase induction otor attains four-level output voltages. So the cobined effective pole voltage of proposed ultilevel inverter produces fourlevel output voltage as shown in Fig. 7. The corresponding The advantage of proposed control strategy for proposed ultilevel inverter topology is that all the four levels of can be achieved in entire odulation index (fro 0 to1). 3. PROPOSED GPWM ALGORITHM Assue two set of instantaneous phase voltages as given in (4) and (5). an bn cn ax bx cx = = = = = = cos( ωt ) cos( ωt 120) cos( ωt 240) cos( ωt ) cos( ωt 120) cos( ωt 240) (4) (5)

4 Acta Electrotechnica et Inforatica, ol. 14, No. 1, As the potential O and O' are isolated, in proposed GPWM algorith, the odulating waves are generated by siply adding zero sequence voltage to the instantaneous phase voltages as given in (6). * in in zs, dc Where zs = (2a 0 1) a 0 ax + ( a 0 1) (7) 2 zs is known as zero sequence voltage. = +, i = a, b c (6) ax is the axiu of an, bn, cn and ax,x is the axiu value of ax, bx, cx in each sapling tie interval. For the generation of various PWM algoriths, the variation of the constant is shown in Table-2 and the corresponding odulating signals are shown in Fig. 8. Fro the Fig. 8, it can be observed that the SPWM has continuous odulating wavefor and hence gives continuous pulse pattern. Whereas, the odulating waves of discontinuous PWM (DPWM) algoriths clap to either positive dc or negative dc bus for a duration of 120 degrees in each fundaental cycle. Hence, the switching losses can be reduced by 33.33%. Table 2 a value for various PWM algoriths PWM algorith a o SPWM 0.5 DPWMMIN 0 DPWMMAX 1 DPWM0 ax + in < 0 then a0 ax + in 0 then a0 DPWM1 ax, x + in, x 0 then DPWM2 DPWM3 ax, x + in, x = 0 = 1 a < 0 then a 0 0 = 1 = 0 ax + in < 0 then a0 = 1 ax + in 0 then a0 = 0 ax, x + in, x < 0 then a0 = 1 ax, x + in, x 0 then a 0 = 0 4. SIMULATION RESULTS AND DISCUSSION The characteristics of ultilevel inverter topology with different PWM algoriths have been studied and analyzed in MATLAB/siulation environent for a three phase induction otor. The induction otor paraeters used in the analysis and inverter paraeters are given in Table-3. For the siulation studies, the switching frequency is taken as 3 khz. Hence, the sapling tie period (T) for is taken as 0.333s. The siulation studies have been carried out for four-level. Hence, to achieve four -level, for a sapling tie period of T inverter-i is switched for a period of (2T/3) and inverter-ii is switched for a period of (T/3). Moreover, when one inverter is switched other inverter is claped. The of inverters for various PWM algoriths is as shown in Table-4. The siulation results for various PWM algoriths for a four-level are shown in fro Fig. 9 to Fig. 15. Table 3 Paraeters and specifications of the Induction otor Rated speed 1500 RPM Rotor resistance 1.21Ω frequency 50HZ Inverter input 450 DC oltage Stator 1.57Ω Mutual 176H resistance inductance Stator inductance 183H Rotor inductance 183H Table 4 Operation of inverters for various PWM algoriths Type of PWM SPWM SPWM DPWMMIN Operation of Inverter-I in 2T/3 tie period switching in2t/3 period switching in2t/3 period claped for soe tie duration in 2 DPWMMAX switching in 2 Operation of Inverter-II in T/3 tie period switching in switching in switching in claped for soe tie duration in Reason odulating wavefor odulating wavefor As the odulating wave is claped to negative dc bus As the odulating wave is claped to positive dc bus Fig. 8 Modulating signals of different PWM algoriths DPWM0 DPWM1 DPWM2 DPWM3 claped for soe tie duration in 2 claped for soe tie duration in As the odulating wave is claped to both positive and negative dc bus

5 32 Generalized PWM Technique for Dual Inverter Fed Induction Motor Drive Fig. 9 oltage plots with SPWM algorith during four-level Fig. 11 oltage plots with DPWMMAX algorith during fourlevel Fig.10 oltage plots with DPWMMIN algorith during fourlevel Fig. 12 oltage plots with DPWM0 algorith during four-level

6 Acta Electrotechnica et Inforatica, ol. 14, No. 1, Fig. 13 oltage plots with DPWM1 algorith during four-level Fig. 15 oltage plots with DPWM3 algorith during four-level The haronic spectra of line voltages for various PWM algoriths are shown in fro Fig. 16 to Fig. 23 for four-level. Moreover, the haronic spectra line voltage for two-level and three-level with SPWM algorith is shown in Fig. 24 and Fig. 25. Fro the haronic spectra results, it can be observed that as the nuber of levels increases, the haronic distortion also decreases. Moreover, the proposed GPWM algorith gives all possible PWM algoriths with reduced coplexity. Also, it can be concluded that as the DPWM algoriths clap for a total period of 120 degrees in each fundaental cycle, the switching losses can be reduced 33.33%. Fig. 14 oltage plots with DPWM2 algorith during four-level Fig. 16 Haronic spectra of line voltage for SPWM algorith

7 34 Generalized PWM Technique for Dual Inverter Fed Induction Motor Drive Fig. 17 Haronic spectra of line voltage for SPWM algorith Fig. 21 Haronic spectra of line voltage for DPWM1 algorith Fig. 18 Haronic spectra of line voltage for DPWMMIN algorith Fig. 22 Haronic spectra of line voltage for DPWM2 algorith Fig. 19 Haronic spectra of line voltage for DPWMMAX algorith Fig. 23 Haronic spectra of line voltage for DPWM3 algorith Fig. 20 Haronic spectra of line voltage for DPWM0 algorith Fig. 24 Haronic spectra of line voltage for SPWM algorith for two-level.

8 Acta Electrotechnica et Inforatica, ol. 14, No. 1, Fig. 25 Haronic spectra of line voltage for SPWM algorith for three-level. 5. CONCLUSIONS The proposed GPWM algorith is very siple and is less coplex when copared to conventional continuous and discontinuous PWM algoriths. Fro the results it can be concluded that discontinuous PWM techniques reduce a total of 33% of switching losses when copared to continuous PWM algoriths. Moreover, the proposed circuit topology can generate two-level, three-level and four-level output voltages with reduced switching losses at all the odulation indices. As nuber of levels increases haronic content in the output voltage gets reduced. In view of perforance the proposed inverter topology is highly efficient at low voltage rating also. During faulty conditions of the drive the coplete otor drive can be operated with one set of inverter by isolating other inverter fro the. REFERENCES [1] MURPHY, J. M. D. EGAN, M. G.: A coparison of PWM strategies for inverter fed induction otors, IEEE trans. On Ind. Appl., vol. IA-19, issue. 3, pp , May, [2] HOLTZ, J.: Pulse Width odulation A survey, IEEE trans. industrial elec., ol. 39., pp [3] HOLTZ, J.: Pulsewidth odulation for electronic power conversion, Proc. IEEE, vol. 82, no. 8, pp , Aug [4] AN DER BROECK, H. W. SKUDELNY, H. C. STANKE, G.: Analysis and relisation of pulse width odulator based on voltage space vector, in Proc. IEEE IAS Annu eeting Denver, CO, 1986 pp [5] KIM, J. S. KUL, S.: A novel voltage odulation technique of Space ector PWM, in conf. Rec IPEC Yokohaa '95 pp [6] AN DER BROECK, H. W.: Analysis of the haronics in voltage fed inverter drives caused by PWM schees with discontinuous switching, in Conf. Rec. EPE 91, 1991, vol. 3, pp [7] CHUNG, D. W. KIM, J. S. SUL, S. K.: Unified oltage Modulation Technique for Real-Tie Three-Phase Power Conversion, IEEE Trans industrial appl. ol. 34, NO. 2, MARCH/APRIL [8] HAA, A. M. KERKMAN, R. J. LIPO, T. A.: A high perforance generalised discontinuous PWM algorithes, IEEE Trans Ind. Applicat ol: 34, no. 5 Sep/Oct 1998, pp [9] TEODORESCU, R. BEAABJERG, F. PEDERSEN, J. K. CENGELCI, E. SULISTIJO, S. WOO, B. ENJETI, P.: Multilevel converters A survey, in Proc. European Power Electronics Conf. (EPE 99), Lausanne, Switzerland, 1999, CD- ROM. [10] RODRÍGUEZ, J. LAI, J. S.: Multilevel Inverters: A Survey of Topologies Controls and Applications, IEEE Trans. Ind. Ele., ol. 49, no. 4, pp , Aug [11] REDDY, T. B. ISHWARYA, K. YSHNAI, D. HANEESHA, K.: Generalized Scalar PWM Algorith for Three level diode claped inverter fed Induction otor Drive with Reduced coplexity, International conf. on APCET, Aug, 2012, India. [12] SOMASEKHAR,. T. GOPAKUMAR, K.: Three-level inverter configuration cascading twotwolevel inverters, IEE Proc.-Eleclr. Power Appl, ol. 150, No. 3, May [13] SHIAKUMAR, E. G. GOPAKUMAR, K. SINHA, S. K. PITTET, A. RANGANATHAN,. T.: Space vector control of dual inverter fed openend winding induction otor drive, EPE J., vol. 12, no. 1, pp. 9 18, Feb [14] SOMASEKHAR,. T. GOPAKUMAR, K. BAIJU, M. R. MOHAPATRA, K. K.: A Multilevel Inverter syste for an Induction Motor with Openend Winding, in Proceedings of.ieee IECON 2002 pp [15] SOMASEKHAR,. T. GOPAKUMAR, K. BAIJU, M. R. MOHAPATRAAND, K. K. UMANAND, L.: A Multilevel Inverter Syste for an Induction Motor With Open-End Windings, IEEE trans, onindustrial elec. ol. 52, NO. 3, June Received Deceber 6, 2013, accepted March 17, 2014 BIOGRAPHIES M. Harsha ardhan Reddy received B.Tech degree fro Rajeev Gandhi Meorial college of Engineering and Technology, Nandyal, Andhra Pradesh in He received M.Tech degree in power electronics and drives fro Karunya University, Coibatore in Currently, he is with G. Pulla Reddy Engineering college, kurnool, as an Assistant Professor. His areas of interests are power electronic control of drives.

9 36 Generalized PWM Technique for Dual Inverter Fed Induction Motor Drive Dr. T. Brahananda Reddy graduated fro Sri Krishna Devaraya University, Anantapur in the year He received M.E degree fro Osania University, Hyderabad, India in the year 2003 and Ph.D fro J.N.T.University, Hyderabad in the year He is presently working as Professor and Head of Electrical and Electronics Engineering Departent, G. Pulla Reddy Engineering College (Autonoous), Kurnool, India. He presented ore than 100 research papers in various national and international conferences and journals. His research area includes PWM techniques, DC to AC converters and control of electrical drives. B.Ravindranath Reddy obtained his B.Tech degree in Electrical & Electronics Engineering fro the J.N.T.U. College of Engg., Anantapur in the year He obtained his M.Tech degree in Energy Systes fro IPGSR of J.N.T.University Hyderabad in the year He obtained his doctoral degree fro JNTUA, Anantapur University in the field of Electrical Power Systes. He is presently working as Executive Engineer in JNTUH. He has ore than 20 research papers. His areas of interests are Power Systes, High oltage Engineering and Control Systes. His research area includes Siulation studies on Transients of different power syste equipent. M. Surya Kalavathi obtained her B.Tech degree fro S..University in the year 1988 and M.Tech degree fro sae university in the year Obtained her doctoral degree fro JNTU, Hyderabad and post doctoral fro CMU, USA. She is presently working as professor in JNTU college of Engg. Hyderabad. She has published ore than 40 research papers. Her research area includes siulation studies on transients of different power syste equipent.