RT9618/A. Synchronous-Rectified Buck MOSFET Drivers. Features. General Description. Applications

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1 Synchronous-Rectified Buck MOSFET Drivers General Description The are high frequency, dual MOSFET drivers specifically designed to drive two power N-MOSFETs in a synchronous-rectified buck converter topology. The drivers combined with Richtek s series of Multi-Phase Buck controller form a complete core-voltage regulator solution for advanced micro-processors. The drive both the lower/upper gate in a synchronous-rectifier bridge with 12V. This drive-voltage flexibility provides the advantage of optimizing applications involving trade-offs between switching losses and conduction losses. RT9618A has longer / deadtime which can drive the MOSFETs with large gate RC value, avoiding the shoot-through phenomenon. RT9618 is targeted to drive low gate RC MOSFETs and performs better efficiency. The output drivers in the can efficiently switch power MOSFETs at frequency up to 500kHz. Switching frequency above 500kHz has to take into account the thermal dissipation of the packages. are capable to drive a 3nF load with a 30ns rise time. implements bootstrapping on the upper gate with an external capacitor and an embedded diode. This reduces implementation complexity and allows the use of higher performance, cost effective N-MOSFETs. Adaptive shootthrough protection is integrated to prevent both MOSFETs from conducting simultaneously. Pin Configurations (TOP VEW) VCC SOP-8 PGND Features Drives Two N-MOSFETs Adaptive Shoot-Through Protection Embedded Boot Strapped Diode Support High Switching Frequency Fast Output Rise Time Small SOP-8 and 8-Lead WDFN Package Tri-State nput for Bridge Shutdown Supply Under Voltage Protection Upper MOSFET Direct Shorted Protection RoHS Compliant and 0% Lead (Pb)-Free Applications Core Voltage Supplies for Desktop, Motherboard CPU High Frequency Low Profile DC-DC Converters High Current Low Voltage DC-DC Converters Ordering nformation Package Type S : SOP-8 QW : WDFN-8L 3x3 Lead Plating System P : Pb Free G : Green (Halogen Free and Pb Free) Long Dead Time Short Dead Time Note : Richtek products are : RoHS compliant and compatible with the current requirements of PC/JEDEC J-STD-020. Suitable for use in SnPb or Pb-free soldering processes. Marking nformation For marking information, contact our sales representative directly or through a Richtek distributor located in your area. VCC GND PGND 5 WDFN-8L 3x3 1

2 Typical Application Circuit L1 ATX_12V 2.2uH C8 C9 C C11 C12 C13 C14 uf uf 00uF 00uF 00uF uf uf V N D1 R2 1 C2 ATX_12V R1 1 4 VCC C1 5V 3 2 PGND R3 2.2 R4 0 Q1 Q2 L2 1uH R5 2.2 C3 3.3nF V CORE C4 C5 C6 C7 2200uF 2200uF uf uf Functional Pin Description Pin No. Pin Name Pin Function S QW 1 1 Floating bootstrap supply pin for upper gate drive. 2 2 nput signal for controlling the driver. 3 3 Output Disable. When low, both and are driven low and the normal operation is disabled. 4 4 VCC 12V Supply Voltage. 5 5 Lower Gate Drive Output. Connected to gate of low-side power N-MOSFET. 6 6 PGND Common Ground. 7 7 Connected this pin to the source of the high-side MOSFET and the drain of the low-side MOSFET. 8 8 Upper Gate Drive Output. Connected to gate of high-side power N-MOSFET (Exposed Pad) GND The exposed pad must be soldered to a large PCB and connected to GND for maximum power dissipation. 2

3 Function Block Diagram VCC nternal 5V POR R R nput Disable Shoot-Through Protection Turn Off Detect VCC Shoot-Through Protection PGND Timing Diagram t pdl 90% 2V t pdl 2V 2V 90% 2V t pdh t pdh 3

4 Absolute Maximum Ratings (Note 1) Supply Voltage, V CC V to 15V to V to 15V to GND DC V to V CC 15V < 200ns V to 42V to GND DC V to 15V < 200ns V to 30V DC GND 0.3V to V CC 0.3V < 200ns V to V CC 0.3V V 0.3V to V 0.3V < 200ns V 2V to V 0.3V nput Voltage GND 0.3V to 7V GND 0.3V to 7V Power Dissipation, P T A = 25 C SOP W WDFN-8L 3x W Package Thermal Resistance (Note 2) SOP-8, θ JA C/W WDFN-8L 3x3, θ JA C/W WDFN-8L 3x3, θ JC C/W Lead Temperature (Soldering, sec.) C Storage Temperature Range C to 150 C ESD Susceptibility (Note 3) HBM (Human Body Mode) kV MM (Machine Mode) V Recommended Operating Conditions (Note 4) Supply Voltage, V CC V ±% Junction Temperature Range C to 125 C Ambient Temperature Range C to 70 C Electrical Characteristics (Recommended Operating Conditions, T A = 25 C unless otherwise specified) Parameter Symbol Test Conditions Min Typ Max Units V CC Supply Voltage Power Supply Voltage V CC V V CC Supply Current Power Supply Current VCC V = 12V, = 0V ma Power-On Reset POR Threshold V VCCrth V CC Rising V 4 To be continued

5 Parameter Symbol Test Conditions Min Typ Max Units Hysteresis V VCChys V nput Maximum nput Current = 0V or 5V μa Floating Voltage V fl V CC = 12V V Rising Threshold V rth V Falling Threshold V fth V Output Disable nput Rising Threshold V rth V Hysteresis V hys V Timing Rise Time t r V CC = 12V, 3nF load ns Fall Time t f V CC = 12V, 3nF load ns Rise Time t r V CC = 12V, 3nF load ns Fall Time t f V CC = 12V, 3nF load ns Propagation Delay Output RT t pdh V RT9618A V = 12V See Timing Diagram t pdl t pdh See Timing Diagram t pdl Drive Source R sr V V = 12V Ω Drive Sink R sk V V = 12V Ω Drive Source R sr V CC = 12V Ω Drive Sink R sk V CC = 12V Ω Note 1. Stresses listed as the above Absolute Maximum Ratings may cause permanent damage to the device. These are for stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. Note 2. θja is measured in the natural convection at TA = 25 C on a low effective thermal conductivity test board of JEDEC 51-3 thermal measurement standard. The case point of θjc is on the expose pad for the package. Note 3. Devices are ESD sensitive. Handling precaution is recommended. Note 4. The device is not guaranteed to function outside its operating conditions. ns 5

6 Typical Operating Characteristics High side MOSFET : FR3707Z x 1, Low side MOSFET : LR8113 x 2 Drive Enable Drive Disable (2V/Div) (20V/Div) (2V/Div) (20V/Div) (V/Div) (V/Div) (V/Div) No Load (V/Div) No Load Time (1μs/Div) Time (1μs/Div) to Drive Waveform to Drive Waveform (20V/Div) (20V/Div) (V/Div) (V/Div) (V/Div) No Load (V/Div) No Load Time (25ns/Div) Time (25ns/Div) Dead Time Dead Time 30A/CH 30A/CH Time (20ns/Div) Time (20ns/Div) 6

7 Dead Time Dead Time No Load No Load Time (20ns/Div) Time (20ns/Div) OUT = 119A to 24A Short Pulse 0.06 nternal Diode -V Curve 0.05 Current (A) Time (20ns/Div) Voltage (V) 7

8 Application nformation The are designed to drive both high side and low side N-MOSFET through externally input control signal. t has power-on protection function which held and low before VCC up across the rising threshold voltage. After the initialization, the signal takes the control. The rising signal first forces the signal turns low then signal is allowed to go high just after a non-overlapping time to avoid shootthrough current. The falling of signal first forces to go low. When and signal reach a predetermined low level, signal is allowed to turn high. The signal is acted as "High" if above the rising threshold and acted as "Low" if below the falling threshold. Any signal level enters and remains within the shutdown window is considered as "tri-state", the output drivers are disabled and both MOSFET gates are pulled and held low. f left the signal floating, the pin will be kept around 2.4V by the internal divider and provide the controller with a recognizable level. pin will also shutdown the bridge of tied to GND. The typically operate at frequency of 200kHz to 500kHz. t shall be noted that to place a 1N4148 or schottky diode between the VCC and pin as shown in the typical application circuit for ligher efficiency. Non-overlap Control To prevent the overlap of the gate drives during the turn low and the turn high, the non-overlap circuit monitors the voltages at the node and high side gate drive (-). When the input signal goes low, begins to turn low (after propagation delay). Before can turn high, the non-overlap protection circuit ensures that the monitored voltages have gone below 1.2V. Once the monitored voltages fall below 1.2V, begins to turn high. For short pulse condtion, if the pin had not gone high after turns low, the has to wait for 200ns before turn high. By waiting for the voltages of the pin and high side gate drive to fall below 1.2V, the non-overlap protection circuit ensures that is low before turns high. Also to prevent the overlap of the gate drives during turn low and turn high, the non-overlap circuit monitors the voltage. When go below 1.2V, is allowed to go high. Driving Power MOSFETs The DC input impedance of the power MOSFET is extremely high. When V gs at 12V (or 5V), the gate draws the current only few nano-amperes. Thus once the gate has been driven up to "ON" level, the current could be negligible. However, the capacitance at the gate to source terminal should be considered. t requires relatively large currents to drive the gate up and down 12V (or 5V) rapidly. t also required to switch drain current on and off with the required speed. The required gate drive currents are calculated as follows. V N V g1 V g2 d1 Cgd1 gd1 g1 D1 g1 gs1 g2 V 12V 12V s1 Cgs1 g2 gd2 gs2 Cgd2 Figure 1. Equivalent Circuit and Associated Waveforms n Figure 1, the current g1 and g2 are required to move the gate up to 12V. The operation consists of charging C gd and C gs. C gs1 and C gs2 are the capacitances from gate to source of the high side and the low side power MOSFETs, respectively. n general data sheets, the C gs is referred as "C iss " which is the input capacitance. C gd1 and C gd2 are the capacitances from gate to drain of the high side and Cgs2 d2 s2 L D2 t t V OUT GND 8

9 the low side power MOSFETs, respectively and referred to the data sheets as "C rss " the reverse transfer capacitance. For example, t r1 and tr2 are the rising time of the high side and the low side power MOSFETs respectively, the required current gs1 and gs2, are showed below : gs1 gs1 = Cgs1 = (1) dt tr1 Before driving the gate of the high side MOSFET up to 12V (or 5V), the low side MOSFET has to be off; and the high side MOSFET is turned off before the low side is turned on. From Figure 1, the body diode "D 2 " had been turned on before high side MOSFETs turned on. dv 12V gd1 Cgd1 Cgd1 dt tr1 = = (3) Before the low side MOSFET is turned on, the C gd2 have been charged to V N. Thus, as C gd2 reverses its polarity and g 2 is charged up to 12V, the required current is gd2 = C gd2 dv = C dt gd2 Vi 12V t t is helpful to calculate these currents in a typical case. Assume a synchronous rectified buck converter, input voltage V N = 12V, Vg1 = V g2 = 12V. The high side MOSFET is PHB83N03LT whose C iss = 1660pF, C rss = 380pF, and t r = 14ns. The low side MOSFET is PHB95N03LT whose C iss = 2200pF, C rss = 500pF and t r = 30ns, from the equation (1) and (2) we can obtain gs2 gs1 gs2 = C gs1 dvg1 dvg2 C = dt = r2 12 = 0.88 (A) (4) -12 = = (A) (5) C gs1 tr (2) (6) the total current required from the gate driving source is g1 g2 = = gs1 gs2 gd1 gd2 = ( ) = = ( ) = 1.28 (A) (A) By a similar calculation, we can also get the sink current required from the turned off MOSFET. Select the Bootstrap Capacitor Figure 2 shows part of the bootstrap circuit of. The V CB (the voltage difference between and on ) provides a voltage to the gate of the high side power MOSFET. This supply needs to be ensured that the MOSFET can be driven. For this, the capacitance C B has to be selected properly. t is determined by following constraints. V CC V CC 1N4148 PGND V N C B V CB - (9) () Figure 2. Part of Bootstrap Circuit of n practice, a low value capacitor C B will lead the overcharging that could damage the C. Therefore to minimize the risk of overcharging and reducing the ripple on V CB, the bootstrap capacitor should not be smaller than 0.1μF, and the larger the better. n general design, using can provide better performance. At least one low-esr capacitor should be used to provide good local de-coupling. Here, to adopt either a ceramic or tantalum capacitor is suitable. from equation. (3) and (4) Power Dissipation gd1 gd2-12 = = (A) 500 (12 12) = = (A) (7) (8) For not exceeding the maximum allowable power dissipation to drive the C beyond the maximum recommended operating junction temperature of 125 C, it is necessary to calculate power dissipation appro-priately. 9

10 This dissipation is a function of switching frequency and total gate charge of the selected MOSFET. Figure 3 shows the power dissipation test circuit. C L and CU are the and load capacitors, respectively. The bootstrap capacitor value is V V 1N4148 VCC C PGND Figure 3. Test Circuit C L 3nF 2N V Figure 4 shows the power dissipation of the as a function of frequency and load capacitance. The value of the C U and C L are the same and the frequency is varied from 0kHz to 1MHz. Power Dissipation vs. Frequency CU=CL=3nF 2N7002 C U 3nF 20 T J = (160 C/W x 0mW) 25 C = 41 C (11) where the ambient temperature is 25 C. The method to improve the thermal transfer is to increase the PCB copper area around the first. Then, adding a ground pad under C to transfer the heat to the peripheral of the board. Layout Consideration Figure 5 shows the schematic circuit of a two-phase synchronous buck converter to implement the. The converter operates from 5V to 12V of V N. When layout the PCB, it should be very careful. The powercircuit section is the most critical one. f not configured properly, it will generate a large amount of EM. The junction of Q1, Q2, L2 should be very close. Next, the trace from, and should also be short to decrease the noise of the driver output signals. signals from the junction of the power MOSFET, carrying the large gate drive current pulses, should be as heavy as the gate drive trace. The bypass capacitor C4 should be connected to PGND directly. Furthermore, the bootstrap capacitors (C B ) should always be placed as close to the pins of the C as possible. Power Dissipation (mw) CU=CL=2nF CU=CL=1nF Frequency (khz) Figure 4. Power Dissipation vs. Frequency V N 12V V CORE L1 1.2uH C3 1500uF C1 00uF Q1 L2 2uH Q2 C2 PHB83N03LT PHB95N03LT CB D1 VCC 4 PGND 6 12V 2 Figure 5. Two-Phase Synchronous Buck Converter Circuit 3 R1 C4 5V The operating junction temperature can be calculated from the power dissipation curves (Figure 4). Assume V CC =12V, operating frequency is 200kHz and the C U =C L =1nF which emulate the input capacitances of the high side and low side power MOSFETs. From Figure 4, the power dissipation is 0mW. For, the SOP-8 package thermal resistance θ JA is 160 C/W, the operating junction temperature is calculated as :

11 Outline Dimension A H M J B F C D Symbol Dimensions n Millimeters Dimensions n nches Min Max Min Max A B C D F H J M Lead SOP Plastic Package 11

12 D D2 L E E2 1 SEE DETAL A e b A A1 A3 DETAL A Pin #1 D and Tie Bar Mark Options Note : The configuration of the Pin #1 identifier is optional, but must be located within the zone indicated. Symbol Dimensions n Millimeters Dimensions n nches Min Max Min Max A A A b D D E E e L W-Type 8L DFN 3x3 Package, 0.5mm Lead Pitch Richtek Technology Corporation Headquarter 5F, No. 20, Taiyuen Street, Chupei City Hsinchu, Taiwan, R.O.C. Tel: (8863) Fax: (8863) Richtek Technology Corporation Taipei Office (Marketing) 5F, No. 95, Minchiuan Road, Hsintien City Taipei County, Taiwan, R.O.C. Tel: (8862) Fax: (8862) marketing@richtek.com nformation that is provided by Richtek Technology Corporation is believed to be accurate and reliable. Richtek reserves the right to make any change in circuit design, specification or other related things if necessary without notice at any time. No third party intellectual property infringement of the applications should be guaranteed by users when integrating Richtek products into any application. No legal responsibility for any said applications is assumed by Richtek. 12