Design Optimization of a Five-level Active NPC Inverter

Transcription

1 Keywords Design Optiizati of a Five-level Active NC nverter Yugo Kashihara, and Jun-ichi toh, Nagaoka University of Technology 63- Kaitoioka-cho Nagaoka City Niigata,Japan Tel.: +8 / (58) Fax: +8 / (58) itoh@vos.nagaokaut.ac.jp URL: Multilevel cverter, Design, hotovoltaic. Abstract This paper discusses the optiizati designing ethod for a 5-level ANC inverter. The point of the atheatical expressi is to observe the losses of a cverter based the study of the device cditi. Selecti of the capacitor is also discussed accordingly based the design ethod. The perforance of the 5-level ANC inverter is copared with a cvential -level inverter. The validity of the proposed calculati ethod for the power loss is cfired with the experiental results. The 5-level ANC inverter can achieve higher efficiency than the -level inverter.. ntroducti Applicatis of the ultilevel cverters are actively researched recently [-3]. Coparing the ultilevel cverters to the cvential -level cverters, ultilevel cverters show better advantages, for exaple a ultilevel cverter can reduce the voltage stress of a switching device to /(n-) of the DC input voltage and also reduce the haric copent of the output voltage. As a result, ultilevel cverters can use switching devices, which are high speed switching and low voltage rating. Multilevel cverters are possible to obtain higher efficiency than the cvential cverters. n general, the ultilevel cverters are applied to the ediu voltage applicati such as the power cverter for large power otor drive and also for the power transissi line. Recently, low voltage applicatis also have been studied to use ultilevel cverter such as the uninterrupted power supply (US) and the power cverter for photo voltaic cell () [3]. There are two cvential ultilevel topologies; the neutral point claped (NC) type and the flying capacitor (FC) type []. The NC type outputs the voltage level fro the neutral point voltage which is claped by using diodes. However the nuber of switching devices increases in proportial to the voltage level. The FC type outputs the voltage level fro the DC link voltage based the flying capacitor voltage. However, FC type needs ore capacitors as the voltage level increases. The active neutral point claped (ANC) which is e of the ultilevel topology has been proposed in Ref []. The ANC type is a new topology that cobines the NC and FC type into e cverter. Copared to the cvential NC and FC type cverters, the ANC uses lesser switching devices. Therefore, the ANC type is low in ter of cost and further achieves higher efficiency than the cvential NC and FC type. Selecti criteria of switching devices for ulti-level cverter are necessary to deterine the cverter obtains high efficiency in low voltage applicatis. Loss analysis by using siulator is a siple ethod to study the losses ag the ultilevel cverter topologies under a sae device specificati. However the loss estiati by siulati is not useful to csider the optiizati of design because hundreds of siulatis are required under different cditis. This paper establishes an optiizati designing ethod for a 5-level ANC inverter. The point of the atheatical expressi is to observe the losses of a cverter based the study of the device

2 cditi. Selecti of the capacitor is also discussed accordingly based the design ethod. n this paper, the 5-level ANC inverter is designed to apply in a syste. The perforance of the 5-level ANC inverter is then copared with the cvential -level inverter. The validity of the proposed calculati results for the power loss is cfired with the experiental results. The 5-level ANC inverter is shown able to achieve higher efficiency than the -level inverter.. A Five-Level Cverter Topology A. ANC circuit Figure shows the single leg diagra of a five-level ANC inverter, which is cstructed by eight switches and three capacitors. The ANC cverter has two advantages; first, the ANC inverter is able to obtain high efficiency because of the low switching loss. There are two switching frequencies in an ANC cverter. n the cvential ulti-level cverter topology, the switching frequency of all the switching devices is sae to the carrier frequency, the other hand, in an ANC, the switching frequency of the Cell switching device in Fig. is sae to the output frequency (5Hz) and ly Cell switching devices use the carrier frequency. As a result, the switching loss is greatly reduced. t should be noted that the voltage rating of the switching devices in Cell are required to equal to half of the DC link voltage. The secd advantage is the ANC cverter can ctrol the flying capacitor voltage C and therefore a voltage balance circuit is not necessary and results the size of the circuit is copact and sall. Table shows the switching pattern of the five-level ANC cverter and the flying capacitor voltage. The five-level ANC inverter outputs five kind of voltage levels which are /E dc, /4E dc,, +/4E dc, and +/4E dc. These five kind of voltage levels are given by suing the flying capacitor voltage and the DC soothing capacitor voltage. There are eight switching pattern in the five-level ANC inverter. When the switching pattern is +/4E dc or -/4E dc, the flying capacitor is in charge ode or discharge ode. TABLE Switching pattern and flying capacitor voltage. Fig.. Single phase 5-level ANC inverter circuit topology. B. Ctrol strategy Figure shows the gate signal wavefor of the five-level ANC inverter. The gate signals of Cell switches are generated by phase shift carrier-based WM strategy. These gate signals are generated by coparing to the output voltage coand with two carriers which the phase is reversed to each other. The duty ratio coand D ref for Cell is given by; D ref asin... (), D ref a sin...(), where a is the odulati index and is the reference phase angle.

3 When the polarity of the output voltage coand is positive, the gate signals of S 5 and S 7 are turned. When the polarity of voltage coand is negative, the gate signals of S 6 and S 8 are turned. This ctrol ethod can balance the flying capacitor voltage autoatically, by choosing the discharge and charge odes according to the cycle of carrier frequency.. Matheatical Expressi of ower Loss This chapter explains the power loss expressi of the five-level ANC inverter. The ANC inverter is assued to operate in an ideal cditi. The power loss of the ANC inverter is calculated under two ideal cditis, that is no load ripple current and no voltage ripple in capacitors. Then, the power loss of the ANC inverter is given by Loss Cell Cell FC C DCSC...(3), where Loss is the total loss (W), Cell is the Cell loss (W), Cell is the Cell loss (W), FC is the flying capacitor loss (W) and DCSC is the DC soothing capacitor loss (W). Furtherore, the power loss csists of the switching loss and the cducti loss, which are generated at turn and off, fro the forward voltage drop of a switching device, respectively. A. ower loss of Cell ) Cducti loss The cducti loss is separated into two, naely the switch side loss and FWD side loss. We assue that the positive current flows into the switch side and the negative current flows into the FWD side. n additi, if the switching device of the ANC cverter is MOSFET, both the positive current and negative current flow into the switch side due to low -resistance. The average value of the cducti loss is calculated fro the -voltage and the switch current and the duty ratio coand D ref which can be given by dx...(4), r v...(5), Switch visw v isw sin Fig.. Gate signals. Dref...(6), where v is the -voltage, r is the -resistance (), is the current flows through the switch (A), v is the drop voltage () when equals to approxiately A, is the peak phase current, a is the odulati index, is the power factor. The -voltage v in the equati (4) and the equati (5) is expressed for the GBT. The -voltage

4 occurs in the switching device fro -resistance and p-n juncti, which is expressed in the equati (5). On the other hand, if the switching device of the ANC cverter is MOSFET, v = in the equati (5). The cvential loss _sw in the switch side are expressed in the equati (7) fro the equati (4), (5), (6). On _ sw v v cos r 8 sin 4 r ar 3 cos av 4 cos (7) On the other hand, the cvential loss _FWD in the switch side are given by On _ FWD v v cos r 8 sin r 4 4 r ar 3 cos av 4 cos (8). ) Switching loss We assue that the switching loss of the switches in Cell is proportial to the applied voltage and current. Therefore, the switching loss of the Cell depends the current flows through the switches and the nuber of switching. The Cell switching loss sw is given by Edc sw e e off f c 4...(9), Edcd d where E dc is the input voltage (), e is the turn- energy (J) per switching at datasheet, e off is the turn-off energy (J) per switching at datasheet, E dcd is the voltage () at the easureent cditi of switching loss at datasheet, d is the current (A) at the easureent cditi of switching loss at datasheet and f c is the carrier frequency (Hz). The recovery loss Rec in Cell is given by Edc Rec err fc...(), 4 Edcd d where e rr is the recovery energy (J) per switching fro the datasheet. B. ower Loss of Cell ) Cducti loss The cducti loss in Cell is obtained by the sae forula that is used to calculate the cducti loss in Cell. However, the current flows into the Cell switches are different fro the Cell because of the following two cditis: S 5 and S 7 are turn- when the output voltage coand is positive and S 6 and S 8 are turn- when the output voltage coand is negative. i swa is the switch current flows to S 5 and S 7 and i swb is the switch current flows to S 5 and S 7, which are given by i sw sin Dref i swa (), i swb i sw sin Dref (). Therefore, the cducti loss _swa is calculated by substituting equati () into equati (4). _swa is given by On _ swa ar cos cos av cos sin cos (3). 6 3 The cducti loss of the FWD side of S 5 and S 7 are given by a8 4 sin 3v sin 3v cos On _ FWD A r (4). Likewise, the cducti loss for the switch side of the S 6 and S 8 is given by (5) and the cducti loss for the FWD side of the S 6 and S 8 is given by (6) _ swb v cos r sin av cos sin cos 4 (5), ar cos cos 6 3

5 _ FWDB r sin v v cos av sin cos ar cos cos (6), 4 ) Switching loss The switching loss in the Cell is depending the output frequency (5Hz). As a result, the switching loss in the Cell is lower than the switching loss in the Cell, which is nearly equal to zero and therefore the switching loss can be disregarded.. araeter Design of The Capacitor A. Flying capacitor ) Design of the capacitor The capacitance of the flying capacitor C is calculated by the capacitor current, the ripple voltage and the tie integrati of the charge period or discharge period. The flying capacitor voltage is repeating to charge and discharge in e carrier cycle. Thus, the tie integrati of the charge period and the discharge period is equivalent. Therefore, the capacitance of C is given by T Edc CFC 8...(7), FC Where C is the ripple voltage of the flying capacitor, DC is the DC link voltage, is the axiu value of output voltage, and T is the reciprocal of carrier frequency. ) Calculati ethod of the flying capacitor loss The cducti loss FC occurs in the flying capacitor is based the equivalent series resistance (ESR) []. The cducti loss FC is given by FC rs _ FC RFC...(8), where rs_fc is the rs value of the flying capacitor current (A) and R FC is the ESR value of the flying capacitor (). The ripple current of the capacitors are liited as a peritted value in ters of the lifetie of the capacitor. Thus, rs_fc is an iportant factor for selecting the capacitor. The rs value of the ripple current at switching frequency is a n-linear value. Therefore, the calculati as for a general soluti is difficult and the coplexity is ipractical. The current of the flying capacitor is a functi for the output power factor and odulati index. These values are also n-diensial. The rs value of the flying capacitor value is given by equati (9) using the flying capacitor current coefficient K fc. The flying capacitor current coefficient K fc is calculated fro the noralized siulati. K rs _ FC cf...(9) Figure 4 shows the cversi of the flying capacitor current coefficient K fc. K fc is defined by the output phase factor and odulati index. The axiu value of K CF is.65 when the odulati index in figure 5 is.5 to.6. The ESR R fc of the flying capacitor is given by R FC tan fc FC F... (), fn where tan is the tangent of loss angle. Tan in the equati () is the noralized value at Hz. Thus, rs_fc and R FC at the switching frequency are calculated by using the frequency correcti coefficient F fn. B. DC soothing capacitor ) Design of the capacitor The DC soothing capacitors are cnected to the DC link voltage in parallel because of the ANC inverter uses DC neutral point voltage. The capacitance of DC soothing capacitor C and C 3 are calculated by the voltage ripple and the DC soothing capacitor current based DC neutral point voltage fluctuati. The capacitance of DC soothing capacitor C and C 3 is given by 3 3 C...() cndc where cn is the axiu voltage ripple of C. ) Calculati loss of the DC soothing capacitor The calculati for the DC soothing capacitor loss is obtained by the sae forula that is used to calculate the flying capacitor loss. The DC soothing capacitor loss is given by DCSC rs _ CDSC RDCSC...(), 6 3

6 K rs _ CDSC cdc...(3), R DCSC tan fc DCSC F... (4), fn where rs_cdsc is the rs value of the ripple current flows through the DC soothing capacitor (A) and R CDC is the ESR of the DC soothing capacitor () and K CDC is the DC capacitor current coefficient K cdc. Figure 5 shows the current coefficient of the DC soothing capacitor. K cdc is calculated by the noralized siulati. Figure 5 indicates that the axiu value of K cdc becoes.46 at a=.6. n additi, the ain copent of the DC soothing capacitor is the switching frequency copent and the triple copent of output frequency. When the power factor is, the rs value rs_cdsc of the ripple current flows through the DC soothing capacitor can be expressed by equati (3). n additi, the rs value rs_cdsc3rd of the triple copent of output frequency is given by rs _ CDSC3rd a...(5) Fig.3. Current coefficient of flying capacitor. Fig.4. Current coefficient of DC soothing capacitor. C. The volue of the capacitor This chapter explains the calculati of the capacitor volue. There are two capacitors which are the flying capacitor and DC soothing capacitor in the ANC inverter. Thus, the capacitors volue is calculated based the fil capacitors and electrolytic capacitors that are available in the arketed [5]. ) The fil capacitor The volue of the fil capacitor is proportial to the energy is stored in the capacitor. The volue CE of the fil capacitor is given by CF C FU CF O...(6), where - CF is the proportiality factor between the energy and the volue, C F is the capacity of the fil capacitor and U O is the applied volue of the fil capacitor. ) The electrolytic capacitor The volue of the electrolytic capacitor is proportial to the rs value of the ripple current of the electrolytic capacitor. The volue CE of the electrolytic capacitor is given by CE CE C, RMS...(7), where - CE is the proportiality factor between the rs value of the ripple current and the volue, and C,RMS is the rs value of the ripple current of the electrolytic capacitor. D. The selecti ethod of the capacitor The capacitor has to satisfy these factors, which are the capacity, the rated voltage and the allowed ripple current. Figure 5 shows the design flowchart for the capacitor. n figure 8, rip is the designed ripple current, ol is the deterined capacitor volue, rip_data is the ripple current of the datasheet, ol _data is the capacitor volue of the datasheet, and C n is the capacity of the datasheet. The capacitor can be selected by the design produce flowchart. The specificatis first need to decide are following; the voltage ripple n of the capacitor, the input voltage in, the output voltage out and axiu output

7 current peak. Firstly, the switching frequency is deterined by the design specificatis. Secdly, the capacity C n and the ripple current rip is calculated based the specificatis. The capacity C n is calculated by equati (7) and equati (). The rated voltage is two-thirds of the applied voltage of the capacitor in the datasheet. The ripple current rip is calculated by equati (9) and equati (3). The capacitor which satisfies the designed paraeter showed be. Fig.5.Design produce flowchart. E. The design ethod of the inductor The applicati of the 5-level ANC inverter in this paper is proposed to apply in a syste [6]. This chapter explains the design ethod of the utility interacti inductor. This utility interacti inductor is for suppressi of the output ripple current. The utility interacti inductor L ANC is given by dc 3 LANC T E 3...(8), dc where is the ripple current. The volue of the inductor is calculated by the Area roduct. The volue of the inductor is given by 3 4 W L K...(9), Ku BJ w where K is the cstant value which is deterined by figure of the core, K u is the window utilizati factor, J w is the current density, B is the flux density. F. The design ethod of heatsink The perforance of the heatsink is discussed based the Cooling Syste erforance ndex (CS) [5]. The CS is an expressed value of the theral resistance at per unit volue. The larger the volue of the CS, the large is the cooling capacity per unit volue will be. The CS is given by CS...(3), Rth where R th is the theral resistance of the heatsink, o is the volue of the heatsink. n additi, R th is given by T j Ta Rth f a Rth f s...(3), l where T j is the juncti teperature of the switching device, T a is the abient teperature, l is evoluti loss.. Experiental erificati Figure 8 shows the operati wavefors for the five-level ANC inverter. The input voltage is 83, the output voltage is 4, 5 Hz, the output power is kw (rating), the flying capacitor voltage coand is set to 7 and the carrier frequency is khz. The paraeters of the devices are following (S-S4:RF4668pBF (R), S5-S6:XFB7N3 (XYS), C:LGUWMELA (Nichic), and C-3:FXAG47 (Hitachi)) referring to datasheets in [7-]. The output current shows a perfect sinusoidal wavefor without distorti. n additi, the flying capacitor voltage

8 agrees with the voltage coand, which is approxiately 7. Furtherore, a five-step wavefor is shown at the output voltage of the ANC inverter. Figure 9 shows the efficiency of the five-level ANC inverter. The axiu efficiency is 98.9% at a.45 kw load. The Five-level ANC inverter can obtain efficiency of over 98% in wide load cditis. Figure shows the loss of the five-level ANC inverter fro the theoretical calculati and experiental results. The axiu error of the theoretical value and experiental value is.9w at.45 kw load. The loss estiati results are well agreed with that of the experiental results. Figure shows the switching loss analysis of the five-level ANC inverter based the theoretical calculati. n the five-level ANC inverter, the ajor loss is doinant by the cducti loss. n order to achieve high efficiency, the switching devices which are featuring the low -resistance or low -voltage are selected. n the devices selecti, focus should be the cducti loss, because the switching loss in the Cell is very low. Note that there is trade off relatiship between the switching speed and -resistance in the power device. That is, the switching device in the Cell should be designed with a low -resistance even though the switching speed becoes slow. Fig.6 Experiental wavefor. Fig.7 Efficiency of a five- level ANC inverter. Fig.8 Loss analysis coparis between theoretical and experiental. Fig.9. Loss analysis.. The Design Optiizati of the 5-Level ANC nverter for a syste This chapter discusses the design optiizati of the 5-level ANC inverter for a syste. First, The inverter is designed by using the paraeter design ethod of the 5-level ANC inverter. Secdary, The perforance of the 5-level ANC inverter is copared with the cvential -level inverter. Table shows the specificati of the cverter. The input voltage is 35, the output voltage is, the rated power is 4 kw, the ripple voltage of the flying capacitor is 3%, the ripple voltage of the DC soothing capacitor is 5%. The CS of the heatsink is. Table shows the selected devices for the 5-level ANC inverter and -level inverter. Table shows the selected device paraeters for the 5-level ANC inverter and -level inverter. The switching device is deterined by the rating voltage and allowable current. The applied voltages of the

9 switching device of the 5-level ANC inverter and -level inverter are difference. n the 5-level ANC inverter, the applied voltage of the Cell switching devices is quarter of the input voltage. The applied voltage of the Cell switching devices is half of the input voltage.thus, the switching device for the 5- level ANC inverter is the MOSFET. On the other hand, the applied voltage of the -level inverter is sae to the input voltage. The switching device for the -level inverter is the GBT. The capacitor values of the 5-level ANC inverter are designed by the ripple voltage value fro the table. The flying capacitor and DC soothing capacitor use the electrolytic capacitor because of designed capacitor value is high. Three capacitors are cnected in parallel because the ripple current is relatively high. Figure shows the efficiency of the 5-level ANC inverter and -level inverter. The efficiency of the 5-level ANC inverter is 99.3% at rated load. On the other hand, the efficiency of the -level inverter is 97.9 %. The efficiency of the 5-level ANC inverter is.3 % higher than the efficiency of the -level inverter. Figure shows the loss analysis of the 5-level ANC inverter and -level inverter. n the 5-level ANC inverter, ajor loss is doinant by the capacitor loss. On the other hand, ajor loss of the - level inverter is doinant by the cducti loss. Figure shows the volue of the 5-level ANC inverter and -level inverter. n the 5-level ANC inverter, the volue value is.36 d 3. The ajor volue of the 5-level ANC inverter is doinant by the capacitor volue of the flying capacitor and DC soothing capacitor. On the other hand, the volue value of the -level inverter is.35 d 3. The ajor volue of the -level inverter is doinant by the inductor. The volue of the -level inverter is lower.d 3 than the volue of the 5-level ANC inverter. However, the inductor volue of the 5-level ANC inverter is.d 3. On the other Table Specificati of the cverter. Table Selected devices. Table Designed device paraeters. Fig. efficiency of the 5-level ANC inverter Fig. Loss analysis of the cverters s. and -level inverter.

10 hand, the inductor volue of the -level inverter is.d 3. The 5-level ANC inverter can reduce the inductor volue by 5%. Figure 3 shows the relatiship between the efficiency and power density at switching frequency fro khz to khz. When the switching frequency is 9 khz, the 5-level ANC inverter achieves the axiu power density 5. kw/d 3 and the efficiency is 98.3%. On the other hand, when the switching frequency is khz, the -level inverter achieves the axiu power density 3.3 kw/d 3 and the efficiency point of 98.3%. The 5-level ANC inverter is proved to achieve a higher efficiency than the -level inverter.. Cclusi This paper established an optiizati designing ethod for a five-level ANC inverter. The fivelevel ANC inverter loss is analyzed by the atheatical expressis and experiental results. The error rate between the theoretical value and experiental value is % at the rated load. n additi, the perforance of the 5-level ANC inverter is copared with the cvential -level inverter under an applicati for syste. When the switching frequency is 9 khz, the 5-level ANC inverter achieves the axiu power density 5. kw/d 3 and efficiency is 98.3%. The 5-level ANC inverter is shown perfor better than the -level inverter in ter of efficiency and power density. n the future study, the perforance of the 5-level ANC inverter will be copared with other types of cvential ultilevel cverters. References [] F. Z. eng : A Generalized Multilevel nverter Topology with Self oltage Balancing, EEE Transactis industry applicatis, ol.37, No., pp. 4-3 () [] Barbosa,.; Steier,.; etc: Active Neutral-point-Claped Multilevel Cverter, ower Electrics Specialists Cference, 5. ESC '5. EEE 36th6-6 June 5 age(s):96 3 [3] Lin Ma, Taas Kerekes, etc : The high efficiency Transforer-less nverter Topologies Derived Fro NC Topology, EE9 Barcela [4]Yugo Kashihara, Jun-ichi toh: araeter design of a Five-level nverter for systes, CE- ECCE Asia [5] J. W. Kolar, J Biela and J. Miniböck: Exploring the areto Frt of Multi Objective Single-hase FC Rectifier Design Optiizati -99.% Efficiency vs. 7kW/d 3 ower Density,EMC 9-China,(9) [6] W. T. Mclyan: Transforer and inductor design handbook, Marcel Dekker nc. (4) [7] Data sheet: RF4668pBF (R) [8] Data sheet: XFB7N3 (XYS) ixys.co/datasheet//ds(xfb7n3).pdf [9] Data sheet: LGUWMELA (Nichic) [] Data sheet: FXAG47 (Hitachi) hitachiaic.co/products/cdenser/ali/neji.htl Fig. Analysis of the cverter volue Fig.3 Relatis between the Efficiency and power density.