VND600SP Double channel high-side solid state relay Features Description PowerSO-10

Transcription

1 Double channel high-side solid state relay Features Type R DS(on) I OUT V CC 3mΩ (1) 25A (1) 36V 1 1. Per each channel. DC short circuit current: 25A CMOS compatible inputs Proportional load current sense Under-voltage and over-voltage shutdown Over-voltage clamp Thermal shutdown Current limitation Very low standby power consumption Protection against loss of ground and loss of V CC Reverse battery protection Description The is a monolithic device made using STMicroelectronics VIPower M-3 technology. It is intended for driving resistive or inductive loads with one side connected to ground. Active V CC pin voltage clamp protects the device against low energy spikes (see ISO7637 transient compatibility table). This device has two channels in high-side configuration; each channel has an analog sense output on which the sensing current is proportional (according to a known ratio) to the corresponding load current. Built-in thermal shutdown and outputs current limitation protect the chip from over-temperature and short circuit. Device turns-off in case of ground pin disconnection. 1 PowerSO-1 Table 1. Device summary Package Tube Order codes Tape and reel PowerSO-1 13TR December 28 Rev 4 1/

2 Contents Contents 1 Block diagram and pin description Electrical specifications Absolute maximum ratings Thermal data Electrical characteristics Electrical characteristics curves Application information GND protection network against reverse battery Solution 1: a resistor in the ground line (RGND only) Solution 2: a diode (D GND ) in the ground line oad dump protection MCU I/O protection Maximum demagnetization energy (V CC = 13.5V) Package and PCB thermal data PowerSO-1 thermal data Package and packing information ECOPACK packages PowerSO-1 mechanical data PowerSO-1 packing information Revision history /26

3 ist of tables ist of tables Table 1. Device summary Table 2. Suggested connections for unused and not connected pins Table 3. Absolute maximum ratings Table 4. Thermal data Table 5. Power Table 6. Protections Table 7. V CC - output diode Table 8. Current sense (9V VCC 16V) Table 9. ogic inputs Table 1. Switching (V CC = 13V) Table 11. Truth table Table 12. Electrical transient requirements Table 13. Thermal parameters Table 14. PowerSO-1 mechanical data Table 15. Document revision history /26

4 ist of figures ist of figures Figure 1. Block diagram Figure 2. Configuration diagram (top view) Figure 3. Current and voltage conventions Figure 4. Switching characteristics Figure 5. I OUT /I SENSE versus I OUT Figure 6. Waveforms Figure 7. Off-state output current Figure 8. High level input current Figure 9. Input clamp voltage Figure 1. Turn-on voltage slope Figure 11. Over-voltage shutdown Figure 12. Turn-off voltage slope Figure 13. IIM vs Tcase Figure 14. On-state resistance vs VCC Figure 15. Input high level Figure 16. Input hysteresis voltage Figure 17. On-state resistance vs Tcase Figure 18. Input low level Figure 19. Application schematic Figure 2. Maximum turn-off current versus load inductance Figure 21. PowerSO-1 PC board Figure 22. Rthj-amb Vs PCB copper area in open box free air condition Figure 23. Thermal impedance junction ambient single pulse Figure 24. Thermal fitting model of a quad channel HSD in PowerSO Figure 25. PowerSO-1 package dimensions Figure 26. PowerSO-1 suggested pad layout Figure 27. PowerSO-1 tube shipment (no suffix) Figure 28. PowerSO-1 tape and reel shipment (suffix TR ) /26

5 Block diagram and pin description 1 Block diagram and pin description Figure 1. Block diagram V CC V CC CAMP OVER-VOTAGE UNDER-VOTAGE PwCAMP 1 INPUT 1 DRIVER 1 I IM1 OUTPUT 1 INPUT 2 GND OGIC Ot1 OVER-TEMP. 1 Ot2 OVER-TEMP. 2 DRIVER 2 V dslim1 I OUT1 K PwCAMP 2 I IM2 V dslim2 I OUT2 K Ot1 Ot2 CURRENT SENSE 1 OUTPUT 2 CURRENT SENSE 2 Figure 2. Configuration diagram (top view) GROUND INPUT 2 INPUT 1 C.SENSE1 C.SENSE OUTPUT 2 OUTPUT 2 N.C. OUTPUT 1 OUTPUT 1 11 V CC Table 2. Suggested connections for unused and not connected pins Connection / pin Current sense N.C. Output Input Floating X X X To ground Through 1KΩ resistor X Through 1KΩ resistor 5/26

6 Electrical specifications 2 Electrical specifications Figure 3. Current and voltage conventions I S V CC V F1 (*) V CC V IN1 I IN1 OUTPUT1 INPUT1 CURRENT SENSE 1 I OUT1 I SENSE1 V OUT1 V SENSE1 V IN2 I IN2 OUTPUT2 INPUT2 CURRENT SENSE 2 I OUT2 V OUT2 I SENSE2 GROUND V SENSE2 I GND 2.1 Absolute maximum ratings Stressing the device above the rating listed in the Absolute maximum ratings table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality document. Table 3. Absolute maximum ratings Symbol Parameter Value Unit V CC DC supply voltage 41 V -V CC Reverse supply voltage -.3 V - I GND DC reverse ground pin current - 2 ma I OUT Output current Internally limited A I R Reverse output current - 21 A I IN Input current +/- 1 ma V CSENSE Current sense maximum voltage V V V ESD Electrostatic discharge (human body model: R = 1.5KΩ; C = 1pF) - INPUT - CURRENT SENSE - OUTPUT - V CC V V V V 6/26

7 Electrical specifications Table 3. Symbol Parameter Value Unit E MAX Absolute maximum ratings (continued) Maximum switching energy ( =.13mH; R = Ω; V bat = 13.5V; T jstart = 15ºC; I = 4A) 145 mj P tot Power dissipation at T c = 25 C 96.1 W T j Junction operating temperature Internally limited C T c Case operating temperature -4 to 15 C T STG Storage temperature -55 to 15 C 2.2 Thermal data Table 4. Thermal data Symbol Parameter Max. value Unit R thj-case Thermal resistance junction-case 1.3 C/W R thj-amb Thermal resistance junction-ambient 51.3 (1) 37 (2) C/W 1. When mounted on a standard single-sided FR-4 board with.5cm 2 of Cu (at least 35 µm thick). 2. When mounted on a standard single-sided FR-4 board with 6 cm 2 of Cu (at least 35 µm thick). 2.3 Electrical characteristics Values specified in this section are for 8V < V CC < 36V; -4 C < T j < 15 C, unless otherwise stated. Table 5. Power Symbol Parameter Test conditions Min. Typ. Max. Unit V CC (1) V USD (1) Operating supply voltage V Under-voltage shutdown V V OV (1) Over-voltage shutdown 36 V R ON On-state resistance I OUT = 5A; T j = 25 C I OUT = 5A; T j = 15 C I OUT = 3A; V CC = 6V V clamp Clamp voltage I CC = 2mA (2) V Off-state; V CC =13V; V IN =V OUT =V 12 4 µa mω mω mω I S (1) Supply current Off-state; V CC =13V; V IN =V OUT =V; T j =25 C ma On-state; V IN = 5V; V CC = 13V; I OUT = A; R SENSE = 3.9kΩ 6 ma I (off1) Off-state output current V IN = V OUT = V 5 µa 7/26

8 Electrical specifications Table 5. Power (continued) Symbol Parameter Test conditions Min. Typ. Max. Unit I (off2) Off-state output current V IN = V; V OUT = 3.5V -75 µa I (off3) Off-state output current V IN = V OUT =V; V CC =13V; T j =125 C 5 µa I (off4) Off-state output current V IN =V OUT = V; V CC = 13V; T j = 25 C 3 µa 1. Per device. 2. V clamp and V OV are correlated. Typical difference is 5V. Table 6. Protections Symbol Parameter Test conditions Min. Typ. Max. Unit I lim T TSD T R DC short circuit current Thermal shutdown temperature Thermal reset temperature V CC = 13V 5.5V < V CC < 36V A A C 135 C T HYST Thermal hysteresis 7 15 C V demag V ON Turn-off output voltage clamp Output voltage drop limitation I OUT = 2A; V IN = V; = 6mH I OUT =.5A T j = -4 C C V CC - 41 V CC - 48 V CC - 55 V 5 mv Note: To ensure long term reliability under heavy over-load or short circuit conditions, protection and related diagnostic signals must be used together with a proper software strategy. If the device is subjected to abnormal conditions, this software must limit the duration and number of activation cycles. Table 7. V CC - output diode Symbol Parameter Test conditions Min. Typ. Max. Unit V F Forward on voltage - I OUT = 2.6A; T j = 15 C.6 V 8/26

9 Electrical specifications Table 8. Current sense (9V V CC 16V) Symbol Parameter Test conditions Min. Typ. Max. Unit K 1 I OUT /I SENSE V SENSE =.5V; other channels open; I OUT1 or I OUT2 =.5A; T j = -4 C...15 C dk 1 /K 1 Current sense ratio drift I OUT1 or I OUT2 =.5A; V SENSE =.5V; other channels open; T j = - 4 C...15 C % K 2 I OUT /I SENSE I OUT1 or I OUT2 = 5A; V SENSE = 4V; other channels open; T j = - 4 C T j = 25 C...15 C dk 2 /K 2 Current sense ratio drift I OUT1 or I OUT2 = 5A; V SENSE = 4V; other channels open; T j = -4 C...15 C % K 3 dk 3 /K 3 V SENSE1,2 V SENSEH R VSENSEH t DSENSE I OUT /I SENSE Current sense ratio drift Max analog sense output voltage Analog sense output voltage in over-temperature condition Analog sense output impedance in over-temperature condition Current sense delay response I OUT1 or I OUT2 = 15A; V SENSE = 4V; other channels open; T j = -4 C T j = 25 C...15 C I OUT1 or I OUT2 = 15A; V SENSE = 4V; other channels open; T j = -4 C...15 C V CC = 5.5V; I OUT1,2 = 2.5A; R SENSE = 1kΩ V CC > 8V, I OUT1,2 = 5A; R SENSE = 1kΩ % V CC = 13V; R SENSE = 3.9kΩ 5.5 V V CC = 13V; T j > T TSD ; all channels open To 9% I SENSE (1) 2 4 V V 4 Ω 5 µs 1. Current sense signal delay after positive input slope. 9/26

10 Electrical specifications Table 9. ogic inputs Symbol Parameter Test conditions Min. Typ. Max. Unit V I Input low level voltage 1.25 V I I ow level input current V IN = 1.25V 1 µa V IH Input high level voltage 3.25 V I IH High level input current V IN = 3.25V 1 µa V I(hyst) Input hysteresis voltage.5 V V IC Input clamp voltage I IN = 1mA I IN = - 1mA V V Table 1. Switching (V CC = 13V) Symbol Parameter Test conditions Min. Typ. Max. Unit t d(on) Turn-on delay time R = 2.6Ω (see Figure 4.) 3 µs t d(off) Turn-on delay time R = 2.6Ω (see Figure 4.) 3 µs (dv OUT /dt) on Turn-on voltage slope R = 2.6Ω (see Figure 4.) (dv OUT /dt) off Turn-off voltage slope R = 2.6Ω (see Figure 4.) See Figure 1. See Figure 12. V/ µs V/ µs Table 11. Truth table Conditions Input Output Sense Normal operation H H Nominal Over-temperature H V SENSEH Under-voltage H Over-voltage H Short circuit to GND H H (T j <T TSD ) (T j >T TSD ) V SENSEH Short circuit to V CC H H H < Nominal Negative output voltage clamp 1/26

11 Electrical specifications Table 12. ISO T/R 7637/1 Test pulse Electrical transient requirements 1-25V (1) Test level I II III IV Delays and impedance - 5V (1) - 75V (1) - 1V (1) 2ms, 1Ω V (1) + 5V (1) + 75V (1) + 1V (1).2ms, 1Ω 3a - 25V (1) - 5V (1) - 1V (1) - 15V (1).1µs, 5Ω 3b + 25V (1) + 5V (1) + 75V (1) + 1V (1).1µs, 5Ω 4-4V (1) - 5V (1) - 6V (1) - 7V (1) 1ms,.1Ω V (1) V (2) V (2) V (2) 4ms, 2Ω 1. All functions of the device are performed as designed after exposure to disturbance. 2. One or more functions of the device is not performed as designed after exposure and cannot be returned to proper operation without replacing the device. Figure 4. Switching characteristics V OUT 8% 9% dv OUT /dt (on) tr 1% t f dv OUT /dt (off) t I SENSE 9% INPUT t d(on) t DSENSE t d(off) t t 11/26

12 Electrical specifications Figure 5. I OUT /I SENSE versus I OUT I OUT /I SENSE max.tj= C min.tj= C max.tj=-4 C typical value min.tj=-4 C I OUT (A) 12/26

13 Electrical specifications Figure 6. Waveforms NORMA OPERATION INPUT n OAD CURRENT n SENSE n UNDER-VOTAGE V CC V USDhyst INPUT n V USD OAD CURRENT n SENSE n OVER-VOTAGE V CC INPUT n OAD CURRENT n SENSE n V OV VCC < V OV V CC > V OV INPUT n OAD CURRENT n OAD VOTAGE n SENSE n SHORT TO GROUND INPUT n OAD VOTAGE n SHORT TO V CC OAD CURRENT n SENSE n <Nominal <Nominal T j T TSD T R OVER-TEMPERATURE INPUT n OAD CURRENT n SENSE n V SENSEH I SENSE = RSENSE 13/26

14 Electrical specifications 2.4 Electrical characteristics curves Figure 7. Off-state output current Figure 8. High level input current I(off1) (ua) Iih (ua) Off state Vcc=36V Vin=Vout=V Vin=3.25V Tc ( C) Tc ( C) Figure 9. Input clamp voltage Figure 1. Turn-on voltage slope Vicl (V) 8 dvout/dt(on) (V/ms) Iin=1mA Vcc=13V Rl=2.6Ohm Tc ( C) Tc (ºC) Figure 11. Over-voltage shutdown Figure 12. Turn-off voltage slope Vov (V) 5 dvout/dt(off) (V/ms) Vcc=13V Rl=2.6Ohm Tc ( C) Tc (ºC) 14/26

15 Electrical specifications Figure 13. I IM vs T case Figure 14. On-state resistance vs V CC Ilim (A) Ron (mohm) Vcc=13V 7 6 Iout=5A Tc= 15 C Tc= 25 C Tc= - 4 C Tc ( C) Vcc (V) Figure 15. Input high level Figure 16. Input hysteresis voltage Vih (V) Tc ( C) Vhyst (V) Tc ( C) Figure 17. On-state resistance vs Tcase Figure 18. Input low level Ron (mohm) 1 Vil (V) Iout=5A Vcc=8V & 36V Tc ( C) Tc ( C) 15/26

16 Application information 3 Application information Figure 19. Application schematic +5V R prot INPUT1 V CC D ld µc R prot CURRENT SENSE1 OUTPUT1 R prot INPUT2 R prot CURRENT SENSE2 GND OUTPUT2 R SENSE1 R SENSE2 VGND R GND D GND 3.1 GND protection network against reverse battery This section provides two solutions for implementing a ground protection network against reverse battery Solution 1: a resistor in the ground line (R GND only) This can be used with any type of load. The following show how to dimension the R GND resistor: 1. R GND 6mV / 2 (I S(on)max ) 2. R GND ( - V CC ) / ( - I GND ) where - I GND is the DC reverse ground pin current and can be found in the absolute maximum rating section of the device datasheet. Power dissipation in R GND (when V CC < during reverse battery situations) is: P D = ( - V CC ) 2 / R GND This resistor can be shared amongst several different HSDs. Please note that the value of this resistor should be calculated with formula (1) where I S(on)max becomes the sum of the maximum on-state currents of the different devices. 16/26

17 Application information Please note that, if the microprocessor ground is not shared by the device ground, then the R GND will produce a shift (I S(on)max * R GND ) in the input thresholds and the status output values. This shift will vary depending on how many devices are ON in the case of several high-side drivers sharing the same R GND. If the calculated power dissipation requires the use of a large resistor, or several devices have to share the same resistor, then ST suggests using solution 2 below Solution 2: a diode (D GND ) in the ground line A resistor (R GND = 1kΩ) should be inserted in parallel to D GND if the device will be driving an inductive load. This small signal diode can be safely shared amongst several different HSD. Also in this case, the presence of the ground network will produce a shift (j6mv) in the input threshold and the status output values if the microprocessor ground is not common with the device ground. This shift will not vary if more than one HSD shares the same diode/resistor network. Series resistor in INPUT and STATUS lines are also required to prevent that, during battery voltage transient, the current exceeds the Absolute Maximum Rating. Safest configuration for unused INPUT and STATUS pin is to leave them unconnected. 3.2 oad dump protection D ld is necessary (voltage transient suppressor) if the load dump peak voltage exceeds the V CC maximum DC rating. The same applies if the device is subject to transients on the V CC line that are greater than those shown in the ISO T/R 7637/1 table. 3.3 MCU I/O protection If a ground protection network is used and negative transients are present on the V CC line, the control pins will be pulled negative. ST suggests to insert a resistor (R prot ) in line to prevent the µc I/O pins from latching up. The value of these resistors is a compromise between the leakage current of µc and the current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of µc I/Os: - V CCpeak / I latchup R prot (V OHµC - V IH - V GND ) / I IHmax Example For the following conditions: V CCpeak = - 1V I latchup 2mA V OHµC 4.5V 5kΩ R prot 65kΩ. Recommended values are: R prot = 1kΩ 17/26

18 Application information 3.4 Maximum demagnetization energy (V CC = 13.5V) Figure 2. Maximum turn-off current versus load inductance IMAX (A) 1 1 A C B 1,1, (mh) A = single pulse at T Jstart = 15ºC B= repetitive pulse at T Jstart = 1ºC C= repetitive pulse at T Jstart = 125ºC V IN, I Demagnetization Demagnetization Demagnetization t Note: Values are generated with R = Ω. In case of repetitive pulses, T jstart (at beginning of each demagnetization) of every pulse must not exceed the temperature specified above for curves B and C. 18/26

19 Package and PCB thermal data 4 Package and PCB thermal data 4.1 PowerSO-1 thermal data Figure 21. PowerSO-1 PC board Note: ayout condition of R th and Z th measurements (PCB FR4 area = 58mm x 58mm, PCB thickness = 2mm, Cu thickness = 35µm, Copper areas: from minimum pad-lay-out to 8cm 2 ). Figure 22. R thj-amb Vs PCB copper area in open box free air condition RTHj_amb ( C/W) 55 5 Tj-Tamb=5 C PCB Cu heatsink area (cm^2) 19/26

20 Package and PCB thermal data Figure 23. Thermal impedance junction ambient single pulse ZTH ( C/W) Footprint 6 cm Time (s) Equation 1: pulse calculation formula Z THδ = R TH δ + Z THtp ( 1 δ) where δ = t p T Figure 24. Thermal fitting model of a quad channel HSD in PowerSO-1 Tj_1 C1 C2 C3 C4 C5 C6 Pd1 R1 R2 R3 R4 R5 R6 Tj_2 C1 C2 R1 R2 Pd2 T_amb 2/26

21 Package and PCB thermal data Table 13. Thermal parameters Area / island (cm 2 ) Footprint 6 R1 ( C/W).5 R2 ( C/W).3 R3 ( C/W).3 R4 ( C/W).8 R5 ( C/W) 12 R6 ( C/W) C1 (W.s/ C).1 C2 (W.s/ C) 5E-3 C3 (W.s/ C).2 C4 (W.s/ C).3 C5 (W.s/ C).75 C6 (W.s/ C) /26

22 Package and packing information 5 Package and packing information 5.1 ECOPACK packages In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: ECOPACK is an ST trademark. 5.2 PowerSO-1 mechanical data Figure 25. PowerSO-1 package dimensions B 1.1 A B H E E2 E E4 1 SEATING PANE e.25 B DETAI "A" A C A A1 F h D = D1= = = SEATING PANE A1 DETAI "A" α 22/26

23 Package and packing information Table 14. PowerSO-1 mechanical data mm Dim. Min. Typ. Max. A A (1) A1.1 B.4.6 B (1) C C (1) D D E E E2 (1) E E4 (1) e 1.27 F F (1) H H (1) h (1) α 8 α (1) Muar only POA P13P. 23/26

24 Package and packing information 5.3 PowerSO-1 packing information Figure 26. PowerSO-1 suggested pad layout Figure 27. PowerSO-1 tube shipment (no suffix) C B CASABANCA MUAR A A C All dimensions are in mm. Base Q.ty Bulk Q.ty Tube length (±.5) A B C (±.1) Casablanca B Muar Figure 28. PowerSO-1 tape and reel shipment (suffix TR ) Reel dimensions Base Q.ty 6 Bulk Q.ty 6 A (max) 33 B (min) 1.5 C (±.2) 13 F 2.2 G (+ 2 / -) 24.4 N (min) 6 T (max) 3.4 Tape dimensions According to Electronic Industries Association (EIA) Standard 481 rev. A, Feb Tape width W 24 Tape Hole Spacing P (±.1) 4 Component Spacing P 24 Hole Diameter D (±.1/-) 1.5 Hole Diameter D1 (min) 1.5 Hole Position F (±.5) 11.5 Compartment Depth K (max) 6.5 Hole Spacing P1 (±.1) 2 All dimensions are in mm. End Start Top cover tape No components 5mm min Components Empty components pockets saled with cover tape. No components 5mm min User direction of feed 24/26

25 Revision history 6 Revision history Table 15. Document revision history Date Revision Changes 7-Jul-24 1 Initial release. 9-Sep-24 2 Current and voltage convention update (page 2). Configuration diagram (top view) & suggested connections for unused and n.c. pins insertion (page 2). 6 cm2 Cu condition insertion in thermal data table (page 3). V CC - output diode section update (page 3). Revision history table insertion (page 17). Disclaimers update (page 18). 3-May-26 3 Suggested connections for unused and n.c. pins correction. 15-Dec-28 4 Document reformatted and restructured. Added contents, list of tables and figures. Added ECOPACK packages information. 25/26

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