Datasheet. Macroblock 16-Channel Constant Current LED Sink Driver

Transcription

1 Features Datasheet Macroblock Small Outline Package 16 constant-current output channels Constant output current invariant to load voltage change: Constant output current range: DD =5V; DD =3.3V Excellent output current accuracy (I OUT DS =0.7V): between channels: ±1.5% (typ.) and ±2% (max.) between ICs: ±1.5% (typ.) and ±3% (max.) Output current adjusted through an external resistor Fast response of output current, OE (min.): 70ns with good uniformity between output channels Staggered delay of output 25MHz clock frequency Schmitt trigger input 3.3V/ 5V supply voltage RoHS compliant package GD: SOP24L GF: SOP24L Shrink SOP GP: SSOP24L Thin Shrink SOP GTS: TSSOP24L Product Description With PrecisionDrive technology, is designed for LED displays which require to operate at low current and to match the luminous intensity of each channel. It provides supply voltage and accepts CMOS logic input at 3.3V and 5.0V to meet the trend of low power consumption. contains a serial buffer and data latches which convert serial input data into parallel output format. At output stage, sixteen regulated current ports are designed to provide uniform and constant current sinks for driving LEDs within a large range of V F variations. provides users with great flexibility and device performance while using in their system design for LED display applications, e.g. LED panels. It accepts an input voltage range from 3V to 5.5V and maintains a constant current up from 1mA to 45mA determined by an external resistor, R ext, which gives users flexibility in controlling the light intensity of LEDs. guarantees to endure maximum 17V at the output port. The high clock frequency, 25 MHz, also satisfies the system requirements of high volume data transmission. Macroblock, Inc Floor 6-4, No.18, Pu-Ting Rd., Hsinchu, Taiwan 30077, ROC. TEL: , FAX: info@mblock.com.tw - 1 -

2 Block Diagram OUT0 OUT1 OUT14 OUT15 R-EXT I O Regulator VDD OE 16-bit Output Driver 16 LE 16-bit Output Latch GND 16 SDI CLK 16-bit Shift Register SDO Terminal Description Pin Configuration Pin No. Pin Name Function 1 GND Ground terminal for control logic and current sink 2 SDI Serial-data input to the shift register 3 CLK 4 LE Clock input terminal for data shift on rising edge Data strobe input terminal Serial data is transferred to the output latch when LE is high. The data is latched when LE goes low. 5~20 OUT0 ~ OUT15 Constant current output terminals GND SDI CLK LE OUT0 OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 OUT VDD R-EXT SDO OE OUT15 OUT14 OUT13 OUT12 OUT11 OUT10 OUT9 OUT8 GD/GF/GP/GTS Output enable terminal 21 OE 22 SDO 23 R-EXT When (active) low, the output drivers are enabled; when high, all output drivers are turned OFF (blanked). Serial-data output to the following SDI of next driver IC. SDO signal change on rising edge of CLK. Input terminal used to connect an external resistor for setting up output current for all output channels 24 VDD 3.3V/5V supply voltage terminal - 2 -

3 Equivalent Circuits of Inputs and Outputs OE terminal LE terminal VDD VDD IN IN CLK, SDI terminal VDD SDO terminal VDD IN OUT - 3 -

4 Timing Diagram CLK N = SDI D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 LE OE OUT0 OUT1 OUT2 OUT3 D0 D1 D2 OFF ON OFF ON OFF ON OFF ON OUT15 D15 OFF ON SDO D15 : don t care Truth Table CLK LE OE SDI OUT0 OUT 7 OUT15 SDO H L D n D n.. D n - 7. D n - 15 D n-15 L L D n+1 No Change D n-14 H L D n+2 D n + 2. D n - 5. D n - 13 D n-13 X L D n+3 D n + 2. D n - 5. D n - 13 D n-13 X H D n+4 Off D n

5 Maximum Ratings Characteristic Symbol Rating Unit Supply Voltage V DD 0~7.0 V Input Voltage V IN -0.4~V DD +0.4 V Output Current I OUT +90 ma Sustaining Voltage at OUT Port V DS -0.5~+17.0 V GND Terminal Current I GND ma Power Dissipation (On PCB, Ta=25 C) Thermal Resistance (On PCB, Ta=25 C) GD type 2.88 GF type 2.35 GP type 1.76 GTS-type 3.87 GD type GF type GP type GTS-type P D R th(j-a) Operating Temperature T opr -40~+85 C Storage Temperature T stg -55~+150 C W C/W - 5 -

6 Electrical Characteristics (V DD = 5.0V) Characteristics Symbol Condition Min. Typ. Max. Unit Supply Voltage V DD V Sustaining Voltage at OUT Ports Output Current Input Voltage V DS OUT0 ~ OUT V I OUT Refer to Test Circuit for Electrical Characteristics 1-45 ma I OH SDO ma I OL SDO ma H level V IH Ta =-40~85ºC 0.7*V DD - V DD V L level V IL Ta =-40~85ºC GND - 0.3*V DD V Output Leakage Current I OH V DS =17.0V µa Output Voltage SDO V OL I OL =+1.0mA V V OH I OH =-1.0mA V Output Current 1 I OUT1 V DS =1.0V R ext =18kΩ ma Current Skew di OUT1 I OL =1mA V DS =1.0V R ext =18kΩ - ±1.5 ±3.0 % Output Current 2 I OUT2 V DS =1.0V R ext =720Ω ma Current Skew Output Current vs. Output Voltage Regulation Output Current vs. Supply Voltage Regulation di OUT2 I OL =25.8mA V DS =1.0V R ext =720Ω - ±1.5 ±2.0 % %/dv DS V DS within 1.0V and 3.0V - ±0.1 - %/V %/dv DD V DD within 4.5V and 5.5V - - ±1.0 %/V Pull-up Resistor R IN (up) OE KΩ Pull-down Resistor R IN (down) LE KΩ Supply Current OFF ON I DD (off) 1 R ext =Open, OUT0 ~ OUT15 =Off I DD (off) 2 R ext =1860Ω, OUT0 ~ OUT15 =Off I DD (off) 3 R ext =744Ω, OUT0 ~ OUT15 =Off I DD (on) 1 R ext =1860Ω, OUT0 ~ OUT15 =On I DD (on) 2 R ext =744Ω, OUT0 ~ OUT15 =On ma - 6 -

7 Electrical Characteristics (V DD = 3.3V) Characteristics Symbol Condition Min. Typ. Max. Unit Supply Voltage V DD V Sustaining Voltage at OUT Ports Output Current Input Voltage V DS OUT0 ~ OUT V I OUT Refer to Test Circuit for Electrical Characteristics 1-30 ma I OH SDO ma I OL SDO ma H level V IH Ta=-40~85ºC 0.7*V DD - V DD V L level V IL Ta=-40~85ºC GND - 0.3*V DD V Output Leakage Current I OH V DS =17.0V µa Output Voltage SDO V OL I OL =+1.0mA V V OH I OH =-1.0mA V Output Current 1 I OUT1 V DS =1.0V R ext =18kΩ ma Current Skew di OUT1 I OL =1mA V DS =1.0V R ext =18kΩ - ±1.5 ±3.0 % Output Current 2 I OUT2 V DS =1.0V R ext =720Ω ma Current Skew Output Current vs. Output Voltage Regulation Output Current vs. Supply Voltage Regulation di OUT2 I OL =25.8mA V DS =1.0V R ext =720Ω - ±1.5 ±2.0 % %/dv DS V DS within 1.0V and 3.0V - ±0.1 - %/V %/dv DD V DD within 3.0V and 4.5V - - ±1.0 %/V Pull-up Resistor R IN (up) OE KΩ Pull-down Resistor R IN (down) LE KΩ Supply Current OFF ON I DD (off) 1 R ext =Open, OUT0 ~ OUT15 =Off I DD (off) 2 R ext =6200Ω, OUT0 ~ OUT15 =Off I DD (off) 3 R ext =744Ω, OUT0 ~ OUT15 =Off I DD (on) 1 R ext =6200Ω, OUT0 ~ OUT15 =On I DD (on) 2 R ext =744Ω, OUT0 ~ OUT15 =On ma Test Circuit for Electrical Characteristics IDD VDD IOUT V DD OE OUT0 I IH,IIL. DS CLK V LE. OUT15 V IH, VIL SDI SDO R - EXT GND Iref - 7 -

8 Switching Characteristics (V DD = 5.0V) Propagation Delay Time ( L to H ) Propagation Delay Time ( H to L ) Pulse Width Characteristics Symbol Condition Min. Typ. Max. Unit CLK- OUT 2n ns CLK- OUT 2n + 1 t plh ns LE- OUT 2n ns LE- OUT 2n + 1 t plh ns OE - OUT 2n ns OE - OUT 2n + 1 t plh ns CLK-SDO t plh ns CLK- OUT 2n ns CLK- OUT 2n + 1 t phl ns OE t w(oe) ns Hold Time for LE t h(l) ns Setup Time for LE t su(l) ns Hold Time for SDI t h(d) ns Setup Time for SDI t su(d) ns Maximum CLK Rise Time t r ns Maximum CLK Fall Time t f ns SDO Rise Time t r,sdo ns SDO Fall Time t f,sdo ns Output Rise Time of Output Ports t or ns Output Fall Time of Output Ports LE- OUT 2n t phl ns LE- OUT 2n + 1 V DD =5.0 V ns OE - OUT 2n t phl3 V DS =1.0 V V IH =V DD ns OE - OUT 2n + 1 V IL =GND ns CLK-SDO t phl R ext =930 Ω V L =4.5 V ns CLK t w(clk) R L =162 Ω ns LE t w(l) C L =10 pf ns t of ns * Among output channels exist 15ns delay time between odd number OUT 2n + 1 (e.g.:bit1/bit3/bit5 )and even number OUT 2n (ex: Bit0/Bit2/Bit4 ). has a built-in staggered circuit to perform delay mechanism, by which the even and odd output ports will be turned on at a different time so that the instant current from the power line will be lowered

9 Switching Characteristics (V DD = 3.3V) Propagation Delay Time ( L to H ) Propagation Delay Time ( H to L ) Pulse Width Characteristics Symbol Condition Min. Typ. Max. Unit CLK- OUT 2n ns CLK- OUT 2n + 1 t plh ns LE- OUT 2n ns LE- OUT 2n + 1 t plh ns OE - OUT 2n ns OE - OUT 2n + 1 t plh ns CLK-SDO t plh ns CLK- OUT 2n ns CLK- OUT 2n + 1 t phl ns OE t w(oe) ns Hold Time for LE t h(l) ns Setup Time for LE t su(l) ns Hold Time for SDI t h(d) ns Setup Time for SDI t su(d) ns Maximum CLK Rise Time t r ns Maximum CLK Fall Time t f ns SDO Rise Time t r,sdo ns SDO Fall Time t f,sdo ns Output Rise Time of Output Ports t or ns Output Fall Time of Output Ports LE- OUT 2n t phl ns LE- OUT 2n + 1 V DD =3.3 V ns OE - OUT 2n t phl3 V DS =1.0 V V IH =V DD ns OE - OUT 2n + 1 V IL =GND ns CLK-SDO t phl R ext =930 Ω V L =4.5 V ns CLK t w(clk) R L =162 Ω ns LE t w(l) C L =10 pf ns Test Circuit for Switching Characteristics t of ns IDD VDD Function Generator Logic Input VIH, VIL OE CLK LE SDI VDD R - EXT GND. OUT0 OUT15 SDO IOUT RL CL 5V Waveform Iref CL VL 0V t r =t f =10ns - 9 -

10 Timing Waveform CLK t W(CLK) 50% 50% 50% t su(d) t h(d) SDI 50% 50% SDO 50% LE t plh, t phl t h(l) t W(L) 50% 50% t su(l) OE LOW = OUTPUTS ENABLED HIGH = OUTPUT OFF OUTn 50% t plh1, t phl1 t plh2, t phl2 LOW = OUTPUT ON t W(OE) OE 50% 50% t phl3 t plh3 OUTn 90% 90% 50% 50% 10% % t of t or

11 Application Information Constant Current To design LED displays, provides nearly no variations in current from channel to channel and from IC to IC. This can be achieved by: 1) The maximum current variation between channels is less than ±2%, and that between ICs is less than ±3%. 2) In addition, the current characteristic of output stage is flat and users can refer to the figure as shown below. The output current can be kept constant regardless of the variations of LED forward voltages (V F ). This performs as a perfection of load regulation. I OUT (ma) 50 I OUT vs. V DS at Various R ext,v DD =5.0V V DS (V) I OUT (ma) 40 I OUT vs. V DS at Various R ext,v DD =3.3V V DS (V)

12 Adjusting Output Current The output current of each channel (I OUT ) is set by an external resistor, R ext. The relationship between I OUT and R ext is shown in the following figure. Also, the output current can be calculated from the equation: V R-EXT =1.24VI OUT =V R-EXT x(1/r ext )x15; R ext =(V R-EXT /I OUT )x15 I OUT (ma) R ext vs. I OUT R ext (Ω) Where R ext is the resistance of the external resistor connected to R-EXT terminal and V R-EXT is the voltage of R-EXT terminal. The magnitude of current (as a function of R ext ) is around 25mA at 744Ω and 10mA at 1860Ω

13 Soldering Process of Pb-free & Green Package* Macroblock has defined "Pb-Free & Green" to mean semiconductor products that are compatible with the current RoHS requirements and selected 100% pure tin (Sn) to provide forward and backward compatibility with both the current industry-standard SnPb-based soldering processes and higher-temperature Pb-free processes. Pure tin is widely accepted by customers and suppliers of electronic devices in Europe, Asia and the US as the lead-free surface finish of choice to replace tin-lead. Also, it is backward compatible to standard 215ºC to 240ºC reflow processes which adopt tin/lead (SnPb) solder paste. However, in the whole Pb-free soldering processes and materials, 100% pure tin (Sn), will all require up to 260 o C for proper soldering on boards, referring to J-STD-020C as shown below. Temperature () Average ramp-up rate= 0.7/s 30s max Ramp-down 6/s (max) s max 100 Peak Temperature 245~260< 10s 50 Average ramp-up rate = 0.4/s Average ramp-up rate= 3.3/s Maximum peak temperature Recommended reflow profile Acc. J-STD-020C Time (sec) *Note1: For details, please refer to Macroblock s Policy on Pb-free & Green Package

14 Package Power Dissipation (PD) The maximum allowable package power dissipation is determined as P D (max)=(tj Ta)/R th(j-a). When 16 output channels are turned on simultaneously, the actual package power dissipation is P D (act)=(i DD xv DD )+(I OUT xdutyxv DS x16). Therefore, to keep P D (act) P D (max), the allowable maximum output current as a function of duty cycle is: I OUT ={[(Tj Ta)/R th(j-a) ] (I DD xv DD )}/V DS /Duty/16, where Tj=150 C. Max. I OUT (ma) I OUT vs. Duty Cycle@ R th(j-a) =46.60/W VDS=1V@Ta=25 VDS=1V@Ta=85 VDS=2V@Ta=25 VDS=2V@Ta=85 Max. I OUT (ma) I OUT vs. Duty Cycle@ R th(j-a) =53.28C/W VDS=1V@Ta=25 VDS=1V@Ta=85 VDS=2V@Ta=25 VDS=2V@Ta= % 20% 30% 40% 50% 60% 70% 80% 90% 100% Duty Cycle 0 10% 20% 30% 40% 50% 60% 70% 80% 90% 100% Duty Cycle GD GF I OUT vs. Duty Cycle@ R th(j-a) =70.90/W Max. I OUT (ma) % 20% 30% 40% 50% 60% 70% 80% 90% 100% Duty Cycle VDS=1V@Ta=25 VDS=1V@Ta=85 VDS=2V@Ta=25 VDS=2V@Ta=85 Max. I OUT (ma) I OUT vs. Duty Cycle@ R th(j-a) =32.34/W % 20% 30% 40% 50% 60% 70% 80% 90% 100% Duty Cycle VDS=1V@Ta=25 VDS=1V@Ta=85 VDS=2V@Ta=25 VDS=2V@Ta=85 GP GTS Condition: I OUT =45mA,16 output Channels Device Type R th(j-a) ( C/W) GD GF GP GTS

15 The maximum power dissipation, P D (max)=(tj Ta)/R th(j-a), decreases as the ambient temperature increases. Power Dissipation (W) Maximum Power Dissipation at Various Ambient Temperature GD Type: Rth=46.60C/W GF Type: Rth=53.28C/W GP Type: Rth=70.90C/W GTS Type: Rth=32.34C/W Safe Operation Area Ambient Temperature (C) Load Supply Voltage (V LED ) are designed to operate with V DS ranging from 0.4V to 0.8V (depending on I OUT =1~45mA) considering the package power dissipating limits. V DS may be higher enough to make P D(act) >P D(max) when V LED =5V and V DS =V LED V F, in which V LED is the load supply voltage. In this case, it is recommended to use the lowest possible supply voltage or to set an external voltage reducer, V DROP. A voltage reducer lets V DS =(V LED V F ) V DROP. Resistors or Zener diode can be used in the applications as shown in the following figures. V LED Voltage Supply Voltage Supply (V LED ) V Drop V Drop V F V DS V F V DS Switching Noise Reduction LED driver ICs are frequently used in switch-mode applications which always behave with switching noise due to the parasitic inductance on PCB. To eliminate switching noise, refer to Application Note for 8-bit and 16-bit LED Drivers- Overshoot

16 Package Outline GD Outline Drawing GF Outline Drawing

17 GP Outline Drawing GAUGE PLANE SEATING PLANE Unit: mm D E E1 A A1 A2 D1 E2 b e θ MIN NOM MAX MIN NOM MAX MIN NOM MAX MAX MAX MIN NOM MAX MIN NOM MAX MIN NOM MAX MIN MAX MIN MAX GTS Outline Drawing Note 1: The unit for the outline drawing is mm. Note 2: Please use the maximum dimensions for the thermal pad layout. To avoid the short circuit risk, the vias or circuit traces shall not pass through the maximum area of thermal pad

18 Product Top-mark Information The first row of printing MBIXXXX Or MBIXXXX Part number ID number The second row of printing XXXXXXXX Product No. Package Code Process Code G: Green and Pb-free Manufacture Code Device Version Code Product Revision History Datasheet version Device version code V1.00 A VA.00 A VA.01 B VA.02 B VA.03 B VA.04 B Product Ordering Information Part Number RoHS Compliant Weight (g) Package Type GD SOP24L GF SOP24L GP SSOP24L GTS TSSOP

19 Disclaimer Macroblock reserves the right to make changes, corrections, modifications, and improvements to their products and documents or discontinue any product or service. Customers are advised to consult their sales representative for the latest product information before ordering. All products are sold subject to the terms and conditions supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. Macroblock s products are not designed to be used as components in device intended to support or sustain life or in military applications. Use of Macroblock s products in components intended for surgical implant into the body, or other applications in which failure of Macroblock s products could create a situation where personal death or injury may occur, is not authorized without the express written approval of the Managing Director of Macroblock. Macroblock will not be held liable for any damages or claims resulting from the use of its products in medical and military applications. Related technologies applied to the product are protected by patents. All text, images, logos and information contained on this document is the intellectual property of Macroblock. Unauthorized reproduction, duplication, extraction, use or disclosure of the above mentioned intellectual property will be deemed as infringement