Calibration of current-steering D/A Converters

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1 Calibration of current-steering D/A Converters Citation for published version (APA): Radulov,. I., Quinn, P. J., Hegt, J. A., & Roermund, van, A. H. M. (2009). Calibration of current-steering D/A Converters. In Proceedings of Analog/Mixed-signal Innovation Network "Digitally Assisted Analogue", 22nd October 2009, Dublin, Ireland (pp. 1-26) Document status and date: Published: 01/01/2009 Document Version: Publisher s PDF, also known as Version of Record (includes final page, issue and volume numbers) Please check the document version of this publication: A submitted manuscript is the version of the article upon submission and before peer-review. There can be important differences between the submitted version and the official published version of record. People interested in the research are advised to contact the author for the final version of the publication, or visit the DOI to the publisher's website. The final author version and the galley proof are versions of the publication after peer review. The final published version features the final layout of the paper including the volume, issue and page numbers. Link to publication eneral rights Copyright and moral rights for the publications made accessible in the public portal are retained by the authors and/or other copyright owners and it is a condition of accessing publications that users recognise and abide by the legal requirements associated with these rights. Users may download and print one copy of any publication from the public portal for the purpose of private study or research. You may not further distribute the material or use it for any profit-making activity or commercial gain You may freely distribute the URL identifying the publication in the public portal. If the publication is distributed under the terms of Article 25fa of the Dutch Copyright Act, indicated by the Taverne license above, please follow below link for the End User Agreement: Take down policy If you believe that this document breaches copyright please contact us at: openaccess@tue.nl providing details and we will investigate your claim. Download date: 28. Mar. 2019

2 Calibration of Current Steering D/A Converters ir. eorgi Radulov 1, dr. ir. Patrick Quinn 2, dr. ir. Hans Hegt 1, prof. dr. ir. Arthur van Roermund 1 1 Eindhoven University of Technology 2 Xilinx

3 Current-steering D/A converters Applications demand performance; Errors limit performance; Small errors demand huge resources. Correction methods: Improve performance and Relax design requirements 2

4 Overview Mismatch problem; Current calibration method; MSB unary currents calibration in a 12b 250nm DAC All (MSB unary and LSB binary) currents calibration in a quad-core 12b 180nm DAC; All currents calibration in a 12b-16b flexible 40nm DAC Conclusions 3

5 Mismatch problem Elements real values deviate PDF(I) Deviation depends on: Area Tech. and Circuit parameters I MEAN I I High resolution D/A require Many and accurate elements 2 σ I K I ~ W L ( ) I Large silicon areas Large silicon areas cause Systematic errors Drop of performance INL max ~ n σ I I 4

6 Start-up calibration scheme Mismatch correction; Input offset cancellation; Two phases: φa, φb; φa: I temp =I ref -I offset ; φb: I th (i)=i temp + I offset =I ref ; I offset 1-bit ADC FSM φa: open φa: closed φb: closed φb: open I th (i) I ref I temp with I ref =ΣI bin + I LSB ; Simple logic: 8-state FSM. CALDAC(i) temp CALDAC 5

7 12bit self-calibrating DAC in 250nm CMOS, see ESSCIRC 05

8 12bit DAC implementation 12b current-steering DAC; Segmentation: 6LSB/6MSB; 63 thermo bits calibrated; 6 binary not calibrated; Reference: binary bits; 5bit signed CALDACs; CMOS 0.25µm; Vdd 2.5V. technische universiteit eindhoven 7

9 Chip micrograph 0.98mm Input drivers Latches & Decoder 1.16mm Latches & Decoder CMOS 0.25µm, 1P5M; Coarse (main) current sources designed for 10b Decoder Decoder accuracy in 0.1mm 2 ; FSM & 1bit ADC Cascodes M2, M3a, M3b Array of CALDACs Fully integrated selfcalibration in 0.3mm 2 ; Coarse current sources 5 extra pads for calibration: 4 in & 1 out; technische universiteit eindhoven 8

10 Self-calibration of MSB unary currents measurements SFDR = 68dB SFDR = 81dB Before calibration +13dB After calibration 9

11 Self-calibration of MSB unary currents measurements HD (2,3,4,5) (max) improvement +18dB SFDR improvement +13dB 10

12 Calibration potential Distribution before calibration 3.5 LSB span, σ=1.06lsb; Tech. and design tolerances; Unary currents: +4 bits Distribution after calibration 0.2 LSB span, σ=0.03lsb; Calibration step sets the span; technische universiteit eindhoven 11

13 Static performance INL [LSB] Before 10b MSB unary part dominate; INL max = 1.5LSB; Digital code LSB non-calibrated binary part dominate; INL max = 0.4LSB INL: +2b After 12b INL [LSB] Digital code technische universiteit eindhoven 12

14 Calibration of binary currents Binary no redundancy New sub-dac segmentation (M binary sets) redundancy B 1 1: I ( B)(1) + I ( i)(1) + 1 LSB: = I bin bin ref _ u i= 1 I ref _ bn B 1 2 : I ( B)(2) + I ( i)(1) + 1 LSB: = I bin ref _ bn 3: I ( B)( 1) + I ( B)(2) : = I bin bin ref _ u i= 1 I bin ref _ u equal 1/2 13

15 12b-14b self-calibrating flexible DAC in 180nm CMOS, see APCCAS 08

16 Parallel sub-dac units architecture Current-steering DACs: Parallel current sources (switch current cells), which are switched in groups to create the analog output; a) Unary (Thermometer) grouping; b) Binary grouping; c) Segmented grouping; d) Our NEW grouping: parallel sub-dacs (with an exemplary implementation). technische universiteit eindhoven 15

17 A 12-bit self-calibrated quad-core current-steering DAC recall: 1mm 2 for the presented 12b DAC (250nm CMOS) 0,2mm 2 per 12b DAC (180nm CMOS) -Large LSB binary part; -Full calibration. 16

18 Calibration of unary and binary currents, measurements INL Before calibration After calibration DNL 17

19 Calibration of all DAC currents, measurements DAC accuracy depends only on a design parameter 18

20 Calibration of all DAC currents, dynamic measurements SFDR = 80dB SFDR = 75dB 19

21 12b-16b self-calibrating flexible DAC in 40nm CMOS, unpublished yet

22 A 12b-16b self-calibrated flexible DAC in 40nm CMOS Off-chip calibration engine; Flexibility; Analog outpu N OP K L M H IJ D EF C B A N OP K L M H IJ D EF C B A N OP K L M H IJ D EF C A B N OP M K L H IJ E F D A BC Construction of the full transfer characteristic Narrow gray - sub-dacs set to full-scale 0 ; Italic - sub-dacs convert the12 LSB input data; BOLD - sub-dacs set to full-scale 1. N OP K L M H IJ F E D A BC N OP K L M H IJ F D E A BC N OP K L M H IJ D EF A BC N OP M K L J I H D EF A BC N OP M K L J I H D EF A BC Digital input O N OP MNOP N M M N L M M K L M NOP N OP O P P L K K K L K L K L J H I D EF A BC H IJ D EF A BC H IJ D EF A BC H IJ D EF A BC H IJ D EF A BC H IJ D EF A BC P N O K L M H IJ D EF A BC 15b output 13b output 14b output 12b output 12b output 0.047mm 2 per 12b sub-dac (recall: 1mm 2 for 250nm; 0.2mm 2 for 180nm)

23 Calibration of all DAC currents, INL & slow signals measurements +5 bits Before: SFDR = 59dB After: SFDR = 79dB Before: SFDR = 63dB After: SFDR = 80dB +4 bits

24 Calibration of all DAC currents, dynamic measurements

25 Conclusions Calibration: improves performance; relaxes design requirements; reduces product risks; 3 test-chip demonstrated: aggressive analog area reduction; high current accuracy; analog performance supported by digital.

26 Acknowledgements Xilinx Ireland, Mixed-Signal Design roup Financial support of Dutch Tech. Foundation STW 25

27 Thanks for attention! Discussion technische universiteit eindhoven 26

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