Orderable Part Number IRL100HS121 PQFN 2mm x 2mm Tape and Reel 4000 IRL100HS121. Typical R DS(on) (m )
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1 Target Applications Wireless charging Adapter Telecom Benefits Higher power density designs Higher switching frequency IR MOSFET - Uses OptiMOS TM 5 Chip Reduced parts count wherever 5V supplies are available Driven directly from microcontrollers (slow switching) System cost reductions V DSS V min. D 1 D 2 Q g tot 3.7nC G 3 S Typical values (unless otherwise specified) Top View D V GS ± 20V max 6 D 5 D 4 S Q gd 1.6nC R DS(on) (max.) V V gs(th) 1.7V PQFN 2 mm x 2 mm G D S Gate Drain Source Standard Pack Base part number Package Type Orderable Part Number Form Quantity PQFN 2mm x 2mm Tape and Reel R DS(on), Drain-to -Source On Resistance (m ) I D = 6.7A T J = 125 C T J = 25 C V GS, Gate -to -Source Voltage (V) Typical R DS(on) (m ) VGS = 4.0V VGS = 4.5V VGS = 5.0V VGS = 6.0V VGS = 7.0V VGS = V I D, Drain Current (A) Figure 1 Typical On-Resistance vs. Gate Voltage Figure 2 Typical On-Resistance vs. Drain Current Final Datasheet Please read the important Notice and Warnings at the end of this document
2 Table of Contents Table of Contents Target Applications Benefits Ordering Table. 1 Table of Contents Parameters 3 2 Maximum ratings, Thermal, and Avalanche characteristics 4 3 Electrical characteristics 5 4 Electrical characteristic diagrams 6 Package Information 12 Qualification Information 14 Revision History.. 15 Final Datasheet 2
3 Parameters 1 Parameters Table1 Key performance parameters Parameter Values Units V DS V R DS(on) max 42 m I T C = 25 C 11 A I T A = 25 C 5.1 A Final Datasheet 3
4 Maximum ratings and thermal characteristics 2 Maximum ratings and thermal characteristics Table 2 Maximum ratings (at T J = 25 C, unless otherwise specified) Parameter Symbol Conditions Values Unit Continuous Drain Current (Silicon Limited) I D T C (Bottom) = 25 C, V V 11 Continuous Drain Current (Silicon Limited) I D T C (Bottom) = C, V V 7.8 Continuous Drain Current (Silicon Limited) (Source Bonding Technologies Limited) I D T C (Bottom) = 25 C, V V.2 A Continuous Drain Current (Silicon Limited) I D T A= 25 C, V V 5.1 Pulsed Drain Current I DM T C (Bottom) = 25 C 41 Maximum Power Dissipation P D T C (Bottom) = 25 C 11.5 Maximum Power Dissipation P D T C (Bottom) = C 5.8 W Maximum Power Dissipation P D T A = 25 C 2.5 Gate-to-Source Voltage V GS - ± 20 V Peak Soldering Temperature T P Operating Junction and Storage Temperature Range T J,T STG to C Table 3 Thermal characteristics Parameter Symbol Conditions Min. Typ. Max. Unit Junction-to-Case (Bottom) R JC Junction-to-Case (Top) R JC Junction-to-Ambient R JA C/W Junction-to-Ambient R JA (<s) Table 4 Avalanche characteristics Parameter Symbol Values Unit Single Pulse Avalanche Energy E AS 13 mj Avalanche Current I AR 5.0 A Notes: Repetitive rating; pulse width limited by max. junction temperature. Starting T J = 25 C, L = 1.0mH, R G = 50, I AS = 5.0A based on test data. Pulse width 400µs; duty cycle 2%. R is measured at T J of approximately 90 C. When mounted on a 1 inch square PCB (FR-4). Please refer to AN-994 for more details. Calculated continuous current based on maximum allowable junction temperature. Current is limited to.2a by source bonding technology. Final Datasheet 4
5 Electrical characteristics 3 Electrical characteristics Table 5 Static characteristics Parameter Symbol Conditions Values Min. Typ. Max. Unit Drain-to-Source Breakdown Voltage V (BR)DSS V GS = 0V, I D = 250µA - - V Breakdown Voltage Temp. Coefficient V (BR)DSS/ T J Reference to 25 C, I D = 1mA mv/ C Static Drain-to-Source On-Resistance R DS(on) V GS = V, I D = 6.7A V GS = 4.5V, I D = 3.4A m Gate Threshold Voltage V GS(th) V V DS = V GS, I D = µa Gate Threshold Voltage Temp. Coefficient V GS(th)/ T J mv /C Drain-to-Source Leakage Current I DSS V DS = 80V, V GS = 0V µa Gate-to-Source Forward Leakage I GSS V GS = 20V - - I GSS V GS = -20V - - na Gate Resistance R G Table 6 Dynamic characteristics Values Parameter Symbol Conditions Unit Min. Typ. Max. Forward Trans conductance gfs V DS = 25V, I D = 6.7A S Total Gate Charge Q g Pre-Vth Gate-to-Source Charge Q gs1 I D = 6.7A Post-Vth Gate-to-Source Charge Q gs2 V DS = 50V nc Gate-to-Drain Charge Q V GS gd = 4.5V See Fig.8 Gate Charge Overdrive Q godr Switch Charge (Qgs2 + Qgd) Q sw Output Charge Q oss V DS = 50V,V GS = 0V nc Turn-On Delay Time t d(on) V DD = 50V Rise Time t r I D = 6.7A Turn-Off Delay Time t d(off) R G = ns Fall Time t f V GS = 4.5V Input Capacitance C iss V GS = 0V Output Capacitance C oss V DS = 50V Reverse Transfer Capacitance C rss ƒ = 1.0MHz pf Output Capacitance C oss V GS = 0V, V DS = 1.0V, ƒ = 1.0MHz Output Capacitance C oss V GS = 0V, V DS = 80V, ƒ = 1.0MHz Table 7 Reverse Diode Values Parameter Symbol Conditions Unit Min. Typ. Max. Continuous Source Current MOSFET symbol D I S (Body Diode) showing the G A Pulsed Source Current integral reverse I SM S (Body Diode) p-n junction diode. Diode Forward Voltage V SD T J = 25 C, I S = 6.7A,V GS = 0V V Reverse Recovery Time t rr T J = 25 C, I F = 6.7A, V DD = 50V ns Reverse Recovery Charge Q rr di/dt = A/µs nc Final Datasheet 5
6 Electrical characteristic diagrams 4 Electrical characteristic diagrams 60µs PULSE WIDTH Tj = 25 C 60µs PULSE WIDTH Tj = 175 C I D, Drain-to-Source Current (A) 1 2.7V VGS TOP 12V V 4.5V 4.0V 3.5V 3.3V 3.0V BOTTOM 2.7V I D, Drain-to-Source Current (A) 1 2.7V VGS TOP 12V V 4.5V 4.0V 3.5V 3.3V 3.0V BOTTOM 2.7V V DS, Drain-to-Source Voltage (V) V DS, Drain-to-Source Voltage (V) Figure 3 Typical Output Characteristics Figure 4 Typical Output Characteristics 2.4 I D, Drain-to-Source Current (A) 1 T J = 175 C T J = 25 C V DS = 25V 60µs PULSE WIDTH V GS, Gate-to-Source Voltage (V) R DS(on), Drain-to-Source On Resistance (Normalized) I D = 6.7A V 2.0 GS = V T J, Junction Temperature ( C) Figure 5 Typical Transfer Characteristics Figure 6 Normalized On-Resistance vs. Temperature Final Datasheet 6
7 I SD, Reverse Drain Current (A) I D, Drain-to-Source Current (A) C, Capacitance (pf) Electrical characteristic diagrams 00 0 V GS = 0V, f = 1 MHZ C iss = C gs + C gd, C ds SHORTED C rss = C gd C oss = C ds + C gd C iss C oss C rss V GS, Gate-to-Source Voltage (V) I D = 6.7A V DS = 80V V DS = 50V V DS = 20V V DS, Drain-to-Source Voltage (V) Q G, Total Gate Charge (nc) Figure 7 Typical Capacitance vs. Drain-to-Source Voltage Figure 8 Typical Gate Charge vs. Gate-to-Source Voltage OPERATION IN THIS AREA LIMITED BY R DS (on) T J = 175 C T J = 25 C 1 LIMITED BY PACKAGE µsec 1msec 1 V GS = 0V V SD, Source-to-Drain Voltage (V) msec 0.1 Tc = 25 C DC Tj = 175 C Single Pulse V DS, Drain-to-Source Voltage (V) Figure 9 Typical Source-Drain Diode Forward Voltage Figure Maximum Safe Operating Area Final Datasheet 7
8 V GS(th), I D, Drain Current (A) Gate threshold Voltage (V) Electrical characteristic diagrams 12 LIMITED BY PACKAGE I D = µa I D = 250µA I D = 1.0mA I D = 1.0A T C, Case Temperature ( C) T J, Temperature ( C ) Figure 11 Maximum Drain Current vs. Case Temperature Figure 12 Typical Threshold Voltage vs. Junction Temperature E AS, Single Pulse Avalanche Energy (mj) I D TOP 1.1A 1.7A BOTTOM 5.0A Starting T J, Junction Temperature ( C) Figure 13 Maximum Avalanche Energy vs. Drain Current Final Datasheet 8
9 Electrical characteristic diagrams Single Pulse Allowed avalanche Current vs avalanche pulsewidth, tav, assuming Tj = 150 C and Tstart =25 C (Single Pulse) Avalanche Current (A) Allowed avalanche Current vs avalanche pulsewidth, tav, assuming Tj =25 C and Tstart = 150 C E E E E E E-01 tav (sec) Figure 14 Typical Avalanche Current vs. Pulse Width Thermal Response ( Z thjc ) D = SINGLE PULSE ( THERMAL RESPONSE ) 1E-006 1E t 1, Rectangular Pulse Duration (sec) Notes: 1. Duty Factor D = t1/t2 2. Peak Tj = P dm x Zthjc + Tc Figure 15 Maximum Effective Transient Thermal Impedance, Junction-to-Case Final Datasheet 9
10 Electrical characteristic diagrams Figure 16 Peak Diode Recovery dv/dt Test Circuit for N-Channel Power MOSFETs Figure 17a Gate Charge Test Circuit Figure 17b Gate Charge Waveform Final Datasheet
11 Electrical characteristic diagrams Figure 18a Unclamped Inductive Test Circuit Figure 18b Unclamped Inductive Waveforms Figure 19a Switching Time Test Circuit Figure 19b Switching Time Waveforms Final Datasheet 11
12 Package Information 5 Package Information PQFN 2 x 2 Outline Package Details For more information on board mounting, including footprint and stencil recommendation, please refer to application note AN-1136: For more information on package inspection techniques, please refer to application note AN-1154: PQFN 2 x 2 Part Marking X S121 YWLCP _ Note: For the most current drawing please refer to website at : Final Datasheet 12
13 Package Information PQFN 2 x 2 Tape and Reel Note: For the most current drawing please refer to website at : Final Datasheet 13
14 Qualification Information 6 Qualification Information Qualification Information Qualification Level Moisture Sensitivity Level RoHS Compliant PQFN 2 mm x 2 mm Industrial (per JEDEC JESD47F) Yes MSL1 (per JEDEC J-STD-020D) Applicable version of JEDEC standard at the time of product release. Final Datasheet 14
15 Revision History Revision History Major changes since the last revision Page or Reference Revision Date Description of changes All pages First release data sheet as Provisional. All page All pages Updated datasheet with revised package picture and outline drawings. Datasheet is released as Provisional. Added Switch Time test data. Datasheet is released as Provisional. Parts tested as Unique datasheet with revised current and all other tests Updated ds in New Infineon Template Added Link for Package Information pages 12, 13 All pages Added IR PQFN 2x2 Package Picture page 1 Datasheet completed as Approved Not Released. Datasheet is w/o Approved Not Released All pages First release data sheet on Web. All pages 2.1 Corrected typo on part marking from HS121 to S121 to matched actual marking on the devices page12 Final Datasheet 15
16 Trademarks of Infineon Technologies AG µhvic, µipm, µpfc, AU-ConvertIR, AURIX, C166, CanPAK, CIPOS, CIPURSE, CoolDP, CoolGaN, COOLiR, CoolMOS, CoolSET, CoolSiC, DAVE, DI-POL, DirectFET, DrBlade, EasyPIM, EconoBRIDGE, EconoDUAL, EconoPACK, EconoPIM, EiceDRIVER, eupec, FCOS, GaNpowIR, HEXFET, HITFET, HybridPACK, imotion, IRAM, ISOFACE, IsoPACK, LEDrivIR, LITIX, MIPAQ, ModSTACK, my-d, NovalithIC, OPTIGA, OptiMOS, ORIGA, PowIRaudio, PowIRStage, PrimePACK, PrimeSTACK, PROFET, PRO-SIL, RASIC, REAL3, SmartLEWIS, SOLID FLASH, SPOC, StrongIRFET, SupIRBuck, TEMPFET, TRENCHSTOP, TriCore, UHVIC, XHP, XMC Trademarks updated November 2015 Other Trademarks All referenced product or service names and trademarks are the property of their respective owners. Edition Published by Infineon Technologies AG Munich, Germany 2016 Infineon Technologies AG. All Rights Reserved. Do you have a question about this document? erratum@infineon.com Document reference IMPORTANT NOTICE The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics ( Beschaffenheitsgarantie ). With respect to any examples, hints or any typical values stated herein and/or any information regarding the application of the product, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation warranties of non-infringement of intellectual property rights of any third party. In addition, any information given in this document is subject to customer s compliance with its obligations stated in this document and any applicable legal requirements, norms and standards concerning customer s products and any use of the product of Infineon Technologies in customer s applications. The data contained in this document is exclusively intended for technically trained staff. It is the responsibility of customer s technical departments to evaluate the suitability of the product for the intended application and the completeness of the product information given in this document with For further information on the product, technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies office ( WARNINGS Due to technical requirements products may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies office. Except as otherwise explicitly approved by Infineon Technologies in a written document signed by authorized representatives of Infineon Technologies, Infineon Technologies products may not be used in any applications where a failure of the product or any consequences of the use thereof can reasonably be expected to result in personal injury.
I D = 34A 70 T J = 125 C V GS, Gate -to -Source Voltage (V)
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PD-97174B RADIATION HARDENED LOGIC LEVEL POWER MOSFET SURFACE-MOUNT (SMD-2) 6V, P-CHANNEL TECHNOLOGY Product Summary Part Number Radiation Level RDS(on) I D krads(si).17-56a* IRHLNA79364 3 krads(si).17-56a*
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