ABLIC Inc., 2018 Rev.1.0_00

Transcription

1 15 C OPERATION, LOW INPUT OFFSET VOLTAGE CMOS OPERATIONAL AMPLIFIER ABLIC Inc., 18 This IC incorporates a general purpose analog circuit in a small package. This is a zero-drift operational amplifier with Rail-to-Rail input and output, which uses chopper-stabilizing techniques to provide low input offset voltage. The B is a dual operational amplifier ( circuits), which is suitable for applications requiring less offset voltage. Features Low input offset voltage: Low input offset voltage drift: Operation power supply voltage range: Low current consumption (Per circuit): Low input noise voltage: Low input noise voltage density: Built-in output current limit circuit: Internal phase compensation: Rail-to-Rail input and output Operation temperature range: Lead-free (Sn %), halogen-free V IO = 5 V max. (Ta = 4 C to 15 C) V IO Ta = 5 nv/ C typ. ( = 3. V, Ta = 4 C to 15 C) = 4. V to 36. V (Single supply) =. V to 18. V (Dual supply) I DD = 5 A typ. V NOISE_pp =.8 Vpp typ. (f =.1 Hz to Hz) V NOISE = 5 nv/hz typ. (f = 1 khz) Overcurrent limit when output pin is short-circuited No external parts required Ta = 4 C to 15 C Applications High-accuracy current detection Various sensor interfaces Strain gauge amplifier Package TMSOP-8 1

2 Block Diagram VDD IN1() IN1() OUT1 IN() IN() OUT VSS Figure 1

3 Product Name Structure Refer to "1. Product name" regarding the contents of product name, ". Package" regarding the package drawings and "3. Product name list" regarding the product type. 1. Product name B A - K8T U Environmental code U: Lead-free (Sn %), halogen-free Package abbreviation and IC packing specifications *1 K8T: TMSOP-8, Tape Operation temperature A: Ta = 4C to 15C Number of circuits B:. Package *1. Refer to the tape drawing. Table 1 Package Drawing Codes Package Name Dimension Tape Reel TMSOP-8 FM8-A-P-SD FM8-A-C-SD FM8-A-R-SD 3. Product name list Product Name BA-K8TU Table TMSOP-8 Package 3

4 Pin Configuration 1. TMSOP-8 Top view Table 3 Pin No. Symbol Description Figure OUT1 Output pin 1 IN1() Inverted input pin 1 3 IN1() Non-inverted input pin 1 4 VSS GND pin 5 IN() Non-inverted input pin 6 IN() Inverted input pin 7 OUT Output pin 8 VDD Positive power supply pin 4

5 Absolute Maximum Ratings Table 4 (T j = 4 C to 15 C unless otherwise specified) Item Symbol Absolute Maximum Rating Unit Power supply voltage V SS.3 to V SS 45. V Input voltage V IN(), V IN() V SS.3 to.3 V Output voltage V OUT V SS.3 to.3 V Differential input voltage V IND.5 V Input pin current I IN. ma Junction temperature T j 4 to 15 C Operation ambient temperature T opr 4 to 15 C Storage temperature T stg 4 to 15 C Caution The absolute maximum ratings are rated values exceeding which the product could suffer physical damage. These values must therefore not be exceeded under any conditions. Thermal Resistance Value Table 5 Item Symbol Condition Min. Typ. Max. Unit Board A 16 C/W Board B 133 C/W Junction-to-ambient thermal resistance *1 JA TMSOP-8 Board C C/W Board D C/W Board E C/W *1. Test environment: compliance with JEDEC STANDARD JESD51-A Remark Refer to " Power Dissipation" and "Test Board" for details. 5

6 Electrical Characteristics 1. Recommended operation conditions Table 6 (Ta = 4 C to 15 C unless otherwise specified) Item Symbol Condition Min. Typ. Max. Unit Operation power supply voltage range. = 5. V DC Electrical Characteristics Current consumption ( circuits) V Table 7 Test Circuit (Ta = 4 C to 15 C unless otherwise specified) Item Symbol Condition Min. Typ. Max. Unit I DD V CMR = V OUT = Test Circuit 5 76 A 5 Input offset voltage V IO V CMR = 5 5 V 1 Input offset voltage drift V IO Ta V CMR = nv/c 1 Input bias current I BIAS 3 na 9, Input offset current I IO 3 na 9, Common-mode input voltage range V CMR V SS V V SS.5 V V OUT.5 V, Voltage gain (open loop) A VOL V CMR =, R 93 1 db 8 L = k Maximum output swing voltage Common-mode input signal rejection ratio Power supply voltage rejection ratio V OH V OL I SOURCE = A 4.9 V 3 I SOURCE = 1 ma 4.7 V 3 I SINK = A.1 V 4 I SINK = 1 ma.3 V 4 CMRR V SS V CMR 93 1 db PSRR 4. V 36. V db 1 Source current I SOURCE V OUT =.1 V.4.6 ma 6 Sink current I SINK V OUT =.1 V.5.5 ma 7 Output pin short-circuit current (source) Output pin short-circuit current (sink) I SHORT_SOURCE V OUT = V 16. ma I SHORT_SINK V OUT = 15. ma 6

7 Table 8 AC Electrical Characteristics (Ta = 4 C to 15 C unless otherwise specified) Item Symbol Condition Min. Typ. Max. Unit Slew rate SR R L = 1. M, C L = 15 pf (Refer to Figure 13 and Figure 14), V IN() = 1.5 V 3.5 V.45 V/s Gain-bandwidth product GBP C L = pf 1. MHz Maximum load capacitance C L 47 pf Input noise voltage V NOISE_pp f =.1 Hz to Hz.8 Vpp Input noise voltage density V NOISE f = 1 khz 5 nv/hz 7

8 3. = 3. V DC Electrical Characteristics Current consumption ( circuits) Table 9 (Ta = 4 C to 15 C unless otherwise specified) Item Symbol Condition Min. Typ. Max. Unit I DD V CMR = V OUT = Test Circuit 5 76 A 5 Input offset voltage V IO V CMR = 5 5 V 1 Input offset voltage drift V IO Ta V CMR = 5 nv/c 1 Input bias current I BIAS 3 na 9, Input offset current I IO 3 na 9, Common-mode input voltage range Voltage gain (open loop) Maximum output swing voltage Common-mode input signal rejection ratio Power supply voltage rejection ratio V CMR V SS V A VOL V OH V OL V SS.5 V V OUT.5 V, V CMR =, R L = k 6 db 8 I SOURCE = A 9.9 V 3 I SOURCE = 1 ma 9.7 V 3 I SINK = A.1 V 4 I SINK = 1 ma.3 V 4 CMRR V SS V CMR 6 db PSRR 4. V 36. V db 1 Source current I SOURCE V OUT =.1 V.4.6 ma 6 Sink current I SINK V OUT =.1 V.5.5 ma 7 Output pin short-circuit current (source) Output pin short-circuit current (sink) I SHORT_SOURCE V OUT = V 16. ma I SHORT_SINK V OUT = 15. ma 8

9 Table AC Electrical Characteristics (Ta = 4 C to 15 C unless otherwise specified) Item Symbol Condition Min. Typ. Max. Unit Slew rate SR R L = 1. M, C L = 15 pf (Refer to Figure 13 and Figure 14), V IN() = 14. V 16. V.45 V/s Gain-bandwidth product GBP C L = pf 1. MHz Maximum load capacitance C L 47 pf Input noise voltage V NOISE_pp f =.1 Hz to Hz.8 Vpp Input noise voltage density V NOISE f = 1 khz 5 nv/hz 9

10 Test Circuits (Per circuit) 1. Power supply voltage rejection ratio, input offset voltage, input offset voltage drift Power supply voltage rejection ratio (PSRR) R F The power supply voltage rejection ratio (PSRR) can be calculated by the following expression, with V OUT measured at each. R S R S V OUT Test conditions: = 4. V: = 1, V OUT = V OUT1 = 36. V: =, V OUT = V OUT V CMR = VDD R F Figure 3 Test Circuit 1 PSRR = log Input offset voltage (V IO ) V IO = V OUT 1 V OUT1 1 V OUT R S R F R S R FR S R S Input offset voltage drift V IO Ta The input offset voltage drift V IO can be calculated by the Ta following expression, with V OUT measured at each temperature. Test conditions: Ta = 4C: V IO = V IO1 Ta = 15C: V IO = V IO V IO Ta = V IO V IO1 15C (4C). Common-mode input signal rejection ratio, common-mode input voltage range Common-mode input signal rejection ratio (CMRR) R F The common-mode input signal rejection ratio (CMRR) can be calculated by the following expression, with V OUT measured at each V IN. R S R S V OUT Test conditions: V IN = V CMR Max. : V IN = V IN1, V OUT = V OUT1 V IN = V CMR Min. : V IN = V IN, V OUT = V OUT V IN R F CMRR = log V IN1 V IN V OUT1 V OUT R FR S R S Common-mode input voltage range (V CMR ) Figure 4 Test Circuit The common-mode input voltage range is the range of V IN in which V OUT satisfies the common-mode input signal rejection ratio specifications when V IN is changed.

11 3. Maximum output swing voltage Maximum output swing voltage (V OH ) V OH Test conditions: V IN1 =.1 V V IN =.1 V I SOURCE = A, 1 ma I SOURCE V IN1 V IN Figure 5 Test Circuit 3 4. Maximum output swing voltage I SINK V OL Maximum output swing voltage (V OL ) Test conditions: V IN1 =.1 V V IN =.1 V I SINK = A, 1 ma V IN1 V IN Figure 6 Test Circuit 4 5. Current consumption Current consumption (I DD ) A V CMR = VDD Figure 7 Test Circuit 5 11

12 6. Source current Source current (I SOURCE ) A Test conditions: V OUT =.1 V V IN1 =.1 V V IN =.1 V V IN1 V IN V OUT Figure 8 Test Circuit 6 7. Sink current V OUT Sink current (I SINK ) A Test conditions: V OUT =.1 V V IN1 =.1 V V IN =.1 V V IN1 V IN Figure 9 Test Circuit 7 8. Voltage gain Voltage gain (open loop) (A VOL ) R F N The voltage gain (A VOL ) can be calculated by the following expression, with V OUT measured at each V M. R S R S D.U.T NULL V OUT Test conditions: V M =.5 V: V M = V M1, V OUT = V OUT1 V M = V SS.5 V: V M = V M, V OUT = V OUT R F V CMR = R L V M V SSN A VOL = log R L = k V M1 V M V OUT1 V OUT R F R S R S Figure Test Circuit 8 1

13 9. Input bias current, input offset current Input bias current (I BIAS ) Test conditions: IN() pin input bias current (I BIAS() ) = 1 (V OUT ) R B R B V OUT IN() pin input bias current (I BIAS() ) = V OUT R B I BIAS = I BIAS() I BIAS() V CMR = VDD Figure 11 Test Circuit 9 Input offset current (I IO ) I IO = I BIAS() I BIAS() R B V OUT V CMR = VDD Figure 1 Test Circuit 13

14 . Slew rate V IN() R L = 1. M V OUT C L = 15 pf Figure 13 Test Circuit 11 V IN() 1. V 1. V t R = t F = ns ( V/s) t THL Slew rate (SR) When falling SR = 1.6 V t THL When rising SR = 1.6 V t TLH V OUT (= V IN() ) t TLH ( ( 1. V).8 1. V).8 Figure 14 14

15 Precautions Generally an operational amplifier may cause oscillation depending on the selection of external parts. Perform thorough evaluation using the actual application to set the constants. Do not apply an electrostatic discharge to this IC that exceeds performance ratings of the built-in electrostatic protection circuit. ABLIC Inc. claims no responsibility for any disputes arising out of or in connection with any infringement by products including this IC of patents owned by a third party. This IC operates stably even directly connecting a load capacitance of 47 pf or less to the output pin, as shown in Figure 15. When connecting a load capacitance of 47 pf or more, connect a resistor of or more as shown in Figure 16. In case of connecting a filter for noise prevention, and connecting a load capacitance of 47 pf or more, also connect a resistor of or more as shown in Figure 17. V IN V IN V OUT Load capacitance 47 pf or less V SS Figure 15 V IN V OUT V IN or more V SS Load capacitance Figure 16 Filter V IN V OUT or more V IN Load capacitance V SS Figure 17 Caution The above connection diagrams and constants will not guarantee successful operation. Perform thorough evaluation using the actual application to set the constants. 15

16 Precaution for use 1. Methods for protection against application of overvoltage to input pin ESD protection elements are connected to the input pins as shown in Figure 1. If the input voltage (V IN ) exceeds the V IN absolute maximum rating.3 V, there is a risk of the input pin current which flows through the ESD protection element exceeding. ma (the absolute maximum rating). In this case, connect a current limiting resistor (R LIMT ) to the input pin as shown in Figure 18 to limit the input pin current to less than. ma. However, error voltage and noise generate as a result of input bias current and input offset current. Select the lowest possible resistance when connecting the R LIMT. V IN R LIMT V OUT Figure 18. Input voltage range (input crossover distortion) This IC has two sets of differential circuits in order to achieve the Rail-to-Rail input voltage range. The differential circuits used switch based on the common-mode input voltage range (V CMR ). Differences in the characteristics of the two sets of differential circuits result in the generation of distortion of the output voltage which is referred to as "input crossover distortion" when the differential circuits switch. The differential circuit switching voltage of this IC is approximately between. V and 1. V. When using this IC in applications which require high-accuracy measurement, avoid the range near the differential circuit switching voltage in order to avoid changes in input offset voltage caused by input crossover distortion and changes in input offset voltage drift. This IC is a chopper-stabilized zero-drift amplifier; therefore, it always cancels input offset voltage. For this reason, the input crossover distortion is kept extremely small when compared to standard operational amplifiers. However, please contact our sales office when using this IC near the differential circuit switching voltage. Refer to "8. Input offset voltage (V IO ) vs. Common-mode input voltage range (V CMR )" in " Characteristics (Typical Data)". Input range Approximately. V to 1. V Output circuit Distortion Differential circuit 1 Differential circuit Figure 19 16

17 3. Recommended processing methods for unused circuit When using only a single circuit of this IC, it is recommended that the unused circuit be connected as shown in Figure. Set the non-inverted input pin voltage (V IN() ) within the common-mode input voltage range (V CMR ). V OUT V IN() = V SS to Figure 17

18 Characteristics (Typical Data) 1. Current consumption (I DD ) (Per circuit) vs. Power supply voltage ( ) IDD [A] 4 3 Ta = 15C Ta = 5C Ta = 4C VDD [V] 3 4. Voltage gain (A VOL ) vs. Frequency (f) = 4. V AVOL [db] Ta = 15C Ta = 5C Ta = 4C f [khz] AVOL [db] = 18. V Ta = 15C Ta = 5C Ta = 4C f [khz] AVOL [db] = 36. V Ta = 15C Ta = 5C Ta = 4C f [khz] 18

19 3. Output current 3. 1 Source current (I SOURCE ) vs. Power supply voltage ( ) V OUT =.1 V, V SS = V ISOURCE [ma] Ta = 4C 4..6 Ta = 5C Ta = 15C VDD [V] 3. Sink current (I SINK ) vs. Power supply voltage ( ) ISOURCE [ma] V OUT =.5 V, V SS = V Ta = 4C Ta = 5C Ta = 15C VDD [V] V OUT = V SS.1 V, V SS = V 6. V OUT = V SS.5 V, V SS = V ISINK [ma] Ta = 4C Ta = 5C ISINK [ma] Ta = 4C Ta = 5C.. VDD [V] Ta = 15C VDD [V] Ta = 15C Output voltage (V OUT ) vs. Source current (I SOURCE ) VOUT [V] Ta = 15C = 4. V, V SS = V Ta = 4C Ta = 5C VOUT [V] 15 5 Ta = 15C = 18. V, V SS = V Ta = 4C Ta = 5C ISOURCE [ma] ISOURCE [ma] 5 4 = 36. V, V SS = V VOUT [V] 3 Ta = 4C Ta = 5C Ta = 15C 5 15 ISOURCE [ma] 5 19

20 3. 4 Output voltage (V OUT ) vs. Sink current (I SINK ) VOUT [V] = 4. V, V SS = V Ta = 15C Ta = 5C Ta = 4C 15 ISINK [ma] 5 VOUT [V] 15 5 Ta = 15C Ta = 5C Ta = 4C 5 = 18. V, V SS = V 15 ISINK [ma] 5 VOUT [V] 4 3 Ta = 15C Ta = 5C Ta = 4C = 36. V, V SS = V 5 15 ISINK [ma] 5 4. Input bias current (I BIAS ) vs. Temperature (Ta) = 36. V 75 IBIAS [na] Ta [C]

21 5. Input noise voltage density (V NOISE ) vs. Frequency (f) = 4. V, V SS = V Ta = 15C = 18. V, V SS = V Ta = 15C VNOISE [nv/ Hz] Ta = 5C Ta = 4C VNOISE [nv/ Hz] Ta = 5C Ta = 4C f [khz] f [khz] VNOISE [nv/ Hz] = 36. V, V SS = V Ta = 15C Ta = 5C Ta = 4C f [khz] 6. Input pin current (I IN ) vs. Differential input voltage (V IND ) = 36. V, V SS = V IIN [A] Ta = 4C Ta = 5C Ta = 15C VIND [V]

22 7. Input offset voltage (V IO ) vs. Power supply voltage ( ) 5 V SS = V, V CMR = / VIO [V] VDD [V] 3 4 Remark Measured six samples 8. Input offset voltage (V IO ) vs. Common-mode input voltage range (V CMR ) 5 = 4. V, V SS = V 5 = 16. V, V SS = V 5 5 VIO [V] 5 VIO [V] VCMR [V] VCMR [V] 15 5 = 36. V, V SS = V VIO [V] VCMR [V] 3 4 Remark Measured four samples

23 9. Voltage gain (open loop) (A VOL ) vs. Temperature (Ta) 16 = 4. V, V SS = V 16 = 18. V, V SS = V AVOL [db] 14 AVOL [db] Ta [C] Ta [C] 16 = 36. V, V SS = V AVOL [db] Ta [C]. Power supply voltage rejection ratio (PSRR) vs. Temperature (Ta) 16 PSRR [db] Ta [ C] 3

24 11. Common-mode input signal rejection ratio (CMRR) vs. Temperature (Ta) 16 = 4. V, V SS = V 16 = 18. V, V SS = V CMRR [db] 14 CMRR [db] Ta [ C] Ta [ C] 16 = 36. V, V SS = V CMRR [db] Ta [ C] 4

25 1. Step response (Slew rate) 1. 1 Input signal width (.4 V) V IN() = 1.8 V. V V IN() = 8.8 V 9. V VIN, VOUT [V] = 4. V, V SS = V VIN VOUT, Ta = 15C VOUT, Ta = 5C 3 t [s] VOUT, Ta = 4C VIN, VOUT [V] = 18. V, V SS = V VIN VOUT, Ta = 15C VOUT, Ta = 5C 3 t [s] VOUT, Ta = 4C V IN() = 17.8 V 18. V VIN, VOUT [V] = 36. V, V SS = V VIN VOUT, Ta = 15C VOUT, Ta = 5C 3 t [s] VOUT, Ta = 4C

26 1. Input signal width (4. V) V IN() = V 4. V 1.. V IN() = 7. V 11. V 5 4 = 4. V, V SS = V VOUT, Ta = 4C 1 11 = 18. V, V SS = V VOUT, Ta = 4C VIN, VOUT [V] VIN VOUT, Ta = 5C 3 4 t [s] VIN, VOUT [V] VIN VOUT, Ta = 5C 3 4 t [s] V IN() = 16. V. V 1 = 4. V, V SS = V VOUT, Ta = 4C VIN, VOUT [V] VIN VOUT, Ta = 5C 3 4 t [s] Input signal width (V SS ) V IN() = V 18. V V IN() = V 36. V = 18. V, V SS = V 4 = 36. V, V SS = V VIN, VOUT [V] VIN VOUT, Ta = 4C VOUT, Ta = 5C 3 4 t [s] VIN, VOUT [V] 3 VIN VOUT, Ta = 4C VOUT, Ta = 5C t [s] 14 6

27 13. Input offset voltage distribution = 5. V, V SS = V, Ta = 5 C = 3. V, V SS = V, Ta = 5 C 5 5 Percentage [%] 4 3 Percentage [%] VIO [V] VIO [V] Input offset voltage drift distribution Percentage [%] = 5. V, V SS = V, Ta = 4 C to 15 C Percentage [%] = 3. V, V SS = V, Ta = 4 C to 15 C VIO/Ta [nv/c] VIO/Ta [nv/c] 14 7

28 Power Dissipation TMSOP-8 Power dissipation (PD) [W] B A Tj = 15C max Ambient temperature (Ta) [C] Board Power Dissipation (P D ) A.78 W B.94 W C D E 8

29 TMSOP-8 Test Board (1) Board A IC Mount Area Item Specification Size [mm] x 76. x t1.6 Material FR-4 Number of copper foil layer 1 Land pattern and wiring for testing: t.7 - Copper foil layer [mm] x 74. x t.7 Thermal via - () Board B Item Specification Size [mm] x 76. x t1.6 Material FR-4 Number of copper foil layer 4 1 Land pattern and wiring for testing: t x 74. x t.35 Copper foil layer [mm] x 74. x t x 74. x t.7 Thermal via - No. TMSOP8-A-Board-SD-1. ABLIC Inc.

30

31

32

33 Disclaimers (Handling Precautions) 1. All the information described herein (product data, specifications, figures, tables, programs, algorithms and application circuit examples, etc.) is current as of publishing date of this document and is subject to change without notice.. The circuit examples and the usages described herein are for reference only, and do not guarantee the success of any specific mass-production design. ABLIC Inc. is not responsible for damages caused by the reasons other than the products described herein (hereinafter "the products") or infringement of third-party intellectual property right and any other right due to the use of the information described herein. 3. ABLIC Inc. is not responsible for damages caused by the incorrect information described herein. 4. Be careful to use the products within their specified ranges. Pay special attention to the absolute maximum ratings, operation voltage range and electrical characteristics, etc. ABLIC Inc. is not responsible for damages caused by failures and / or accidents, etc. that occur due to the use of the products outside their specified ranges. 5. When using the products, confirm their applications, and the laws and regulations of the region or country where they are used and verify suitability, safety and other factors for the intended use. 6. When exporting the products, comply with the Foreign Exchange and Foreign Trade Act and all other export-related laws, and follow the required procedures. 7. The products must not be used or provided (exported) for the purposes of the development of weapons of mass destruction or military use. ABLIC Inc. is not responsible for any provision (export) to those whose purpose is to develop, manufacture, use or store nuclear, biological or chemical weapons, missiles, or other military use. 8. The products are not designed to be used as part of any device or equipment that may affect the human body, human life, or assets (such as medical equipment, disaster prevention systems, security systems, combustion control systems, infrastructure control systems, vehicle equipment, traffic systems, in-vehicle equipment, aviation equipment, aerospace equipment, and nuclear-related equipment), excluding when specified for in-vehicle use or other uses. Do not apply the products to the above listed devices and equipments without prior written permission by ABLIC Inc. Especially, the products cannot be used for life support devices, devices implanted in the human body and devices that directly affect human life, etc. Prior consultation with our sales office is required when considering the above uses. ABLIC Inc. is not responsible for damages caused by unauthorized or unspecified use of our products. 9. Semiconductor products may fail or malfunction with some probability. The user of the products should therefore take responsibility to give thorough consideration to safety design including redundancy, fire spread prevention measures, and malfunction prevention to prevent accidents causing injury or death, fires and social damage, etc. that may ensue from the products' failure or malfunction. The entire system must be sufficiently evaluated and applied on customer's own responsibility.. The products are not designed to be radiation-proof. The necessary radiation measures should be taken in the product design by the customer depending on the intended use. 11. The products do not affect human health under normal use. However, they contain chemical substances and heavy metals and should therefore not be put in the mouth. The fracture surfaces of wafers and chips may be sharp. Be careful when handling these with the bare hands to prevent injuries, etc. 1. When disposing of the products, comply with the laws and ordinances of the country or region where they are used. 13. The information described herein contains copyright information and know-how of ABLIC Inc. The information described herein does not convey any license under any intellectual property rights or any other rights belonging to ABLIC Inc. or a third party. Reproduction or copying of the information from this document or any part of this document described herein for the purpose of disclosing it to a third-party without the express permission of ABLIC Inc. is strictly prohibited. 14. For more details on the information described herein, contact our sales office