Research Article Efficient Integration of Pipelined IP Blocks into Automatically Compiled Datapaths

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1 Hindwi Pulishing Corportion EURASIP Journl on Emedded Systems Volume 27, Article ID 6573, 9 pges doi:.55/27/6573 Reserch Article Efficient Integrtion of Pipelined IP Blocks into Automticlly Compiled s Andres Koch Emedded Systems nd Applictions Group, Technicl University of Drmstdt, FB2, Hochschulstrße, Drmstdt, Germny Received 4 My 26; Revised 4 August 26; Accepted 4 Septemer 26 Recommended y Juergen Teich Compilers for reconfigurle computers im to generte prolem-specific optimized dtpths for kernels extrcted from n input lnguge. In mny cses, however, judicious use of preexisting mnully optimized IP locks within these dtpths could improve the compute performnce even further. The integrtion of IP locks into the compiled dtpths poses different set of prolems thn stitching together IPs to form system-on-chip; though, insted of the loose coupling using stndrd usses employed y SoCs, the one etween dtpth nd IP lock must e much tighter. To this end, we propose concise lnguge tht cn e efficiently synthesized using templte-sed pproch for utomticlly generting lightweight dt nd control interfces t the dtpth level. Copyright 27 Andres Koch. This is n open ccess rticle distriuted under the Cretive Commons Attriution License, which permits unrestricted use, distriution, nd reproduction in ny medium, provided the originl work is properly cited.. INTRODUCTION Automtic high-level lnguge compilers [, 2] re one of the prime mens to mke the compute power of reconfigurle computers ville to developers. However, despite the progress in such compile flows, the generted hrdwre often does not rech the qulity of designs crefully optimized y n expert designer. Thus, it ecomes desirle to tightly integrte optimized custom IP locks with the compiler-generted dtpth. While this mixed method is still new in the world of hrdwre design, it hs een estlished for decdes in the softwre re. There, it is quite common to cll highly optimized ssemly code lirries (e.g., for mth or grphics) from high-level progrmming lnguges. Thnks to well-defined inry interfce nd clling conventions, crossstrction level clls re esily performed. For hrdwre design, the sitution is much more complex. One of the resons ppers to e the incresed flexiility of custom hrdwre compred to fixed-function processor: the sme functionlity cn e relized in dedicted hrdwre in mny different wys nd thus e perfectly mtched to the rest of the system environment. However, utomticlly uilding complete system-onchip from these disprte components is difficult. While some ttempts hve een mde to stndrdize on-chip communictions [3 5], they hve not chieved totl success. Mny IP locks still do not use one of these proposed stndrd interfces, ut insted rely on their own custom interfces, which hve to e wrpped efore connecting to stndrd us. Furthermore, when compiling n ccelertor unit for reconfigurle computer, the generted hrdwre should fully exploit the dptive nture of the trget rchitecture: reconfigurility llows the use of highly efficient prolemspecific hrdwre structures, insted of the more generl pproches (e.g., networks-on-chip) tht re often used in the ASIC world. Thus, insted of using generl-purpose communictions structure to ssemle system-on-chip, we re iming for the tight integrtion of lrger numer of smller IP locks directly into the compiled dtpths. For this pplictions, the stndrd usses mentioned ove re generlly too hevyweight, with specilized high-ndwidth lowltency point-to-point connections eing fr preferle. One of the tsks tht hs to e performed to chieve this gol is the cretion of interfce controllers tht trnslte from the vrious IP-specific protocols for initiliztion, dt exchnge, nd so forth, to common protocol comptile with the centrl dt pth controller. Idelly, the cretion of the

2 2 EURASIP Journl on Emedded Systems wrppers should e performed on-the-fly during hrdwre compiltion, without requiring time-consuming HDL-sed synthesis steps. However, the wrppers must e cple of hndling even complex control schemes nd pipelined opertion. Prior work [6, 7] hs lredy detiled the UCODE, simple lnguge for concisely descriing such interfce controllers. We now contriute novel wy to quickly synthesize hrdwre from UCODE: sucircuit templte is ssocited with ech kind of UCODE instruction; these templtes re then composed following the UCODE description to uild the entire interfce controller circuit. As will e shown in Section 6, re/timetrdeoffs cnesilyeperformed y chnging the templtes nd mpping rules. Opertor Opertor Opertor Locl controllers IP lock Wrpper Glol controller Compiled dtpth Opertor Opertor Dt flow 2. RELATED WORK Flexily connecting mismtched interfces hs een the suject of mny reserch efforts. The pproches rnge from constructing product FSMs to uild protocol converters [8] using lirries of interfce modules [9, ] to extrcting event grphs from timing digrms []. A good overview nd forml model of the prolem cn e found in [2]. However, none of these methods mtches our scenrio of tightly integrting preexisting IP locks into utomticlly compiled dtpths. For this tight degree of coupling, the FI- FOs proposed in [3] re inpproprite. In our usge scenrio, FIFOs for ech IP lock would inordintely increse the ltency of the entire dt pth. Thus, our pproch ims to void the introduction of dditionl dely elements. Another common pproch [3, 4] relies on extrcting the interfce description from the HDL code of the IP locks. With the incresing use of encrypted soft-cores or netlistonly firm cores, this pproch ecomes rther imprcticl. To void these difficulties, we rely on UCODE s n IP-externl description of interfce chrcteristics. Pipelining, feture crucil for high throughput dtpths, is lso often lcking from the pproches listed here. Therehveeensomeefforts to pply dt-flow-sed pproch to the prolem, ut they sometimes lck flexiility. For exmple, the technique in [5] cn only hndle sttic dt-flow nd requires fixed send-receive protocol. Other work, such s [6], is more flexile, ut does not cover the direct hrdwre mpping of the descried primitives. In this text, we extend UCODE s flexile description for interfce protocols with n efficient mpping onto ctul hrdwre. 3. TARGET ARCHITECTURE Our ppliction setting is shown in Figure. IP locks re to e inserted into compiler-generted dtpth y utomticlly synthesizing thin wrpper oth on the dt nd the control sides, connected using dedicted point-to-point links to the dtpth nd the glol controller. This glol controller is responsile for higher-level control decisions (e.g., switching n IP lock into nother operting mode, strting/cnceling specultive execution). The wrpper controller in turn cts on lower level nd orchestrtes the control sequencing nd dt exchnge within function selected y the glol controller. On the dt side, the formts used in Control flow Figure : Appliction scenrio. the dtpth nd on the IP lock re ssumed to e mostly comptile. However, minor trnsformtions, such s serilto-prllel conversions, us (de)composition, nd physicllogicl port renming re supported in the wrpper. The following sections will discuss how to concisely descrie the wrpper function, the mnner of integrtion with the glol controller, the ctul templte-sed synthesis, nd optimized mpping of the strct circuit to rel hrdwre. 4. INTERFA DESCRIPTION Similr to the pproch in [4, 6], we compose the descriptions of the controller functions from smll numer of primitives. However, we lso llow the description of pipelining, port renming, nd emedded wired logic. All of our primitives (clled UCODEs) hve een defined in terms of underlying strct hrdwre functions. These templtes cn e composed nd then efficiently mpped to the trget rchitecture (ut not necessrily exctly s depicted, see Section 6). When new IP lock is prepred for utomtic integrtion, it is the tsk of humn expert to uthor the corresponding UCODE descriptions for the vrious cpilities of the lock. These descriptions will generlly e mnully extrcted from the dt sheets nd mnuls delivered y the IP vendor. In this work, we concentrte on the low-level description nd templte-sed synthesis of the wrpper. The complete specifiction [7] lso covers higher-level constructs such s initiliztion, prllel/seril execution modes, nd so forth. 4.. Compute model Despite the hrdwre-centric formultion of our controller ehvior, the underlying model of computtion hs forml roots in Petri nets: the presence of (logic ) indictes n ctive stte, multiple sttes my e ctive t the sme time, nd s my e creted, deleted, nd rerouted during the controller execution. All of our primitives ccept

3 Andres Koch 3 io := iomode [{ portmp }]; iomode := io com io seq ; ; io com := LEVEL ; io seq := ( NEGEDGE ) [repet]; repet := count; count := crdinl; portmp := ( physport logport ) ; physport := port literl; logport := port literl; literl := crdinl; port := nme [ [ [ms : ] ls ] ]; ms := crdinl; ls := crdinl; Figure 2: Input/Output primitives., mny lso propgte it (possily fter modifiction). The glol controller ctivtes wrpper controller y injecting n initil into the first stte. In similr fshion, leving the finl stte cn indicte completion of the wrpper opertion nd trnsfer control ck to the glol controller. Pipelining, however, requires dditionl infrstructure (descried in Section 5) Input/Output Compred to [4], I/O hs een unified here (no distinction is mde etween control nd dt) nd extended (we explicitly model time, currently defined y edges of single clock domin). The I/O opertions shown in Figure 2 re initilly distinguished y whether they operte comintionlly or sequentilly. In the first cse, the UCODE sttement LEVEL is used, in the second one, the nd NEGEDGE sttements will e employed. The ltter differentite etween synchronizing to the rising or flling edge of the centrl clock. Note tht the textul syntx shown here is purely humn-redle convenience. After it hs een written to descrie specific IP lock, UCODE is only hndled within design tools, nd cn thus e represented more efficiently in inry form. For exmple, our current implementtion of UCODE-sed tool flow ctully uses Jv oject grphs for efficient storge nd mnipultion of the UCODE descriptions: the progrms re stored s sequences of sttement ojects; nd textul references, for exmple, to I/O ports, hve een replced y direct references to the corresponding design dtse ojects. Figure 3 shows n exmple for such UCODE frgment emedded in Jv. The frgment shown descries the memory write opertion of vlue dtin to ddress ddr viccheinterfce[7]. As primry rguments, ech of the primitives tkes set of portmp pirs, ech pir ssociting physicl port with logiclportonusorsuussis.suchpirrepresents permnent (wire) or temporry (muxed/demuxed) connection etween the two ports. Alterntively, one of the ports my e replced y constnt literl. This indictes the ppliction of the literl vlue to the remining port of the pir. Figure 4 shows the underlying hrdwre templtes of the sequentil opertors. When the stte is ctivted y n rriving, the ssocited ction occurs: in the input cse (), the selected logicl input port is pplied to the specified physicl port of the IP lock in time to e smpled for the next clock edge. In the control cse (), the presence of the indictes the ppliction of literl vlue (generted y the literl logic) to one or more physicl ports of the IP Block. Finlly, in the output cse (c), the given physicl output port is pplied to the selected logicl output to e smpled into dtpth register t the next clock edge. After the clock edge, indicted y the UCODE, the is then propgted. The comintionl I/O opertions depicted in Figure 5 operte similrly. The crucil difference is the now purely comintionl nture of the opertion (no time steps s defined y clock edges pss). It is ovious tht the finl logic locks controlling the multiplexers nd the dtpth control inputs must e composed y merging the logic locks of ll UCODEs tht pply to the sme port. Consider the following exmple: ssume tht n IP lock implements the logicl ehvior mul(prod,,). The physicl interfce, however, hs single input port D. Both the multiplictor nd the multiplicnd re loded into the lock through this single port, ut on successive clock cycles. The loding process must e strted y rising the control input S. After ccepting the multiplicnd, the result ecomes vlid on the physicl output port Y four clocks lter nd cn then e smpled ck into the dtpth on the following clock edge. Figure 6 shows the UCODE description of oth the control nd dt interfces in the wrpper. The strct (technology independent) circuit for this description cn e generted simply y composing the templtes nd merging the logic locks (Figure 7). Due to the simplicity of the exmple, the logic locks re trivil or hve even een optimized wy entirely (e.g., since there is - mpping of the physicl port Y to the logicl port prod, no demultiplexer nd ssocited control logic re required). The hrdwre ws composed y chining the circuits underlying the UCODE primitives vi their inputs nd outputs. For ech primitive, the form pproprite for dt (ports D, Y) or control (port S) mnipultion is employed. The shift nd wired logic opertions mentioned in Section 4 re relized y offsetting the ms nd ls indices of physicl nd logicl ports ginst ech other. The UCODE in Figure 8() sign-extends the 4 physicl port D to mp to the 8 logicl port x. In similr fshion, split ports my e hndled. The code in Figure 8() ssemles two physicl ports to mp to wider logicl port. The expression in Figure 8(c) converts 22 word ddress on PA to yte-oriented ddress ddr Control flow While the I/O primitives cn lredy hndle simple IP locks on their own, mny locks hve more complex interfcing requirements. Two of the most common ones re hndshking

4 4 EURASIP Journl on Emedded Systems //UCODE for cche write opertion Seq ucwrite = newfseq(); //creteemptysequenceofucodeojects ucwrite.ct ( // comintionlly pply dt nd control signls new Level ( new FSeq ( new PortVlue (CACHE OE, ), new PortVlue (CACHE WE, ), new PortPort (CACHE ADDR, ddr), new PortPort (new BusPort (CACHE WIDTH 6BIT), new BusPort (width, )), new PortPort (new BusPort (CACHE WIDTH 8BIT), new BusPort (width, )), new PortPort (CACHE WRITE, dtin)))); ucwrite.ct ( // wit for cche port redy new Continue (new PortVlue (CACHE STALL, ))); ucwrite.ct ( // signls must e kept stle to next edge for smpling y cche port new PosEdge (new FSeq ( new PortVlue (CACHE OE, ), new PortVlue (CACHE WE, ), new PortPort (CACHE ADDR, ddr), new PortPort (new BusPort (CACHE WIDTH 6BIT), new BusPort (width, )), new PortPort (new BusPort (CACHE WIDTH 8BIT), new BusPort (width, )), new PortPort (CACHE WRITE, dtin)))); Figure 3: Exmple for UCODE emedded in Jv. nd (closely relted) vrile execution times (ltencies). For these cses, the strightline execution of the I/O UCODEs no longer suffices. The CONTINUE UCODE shown in Figure 9 is similr to the wit for event primitive in [4], ut extends the concept y llowing logicl expressions in sum-of-products form. Ech portequls sttes tht the indicted physicl port (or it surnge thereof) must e equl to the given literl vlue. The UCODE wits in the current I/O stte until ll conditions within CONTINUE ecome true (logicl product), or thtny of group of successive CONTINUE primitives mtch (logicl sum). The hrdwre templtes underlying this UCODE re shown in Figure. The condition logic is derived y ANDing the conditions within ech CONTINUE nd ORing these seprte outputs for successive CONTINUE sttements. The sttement opertes y routing n incoming ck to the lst ctive I/O sttement. Only if the joint condition of ll successive CONTINUE sttements ecomes true, will the continue pst the UCODE to the next sttement. The CONTINUE itself is purely comintionl. A synchronous mode of execution cn e chieved y following the CONTINUE with one of the sequentil I/O sttements or NEGEDGE. As n exmple, reconsider the integrtion of the Mult 6 6 IP lock of the previous section. But here, insted of the fixed ltency of four clock cycles, the IP lock indictes the vilility of result in time for the next rising clock edge using on the physicl port R. The corresponding UCODE frgment is shown in Figure, the corresponding hrdwre in Figure 2. The ck-edge of the CONTINUE sttement routes the to the input of previous I/O sttement (the second of the frgment). Due to the trivil condition, the condition logic collpses to single wire from R to the CONTINUE hrdwre. In more complex ppliction, the logic would hold the sum-of-products reliztion of the intr- nd inter-sttement conditions Pipelining For our ppliction of tightly integrting n IP lock into hevily pipelined dtpth, it is crucil to e le to descrie pipelining chrcteristics. Specificlly, we wnt to e le to model the prologue, the stedy-stte, nd the epilogue of pipelined IP lock. START, shown in Figure 3, seprtes the prologue from the stedy stte. It lso merges n incoming from the ck-edge into the forwrd direction (eginning the next pipeline itertion). RESTART (Figure 4) indictes the eginning of the epilogue nd duplictes n incoming : one copy is pssed forwrd into the epilogue of the pipeline itertion, the other copy is pssed ckwrd into the START circuitry, eginning the next pipeline itertion in the stedy-stte. RESTART effectively cretes new thred of execution which results in multiple sttes ecoming ctive in prllel (Petri net-like). Figure 5 shows the pipeline modeled y these UCODEs.

5 Andres Koch 5 Phys. in IP lock Phys. out Log out Select logic register Select logic Literl logic D Q D Q () Dt input interfce () Control interfce (c) Dt output interfce Figure 4: Sequentil I/O templtes. Phys. in IP lock Phys. out Log out Select logic Select logic register Literl logic () Dt input interfce () Control interfce (c) Dt output interfce Figure 5: Comintionl I/O templtes. Only one START/RESTART como my exist within UCODE progrm. This construct is the only wy to ctully iterte within the wrpper controller. All other loops must e relized in the glol controller y repetedly ctivting the wrpper controller. Furthermore, exploiting pipeline prllelism requires dditionl circuitry round the wrpper controller for clenly terminting (drining) the pipeline. This will e discussed in Section 5. To give n exmple on the use of pipelining, we will sty with our regulr multiplier, ut posit this time tht it hs totl ltency of seven cycles (including loding the opernds) nd llows pipelined opertion with n initition intervl of four cycles (then the next opernds cn e loded). The UCODE description in Figure 6 models this ehvior. This UCODE frgment hs n empty prologue, ut the stedy-stte nd epilogue follow the model of Figure 5.The corresponding hrdwre is shown in Figure PIPELINE ADMINISTRATION The strct wrpper circuits creted from the UCODE templtes cn e modified to optionlly provide dditionl cpilities for the glol controller. These extensions include clenly stopping the pipeline nd witing for it to drin. For clrity of the following figures, we show only the strct stte flip-flops, ut omit the comintionl logic (e.g., for CONTINUE sttements) in etween. 5.. Stopping the pipeline This functionlity is provided y dding glol-controller mnipulted input LstIn into the ck-edge from RESTART to START vi n AND with inverted input (Figure 8()). It is crucil tht this gte is inserted directly preceding the D input of the strct flip-flop, otherwise the control signls generted y this or NEGEDGE sttement (the mux control in the figure) would ecome invlid premturely. By sserting LstIn simultneously with the ppliction of the lst set of input dt, the finl pipeline itertion will e strted Drining the pipeline With vrile-ltency elements in the pipeline, it ecomes difficult for the glol controller to determine when the

6 6 EURASIP Journl on Emedded Systems (S ) (D[5 : ] [5 : ]); (S ) (D[5 : ] [5 : ]); ; ; ; ; (Y[3 : ] prod[3 : ]); (S ) (D[5 : ] [5 : ]); (S ) (D[5 : ] [5 : ]); CONTINUE (R ); (Y[3 : ] prod[3 : ]); Figure 6: UCODE for multiplier exmple. Figure : UCODE for vrile ltency multiplier. Mult6 6 D Y S Prod Mult6 6 D Y S R Prod DQ Strt DQ DQ DQ DQ DQ DQ DQ Finish Strt DQ DQ DQ Finish Figure 7: Wrpper for multiplier IP lock. Figure 2: Wrpper for vrile ltency multiplier. () (D[3] x[7]) (D[3] x[6]) (D[3] x[5]) (D[3] x[4]) (D[3 : ] x[3 : ]); () (H[5 : ] dt[3 : 6]) (L[5 : ] dt[5 : ]); (c) (PA[2 : ] ddr[23 : 2]) ( ddr[ : ]); Figure 8: Wired logic nd shifts. continue := CONTINUE { portequls } ; ; portequls := ( physport literl ) ; to lst I/O sttement Figure 9: Flow control. Control in Condition logic Figure : Control flow templtes. from RESTART Figure 3: Pipeline stedy-stte join templte. lst dt item hs een completely processed. Two sic pproches present themselves: one method detects whether the pipeline is empty y checking tht no strct flip-flop holds vlid nd sserts the port PipeEmpty in tht cse. Depending on the speed/re requirements nd the cpilities of the trget technology, this cn e relized either in seril or in prllel fshion (Figure 8() nd (c)). If ny slow-downduetocscdedorverywidelogicgtesisuncceptle, the pproch shown in Figure 9 cn e used. While it completely voids long comintionl pths, it requires doule the numer of strct flip-flops. 6. OPTIMIZED MAPPING Even though we hve expressed the precise semntics of the individul UCODE sttements in terms of composed strct hrdwre templtes, this y no mens indictes tht the ctully implemented hrdwre must hve the sme structure. On the contrry, in mny cses it is eneficil to mp only n optimized form of the wrpper to the trget technology. Since our primry trget re FPGAs, specificlly the Xilinx Virtex FPGA rchitectures, we will discuss some procedures pplicle to these devices. While our strct model of one flip-flop per stte (onehot encoded) hs dvntges oth in theory (esy modeling of prllel sttes) nd in prctice (distriuted controller, less routing congestion), in certin cses the flip-flop

7 Andres Koch 7 to START Figure 4: Pipeline stedy-stte fork templte. Mult6 6 D Y S Prod DQ Strt DQ DQ DQ DQ DQ DQ DQ Finish Prologue Figure 7: Wrpper for pipelined multiplier. START RESTART Stedy stte Epilogue Figure 5: Model of pipeline structure. START; (S ) (D[5 : ] [5 : ]); (S ) (D[5 : ] [5 : ]); ; ; RESTART; ; ; (Y[3 : ] prod[3 : ]); Tle : Results of templte-sed synthesis. Synthesis style Virtex-IIslices Mx. clock [MHz] One-Hot Counter SRL To show the use of medium-complexity IP lock, Figure 2 depicts the UCODE for wrpping the Xilinx Logi- Core 6-Point FFT [22]. After progrmming the operting mode, it ccepts 6-smple lock of time-domin dt. After the end of the computtion is indicted, 6 frequencydomin smples cn e unloded from the IP lock. In pipelined fshion, the next set of time-domin cn e provided to the core when it ecomes ville gin. Tle shows the re nd time trdeoffs when mpping the strct hrdwre to the Virtex-II rchitecture directly one-hot encoded nd using rchitecture-specific locks (counters, shift-registers) on speedgrde 4device. Figure 6: UCODE for pipelined multiplier. requirements exceed the cpilities even of flip-flop rich rchitectures. In these cses, trget-specific locks such s dedicted shift registers (SRL6) cn e employed. Also, the presence of the * (repet) opertor indictes tht given dely in itself is not pipelined nd cn e densely mpped to counter. Conventionl logic synthesis nd mpping lgorithms [8, 9] re used in tightly focused fshion to minimize nd mp the vrious logic locks ssocited with some UCODE opertors. This composing of templtes in UCODE order nd the selective ppliction of limited-scope logic synthesis require only short computtion times. They cn thus e performed on-the-fly during the high-level lnguge compile flow, voiding full-scle HDL synthesis step involving complex externl tools. 7. EXPERIMENTAL RESULTS The UCODE lnguge descried here hs lredy een used for interfcing of simple [2] nd lrger IP locks [2]to utomticlly generted dtpths. 8. FUTURE WORK The UCODEs introduced in this work form the core of the specifiction. However, for relily interfcing with lrge IP locks (e.g., medi codecs) in context of [2], we hve defined extensions such s timeouts nd exception hndling in the CONTINUE sttement tht integrte esily nd with only miniml hrdwre overhed into the existing semntics nd templte-synthesis frmework. While our pplictions hve not required it to dte, irregulr schedules could e hndled elegntly y extending the CONTINUE sttement with n implicit conflict controller [23, 24], thus voiding the need for lrge condition logic locks in the wrpper controller. 9. CONCLUSION Our lightweight pproch (compred to full-scle protocol conversion) hs proven suitle for prcticl use. Esily uthored concise UCODE descriptions llow the tight integrtion even of complex IP locks into compiled dtpths with miniml computtionl effort. Insted of full HDL synthesis, simple mpping tools wre of some technology-specific fetures suffice to implement the ctul circuits from the composed templtes. The UCODE lnguge nd underlying

8 8 EURASIP Journl on Emedded Systems Strt LstIn () DQ DQ DQ DQ () PipeEmpty (c) PipeEmpty Figure 8: Stopping nd comintionlly drining the pipeline. LstIn PipeEmpty Strt Figure 9: Sequentilly drining the pipeline. ; initilize () (SCALE MODE ) (FWD INV ) (START ) (START ) ; strtofstedy-stte START ; wit for cceptnce of first FFT lock CONTINUE (MODE ) ; write 6 time domin smples 6 (DI R[5 : ] time r[5 : ]) (DI I[5 : ] time i[5 : ]) ; fork control flow for pipelining RESTART ; wit for trnsformed dt CONTINUE (DONE ) ; red 6 frequency domin smples 6 (XK R[5 : ] freq r[5 : ]) (XK I[5 : ] freq i[5 : ]) Figure 2: UCODE for wrpping 6-point FFT. compute model re lso esily extended to ccommodte future integrtion requirements. By using UCODE descriptions to utomticlly generte efficient interfce wrppers, the comintion of optimized IP locks nd utomticlly creted dtpths cn increse the performnce of flow trgeting n dptive computer in mnner similr to trnsprently clling ssemly lnguge routines from high-level lnguge. The complexity of the clling nd prmeter trnsfer mechnisms re hidden from the user y the strction of the UCODE description. REFERENS [] Y. Li, T. Cllhn, E. Drnell, R. Hrr, U. Kurkure, nd J. Stockwood, Hrdwre-softwre co-design of emedded reconfigurle rchitectures, in Proceedings of 37th Design Automtion Conference (DAC ), pp , Los Angeles, Clif, USA, June 2. [2] N. Ksprzyk nd A. Koch, High-level-lnguge compiltion for reconfigurle computers, in Proceedings of Europen Workshop on Reconfigurle Communiction-Centric SoCs (Re- CoSoc 5), Montpellier, Frnce, June 25. [3] VSI Allince, Virtul Component Interfce Stndrd Version 2, 2, [4] ARM, AMBA Specifiction Rev 2., 2, com/products/solutions/amba Spec.html. [5] IBM, Core Connect Bus Architecture, 999, im.com/chips/techli/techli.nsf/productfmilies/core Connect Bus Architecture. [6] A. Koch, On tool integrtion in high-performnce FPGA design flows, in Proceedings of 9th Interntionl Workshop on Field-Progrmmle Logic nd Applictions (FPL 99), pp , Glsgow, UK, August-Septemer 999.

9 Andres Koch 9 [7] A. Koch, FLAME: flexile API for module sed environments, Tech. Rep. 24-, EIS, Technicl University of Brunschweig, Brunschweig, Germny, 24. [8] R. Psserone, J. A. Rowson, nd A. Sngiovnni-Vincentelli, Automtic synthesis of interfces etween incomptile protocols, in Proceedings of 35th Design Automtion Conference (DAC 98), pp. 8 3, Sn Frncisco, Clif, USA, June 998. [9]J.S.SunndR.W.Brodersen, Designofsysteminterfce modules, in Proceedings of IEEE/ACM Interntionl Conference on Computer-Aided Design (ICCAD 92), pp , Snt Clr, Clif, USA, Novemer 992. [] B. Lin nd S. Vercuteren, Synthesis of concurrent system interfce modules with utomtic protocol conversion genertion, in Proceedings of IEEE/ACM Interntionl Conference on Computer-Aided Design (ICCAD 94), pp. 8, Sn Jose, Clif, USA, Novemer 994. [] P. Chou, R. B. Orteg, nd G. Borriello, Interfce cosynthesis techniques for emedded systems, in Proceedings of IEEE/ACM Interntionl Conference on Computer-Aided Design (ICCAD 95), pp , Sn Jose, Clif, USA, Novemer 995. [2] V. D silv, A. Sowmy, S. Prmeswrn, nd S. Rmesh, A forml pproch to interfce synthesis for system-on-chip design, Tech. Rep. UNSW-CSE-TR-34, University of New South Wles, Sydney, Austrli, 23. [3] J. Smith nd G. De Micheli, Automted composition of hrdwre components, in Proceedings of 35th Design Automtion Conference (DAC 98), pp. 4 9, Sn Frncisco, Clif, USA, June 998. [4] S. Nryn nd D. D. Gjski, Interfcing incomptile protocols using interfce process genertion, in Proceedings of 32nd Design Automtion Conference (DAC 95), pp , Sn Frncisco, Clif, USA, June 995. [5] H.Jung,K.Lee,ndS.H, Efficient hrdwre controller synthesis for synchronous dtflow grph in system level design, in Proceedings of 3th Interntionl Symposium on System Synthesis (ISSS ), pp , Mdrid, Spin, Septemer 2. [6] J. Teifel nd R. Mnohr, Sttic s: using dtflow to utomte concurrent pipeline synthesis, in Proceedings of th Interntionl Symposium on Advnced Reserch in Asynchronous Circuits nd Systems (ASYNC 4), pp. 7 27, Crete, Greece, April 24. [7] H. Lnge nd A. Koch, Memory ccess schemes for configurle processors, in Proceedings of th Interntionl Workshop on Field-Progrmmle Logic nd Applictions (FPL ), pp , Villch, Austri, August 2. [8] E. M. Sentovich, K. J. Singh, L. Lvgno, et l., SIS: system for sequentil circuit synthesis, Tech. Rep. UCB/ERL M92/4, Electricl Engineering nd Computer Sciences Deprtment, University of Cliforni, Berkeley, Clif, USA, My 992. [9] J. Cong nd Y. Ding, FlowMp: n optiml technology mpping lgorithm for dely optimiztion in lookup-tle sed FPGA designs, IEEE Trnsctions on Computer-Aided Design of Integrted Circuits nd Systems, vol. 3, no., pp. 2, 994. [2] T. Neumnn nd A. Koch, A generic lirry for dptive computing environments, in Proceedings of th Interntionl Conference on Field-Progrmmle Logic nd Applictions (FPL ), pp , Belfst, Northern Irelnd, UK, August 2. [2] H. Lnge nd A. Koch, Hrdwre/softwre-codesign y utomtic emedding of complex IP cores, in Proceedings of 4th Interntionl Conference on Field Progrmmle Logic nd Appliction (FPL 4), pp , Leuven, Belgium, August- Septemer 24. [22] Xilinx, High-Performnce 6-Point Complex FFT/IFFT V., product specifiction, 2. [23] E.S.Dvidson,L.E.Shr,A.T.Thoms,ndJ.H.Ptel, Effective control for pipelined computers, in Proceedings of th IEEE Computer Society Interntionl Conference (COMPCON 75), pp. 8 84, Sn Frncisco, Clif, USA, Ferury 975. [24] P. Schumont, B. Vnthournout, I. Bolsens, nd H. De Mn, Synthesis of pipelined DSP ccelertors with dynmic scheduling, in Proceedings of 8th Interntionl Symposium on System Synthesis (ISSS 95), pp , Cnnes, Frnce, Septemer 995.

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