Control of switch-mode converters

Transcription

1 Mr M. Peretz, Switch-Mde Pwer Supplies [8-] Cntrl switch-mde cnverters Mr M. Peretz, Switch-Mde Pwer Supplies [8-2] Cntrl bjectives Prduce cntrl cmmand t Regulate the utput vltage Obtain zer r small steady-state (DC) errr Quick respnse t reerence changes Fast recvery Immunity t input and lad changes Reasnable versht

2 Mr M. Peretz, Switch-Mde Pwer Supplies [8-3] A Switch-mde cnverters as eedback systems B m e v v e d Pwer stage d v Cmpensatr Ve Mdulatr Pwer stage is a Switching System (nn-linear) Cmpensatr is an analg r digital cntrller inear cntrl thery based design small signal respnse Mr M. Peretz, Switch-Mde Pwer Supplies [8-4] Cntrl PWM cnverters disturbances in vltage mde 2

3 Mr M. Peretz, Switch-Mde Pwer Supplies [8-5] Vltage regulatin Duty cycle V in Pwer stage ( pwer ) C O V O ( pwer ) R O Feedback Driver PWM mdulatr V e errr amp k V O V re Mr M. Peretz, Switch-Mde Pwer Supplies [8-6] V e + - D cmp V p V v V e PWM mdulatr Oscillatr V t Vp Vv t Vv T V V t V V V s p v n t e v Ts t V V D T V V n e v n s p v V v V p V e Practical D n max.8.9 3

4 Mr M. Peretz, Switch-Mde Pwer Supplies [8-7] Sawtth generatr Mr M. Peretz, Switch-Mde Pwer Supplies [8-8] Transer unctins V e t m e D Zm t D d t 4

5 Mr M. Peretz, Switch-Mde Pwer Supplies [8-9] Cntrl PWM cnverters disturbances in vltage mde v A ut d d v in iut v A ut vin vin d iut v Z ut ut iut vin d vut dad vinaviniutzut vut vre Kt G A Z v vin i ut in ut G G G G KtKMBAd Mr M. Peretz, Switch-Mde Pwer Supplies [8-] Sin Dynamics eedback systems Blck diagram divisin + - S S B H P A S ut K G() AB A knwn (pwer stage + divider) B unknwn (have t be designed) 5

6 Mr M. Peretz, Switch-Mde Pwer Supplies [8-] pgain test Nyquist Criterin A C A(s) G(s) The system is unstable i {+G(s)} has rts in the right hal the cmplex plane. Nyquist criterin is a test r lcatin {+G(s)} rts. Nyquist criterin is nrmally translated int the Bde plane (requency dmain) Mr M. Peretz, Switch-Mde Pwer Supplies [8-2] db G pgain test A +8 In negative eedback systems 8 At ( 8 ) 6

7 Mr M. Peretz, Switch-Mde Pwer Supplies [8-3] db Bde plt A A -8 8 already substracted m m A ( 8 ) A 8 Mr M. Peretz, Switch-Mde Pwer Supplies [8-4] A[dB] Graphical representatin BA cnventinal methd A AB[dB] B[dB] [Hz] AB B [Hz] [Hz] Tedius need t re-plt BA Analysis (nt design) riented Requires iteratins 7

8 Mr M. Peretz, Switch-Mde Pwer Supplies [8-5] A[dB] Graphical Representatin BA A 2lgA 2lg B 2lg(BA) 2lgA 2lg B A B G() BA BA AB B BA [Hz] Mr M. Peretz, Switch-Mde Pwer Supplies [8-6] Pssible cmpensatins V d db A /B db - 4 dec /B g() db - 2 dec /B 8

9 Mr M. Peretz, Switch-Mde Pwer Supplies [8-7] Pssible cmpensatins m 9 m 45 m 9 m 45 m 9 m 45 2 db dec B db db dec A db s db dec u s 2 db 2 db dec dec u s 4 db dec 4 db dec 6 db dec s Mr M. Peretz, Switch-Mde Pwer Supplies [8-8] Oversht and Q in Clsed p in Respnse t step in S in Excitatin Oversht t A C Q Q cs sin m m r m 5 Oversht Design target m 45 5 m 9

10 Mr M. Peretz, Switch-Mde Pwer Supplies [8-9] Extracting the pwer stage cntrl-t-utput transer unctin S V Vin D C R E V D in in n G I D b n E V V in V in G b E in I C V R Mr M. Peretz, Switch-Mde Pwer Supplies [8-2] inearizatin ut V(in) I(3) R V ( ut) V ( in) I(3) ( Vut ( )) ( Vut ( )) d( V ( ut)) v( in) i(3) ( Vin ( )) ( I(3)) V ( ut) V ( ut) V ( ut) v( in) i(3) Vin ( ) I(3)

11 Mr M. Peretz, Switch-Mde Pwer Supplies [8-2] SPICE inearizatin (AC Analysis) ut V(in) I(3) R F I(3) F V(in) ut i(3) R V(in) F I(3) Vin ( ) F Vin ( ) I (3) Mr M. Peretz, Switch-Mde Pwer Supplies [8-22] Vin in Gb Buck linearizatin Ein I C ut R E G in b VinD I D in Ein D I ut VAC d V in V(d) i() V(in) v(d) C R R I() v(d) V(d) v(in) V D Gb D G b I Ein V in

12 Mr M. Peretz, Switch-Mde Pwer Supplies [8-23] Pssible phase cmpensatin schemes ag netwrk R A R in p 2C R Mr M. Peretz, Switch-Mde Pwer Supplies [8-24] Design example 2

13 Mr M. Peretz, Switch-Mde Pwer Supplies [8-25] ag netwrk 4 Vac Vdc VV R k V R2 ut C k V n E IN+ OUT+ IN- OUT- EVAUE V(%IN+, %IN-)*E6-4 d -5d db(v(ut)) SE>> -d Hz Hz KHz.MHz p(-v(ut)) Frequency Mr M. Peretz, Switch-Mde Pwer Supplies [8-26] ag ead netwrk A A ( ampl.) O 2 CR R A2 R in A 2 db dec 2 A 2 3

14 Mr M. Peretz, Switch-Mde Pwer Supplies [8-27] ag-ead netwrk R9 V R3 g C2 V ut2 5 Vac Vdc V2V R4 k k n E3 IN+ OUT+ IN- OUT- EVAUE V(%IN+, %IN-)*E6 d -5d db(v(ut2)) SE>> -d Hz Hz KHz.MHz p(-v(ut2)) Frequency Mr M. Peretz, Switch-Mde Pwer Supplies [8-28] Duble zer cmpensatin scheme A O C2 C3 R R2 2 π R 2 C 3 R3 R R3 R2 2π R 3C2 2π R 2C 2π R C 2π R 3C3 β 2 π R 2 C 3 db 2 dec β 4

15 Mr M. Peretz, Switch-Mde Pwer Supplies [8-29] Duble Zer R8 g C4 V p R7 C3 4 2 Vac Vdc V3 V C5 R5 n k R6 k V k n ut3 E2 IN+ OUT+ IN- OUT- EVAUE V(%IN+, %IN-)*E6 d d db(v(ut3)) SE>> -d Hz Hz KHz.MHz p(-v(ut3)) Frequency Mr M. Peretz, Switch-Mde Pwer Supplies [8-3] The relatinship t PID cmpensatrs vc ve K K I p s K s K d d KI s ω s ω z s z2 Vc Ve db B g() Vc Ve db 2 g() 2 /B 5

16 Mr M. Peretz, Switch-Mde Pwer Supplies [8-3] The relatinship t PID cmpensatrs V d db A /B db - 4 dec /B g() db - 2 dec /B Mr M. Peretz, Switch-Mde Pwer Supplies [8-32] 6

17 Mr M. Peretz, Switch-Mde Pwer Supplies [8-33] Mr M. Peretz, Switch-Mde Pwer Supplies [5-34] 7