Modular Multilevel Converter Control Strategy with Fault Tolerance Remus Teodorescu 1, Emanuel-Petre Eni 1, Laszlo Mathe 1 and Pedro Rodriguez 2

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1 Interntionl Conference on Renewble Energies nd Power Qulity (ICREPQ 13) Bilbo (Spin), 0 th to th Mrch, 013 Renewble Energy nd Power Qulity Journl (RE&PQJ) ISSN X, No.11, Mrch 013 Modulr Multilevel Converter Control Strtegy with ult Tolernce Remus Teodorescu 1, Emnuel-Petre Eni 1, szlo Mthe 1 nd Pedro Rodriguez 1 Deprtment of Energy Technology Alborg University Pontoppidnstræde Alborg (Denmrk) Phone: , e-mil: ret@et.u.dk, lm@et.u.dk Abengo C/ Energí Solr nº 1, Plms Alts, Seville (Spin) Phone: , e-mil: pedro.rodriguez@reserch.bengo.com Abstrct. The Modulr Multilevel Converter (MMC) technology hs recently emerged in SC-HDC pplictions where it demonstrted higher efficiency nd fult tolernce compred to the clssicl -level topology. Due to the bility of MMC to connect to H levels, MMC cn be lso used in trnsformerless STATCOM nd lrge wind turbines. In this pper, control nd communiction strtegy hve been developed to ccommodte tolernt module filure nd cpcitor voltge unblnce. A downscled prototype converter hs been built in order to vlidte nd investigte the control strtegy, nd lso test the proposed communiction infrstructure bsed on Industril Ethernet. Keywords MMC, HDC, Converter, Trnsformerless wind turbine, 1. Introduction Wind energy penetrtion is growing nd the size of wind turbines lso, especilly for offshore pplictions where turbines in the rnge of 3-6 MW re now tested [1]. In order to comply with the more demnding grid codes in some countries with high wind power penetrtion (Denmrk, Germny, Spin, UK, etc.) full-scle bck-tobck (BTB) converters re more nd more used in []. The MMC concept ppers to be promising technology recently introduced for high-voltge high power pplictions, due to the incresed efficiency, redundncy provision nd high qulity voltge output with reduced dv/ nd output filter requirements [3-4]. Due to these dvntges, the MMC is being now used by most of the SC-HDC mnufcturers like ABB (HDC-ight), Siemens (HDC-Plus) nd Alstom (HDC-MxSine) nd lso in STATCOM pplictions (Siemens SC-Plus) nd lrge wind turbines directly connected to M levels [5].. Design nd modeling In the following, we consider n MMC converter pplied to 10 MW/0 k trnsformerless wind turbine. The min dt is shown in TABE I. TABE I. INITIA REQUIREMENTS Description Abbrevition lue DC-link voltge Output AC RMS voltge Rted ctive power One redundnt sub-module ws plced in ech rm. This redundnt module prticiptes in the opertion but in cse of filure it cn be bypssed nd the converter opertion cn continue with cceptble qulity output voltge. The remining sub-modules re tolernt to the 8% increse of the voltge. Considering the opertion principle of the MMC, ech cpcitor hs to be rted to the DC-link voltge level which is divided by the number of sub-modules in one rm, tking into ccount sfety nd redundncy mrgins. Another spect tht should be tken into ccount is the storge cpbility of the cpcitor. This mens tht it hs to be ble to provide the rted power during trnsients in the DC link. dc 36 k 0 k P N 10 MW Power fctor cos ±0.9 Number of sub-modules per rm n 13 Sub-module nominl voltge, nom.77 k Number of voltge levels - 14 Power Module # Phse B # Phse A # # # # Phse C TA1 R TA R x(4500 #, 340 A) R R IGBTs # R R Current imiting Rector TA1 TA1TA R TA R UC GRID GRID igure 1: Three Phse MMC for T Wind Turbine f Cf GRID MMC-13 Topology Grid-Side ilter Grid-Side Supply ES ES ES 77 RE&PQJ, ol.1, No.11, Mrch 013

2 Arm inductors hve to be selected bsed on the fult current rise-rte limittion criterion. The inductors re series connected, nd this cn reduce both internl nd externl fult currents therefore preventing the dmge of the equipment under test [6]. dip din dc c P c = N igure : Representtion of circulting currents If the converter rm consists of n sub-modules, the energy chnge in one sub-module is given by [7]: (7) 3. Cpcitor Blncing Method 3 where S is the pprent power of the converter, k is the voltge modultion index, N is the output ngulr frequency, n is the number of sub-modules per rm nd φ is the output ngulr frequency. Assuming tht sub-module cpcitor hs reltive voltge ripple (±ε) round the nominl voltge for which the cpcitor is designed, the energy of the cpcitor cn be expressed s: 1 1 () WC,nom C,nom W 4 rom eqution (), the sub-module cpcitnce (C) t ny desired voltge ripple (0< ε <1) cn be derived s: W (3) C,nom In cse of the designed converter: C =1 m dc = 0.7mH During the opertion, sub-module cpcitors experience n unequl voltge shre due to the opertion principl. This ffects the output voltge wveform by lowering the efficiency nd qulity indictors of the converter. There re severl possibilities to chieve equl voltge over the rm cpcitors without hving externl voltge sources. This is bsed on the sorting of the sub-modules by choosing wherever module hs to be in ON-stte or O-stte for ech operting cycle [9]. The sorting criteri is bsed on: direction of the rm current; cpcitor voltge. The sorting lgorithm will switch on the cpcitors with the lowest voltges when the current flow is positive nd vice vers for negtive current. This method ensures tht n cpcitors in ech phse leg re shring the DC link voltge t ll the time. In consequence smller rm inductnce is required to suppress the circulting currents [10]. This results in blncing currents circulting between the legs s shown in igure. Due to the symmetric structure of the converter, phse A will be used s n exmple. igure shows the positive nd negtive rm currents, ip nd in respectively. The circulting current long the phse A loop ic is used to represent the rm current. The lod current of the phse A is noted with i. k cos S Wsource (k ) 1 (1) 3 k N n (6) Where α is the rise-rte of the fult current in ka/s. urthermore, in eqution (6), the rm inductor depending on the current rise rte cn be expressed s: C, b (5) where is the rm inductnce, IP nd IN re the positive nd negtive rm currents nd dc is the DC-link voltge. or short trnsients, both rm currents re ssumed to be equl, so eqution (5) cn be rewritten s [8]: A. CAPACITOR DIMENSIONING c dip di N dc 0 (4) B. ARM INDUCTOR DIMENSIONING When selecting the rm inductors which limit the fult currents rise-rtes, the most criticl fults hve to be considered; i.e. short circuit between the DC link terminls. In the first instnt of fult, the sum of the voltge over the inserted cpcitors is equl to the DC link voltge. The voltge drop over the rm inductors, ccording to Kirchhoff s voltge lw, is [8]: dip di N dc 0 (8) igure 3 presents the implementtion of the sub-module Converter Mesurements Sub-module Mesurement Q* IP bc evel Control IN I C evel 1 Control,U bc,u * bc,i DC Averging control,u * D - PI Blncing control bc K5 *,i I P inl voltge commnd B IC,U D - I bc D PI D Normlizer,i PWM PWM Genertor * DC,i * AC AC P* P Sub-module Control Clock Q Converter SGN() igure 3: Implementtion of converter control with focus on sub-module control from the upper rm in phse RE&PQJ, ol.1, No.11, Mrch 013

3 blncing control nd its integrtion with the high level control. rom the high level 1 control voltge reference for the entire phse A is given () which will be included in the blncing controller. The blncing controller shown is specific to ny sub-module in the upper rms of phse A. The level 1 controller mesures the positive ( I Pbc ) nd the negtive ( I N bc men of the phse currents ( I ) rms currents, nd then send n C ) to ech sub-module to be used in the verging controller. The sub-module lso U, * receives cpcitor voltge reference ( ) identicl to the entire rm(u=upper rm) in the phse A which needs to be followed nd n verge of the cpcitors voltges ( U, ) in the entire rm of the phse. rom the cpcitor voltge reference, the blncing controller subtrcts its instntneous vlue nd multiplies it with the sign of the current in the rm, in this cse the upper one ( I P ). The signls from the blncing controller re dded up together nd then normlized before being fed into PWM genertor. The PWM genertor receives phse displcement ngle (, i ) specific to its position in the rm (i) in order to generte the PWM for the sub-module. It cn be observed in igure 4 tht the sub-module blncing control forces the sub-module voltges to rech n equl distribution independently on the prticulr phse shift of the tringulr crrier in cse of filure nd bypssing of one with slight increse in the voltge. 4. oss Anlysis The current in the devices is spred uneqully in ; the lower switch nd the upper diode conduct higher mount of current. The verge positive nd negtive rm currents hve to be obtined in order to clculte the switching losses. They cn be derived nlyticlly nd cn be confirmed by the simultions. Simultions scenrios show tht for different switching frequencies nd rm inductors different efficiencies cn be chieved (see Tble II.). or this cse 60 Hz hs been selected leding to high totl efficiency of 98.5% Switching frequency 60 Hz 360 Hz Tble II. Efficiency vs Switching frequency for 10MW/0 k MMC Arm inductor vlue Totl 1 mh mh 3 mh 5 mh eff.% Cond. losses, kw Sw. losses, kw Totl losses, kw Cond. losses, kw Sw. losses, kw 51.3 Totl losses, kw cell off Cell voltge increse igure 4: Cpcitor voltge blncing fter 1 filure 5. Distributed control igure 5 shows the dt exchnge between mster nd slve. The mster send globl brodcst to the entire converter in terms of: modultion frequency, modultion index, PI controller s gins, opertion mode (converter/inverter) nd n enble commnd. This globl brodcst will be resent only when one of the vlues needs to be chnged. A leg brodcst is sent seprtely to ech leg to set the phse number. This vlue (0-3) will be multiplied with the ngle difference between ech phse in order to crete the 3 sinusoidl references for the PWM. This vlue will be updted only when it is needed. The circulting currents will be verged from the mesurements done by the mster nd sent to ech slve from the leg in order to be used by the blncing controller. An rm brodcst is sent with the number of sub-modules from leg, the phse displcement ngle, the reference cpcitor voltge nd the verge from the lst updte cycle. The phse displcement will be used by the slves in order to ensure proper distribution of the tringulr wves. The cpcitors verge vlue will be updted during ech cycle, while the other will only be updte when reconfigurtion is needed. inlly ech sub-module will receive n individul messge contining its position in the rm, in order to ensure proper distribution of the modultion. In turn, ech sub-module will communicte ech cycle its cpcitor voltge, nd its sttus. This will ensure thn the communiction won t be interrupted nd tht no submodule is fulty nd disrupt the proper opertion. 6. Communiction Technology Industril Ethernet hs been developed nd tkes dvntge of well-estblished Ethernet [11] (speed up to Gbs, lrge number of nodes, nd low cost hrdwre). There re different industril Ethernet implementtions vilble for complex drives systems nd other control pplictions which require high bndwih, fst updtes Mster Modultion frequency (byte) Modultion index (byte) Kp1 vlue (byte) Ki1 vlue (byte) Kp vlue (byte) Ki vlue (byte) Opertion mode (bit) Enble opertion (bit) Phse ngle (byte) Phse number (byte) Averge currents (byte) No of rm sub-modules(byte) Phse displcement ngle(byte) Averge cpcitor vlue (byte) Cpcitor reference vlue (byte) Position in rm (byte) Globl brodcst vlues eg brodcst vlues Arm brodcst vlues One time individul write commnd igure 5: rible communiction Slve n Cpcitor voltge (byte) Protection sttus/error (byte) times nd good clock synchroniztion. There re different implementtions lredy on the mrket, most of them proprietry nd hrd to interconnect. Some implementtions hve been relesed s open source: ProfiNet [1], EtherCAT [13], etc. Due to its better performnce [14] for this protocol EtherCAT ws chosen s communiction solution. EtherCAT is n open source protocol currently mnged by the EtherCAT Group (ETG) [13]. It uses stndrd Ethernet frmes s defined by IEEE 803. [11]. In theory Mster nd Slve cn be implemented by using stndrd RE&PQJ, ol.1, No.11, Mrch 013

4 DCi off the shelf interfces (PHY nd MAC), but in order to improve the pckge forwrding delys the slves re implemented on hrdwre like PGAs or ASICs. The Mster on the other hnd cn be implemented on ny off the shelf hrdwre, without ny specil requirements. A typicl EtherCAT network consists of t lest one mster unit nd up to theoreticl slves. The communiction speed is limited to 100Mbps, nd lthough in theory it could go up to gigbit speeds, however, no existing slve hrdwre cn hndle tht high speed. At the moment there is wide vriety of mster code implementtions to suit the needs for the industry. The slve code hs been implemented on lrge number of PGAs nd ASICs, giving the user flexibility in choosing the optimum solution. A typicl EtherCAT telegrm nd its integrtion into n Ethernet frme is presented in igure 6. Ethernet Heder Ethernet Dt CS 6 Byte 6 Byte Byte Byte Byte 4 Byte Destintion 11 Bit 1 Bit 4 Bit ength Res. Type Source EtherType Heder Dtgrms CS EtherType 88A4h 1 st EtherCAT Dtgrm nd n th EtherCAT Dtgrm Byte Mx 1486 Byte Byte Dtg. Heder Dt WKC WKC = Working Counter 8 Bit 8 Bit 3 Bit 11 Bit Bit 1 Bit 1 Bit 1 Bit 16 Bit Cmd Idx Address en Res C Res M IRQ C= Circulting dtgrm? M=More EtherCAT dtgrms? igure 6 - Ethernet frme with EtherCAT dt structure All the EtherCAT telegrms re initited by the mster. As the telegrms pss thorough the slves hrdwre, ech slve reds the dt ddressed to it nd writes the requested dt in its ssigned position inside the telegrm. This normlly trnsltes in propgtion delys under 500ns, depending on the used implementtion [14]. More thn one slve cn be ddressed in telegrm. This mechnism provides better bndwih usge compred to trditionl Ethernet frmes, due to the minimum frme size. The communiction cycles cn be defined in the mster, nd cn be s low s 50 µs. Ech cycle cn send more thn one telegrm, nd in cse the updte time is shorter thn the time needed for the telegrm to trvel bck, the mster progrm will be signled nd the refresh time will be incresed in order to ccommodte the trveling time. To fcilitte the communiction, ech EtherCAT slve controller () hs 3 buffer memory. This ensures tht the ltest informtion will lwys be present between the telegrm nd the micro-controller (µc), in cse the updte times of one of them is fster thn the other. As soon s either the EtherCAT processing unit or the µc strts writing the first bit in one of the 3 buffers, tht buffer gets locked until the lst bit is written. At tht point the buffer is vilble for reding. This is hndled utomticlly by the. EtherCAT offers its own implementtion of IEEE 1588 [15]. The clock synchroniztion is implemented in the DSP EtherCAT controller oltge mesurement CPD PWM igure 7 - Sub-module construction Red: logicl signls; blue: nlog signls; ornge: PWM. hrdwre, llowing for n ccurcy of below 1µs (mostly determined by the clock source used by the hrdwre). The slve closest to the mster normlly is the clock mster or reference clock in n EtherCAT network, nd becuse of the use of distributed ligned clocks, they re tolernt to communiction fults nd delys compred to fully synchronous communiction. Typicl slves hve t lest one communiction port, but it cn be extended up to four, llowing the network to be constructed bsed on ny topology. The telegrm is red/written s it psses from port 0 to port 3 by the EtherCAT processing unit nd then forwrded to next opened port. In cse port 0 is closed, s the telegrm psses it, the circulting counter will be incresed. If the telegrm psses gin through closed port 0, the telegrm will be destroyed. This is sfety feture in order to ensure, tht in cse of communiction filure with the mster telegrm will not keep circulting in the ring nd possible give erroneous commnds to the slves. 7. Reduced Scle Prototype or the communiction testing 9 level (16 sub-modules) 10kA 400c single phse MMC is constructed, supplied from 800-ink. or the control of the converter distributed controller topology will be used, with phse-shifted tringulr crrier pulse wih modultion [16]. The mster will decide on the modultion frequency, index nd phse shift bsed on the number of modules connected, nd the input nd output voltges. In order to limit the circulting currents nd the unblnce between the sub-modules cpcitors, the blncing controller presented in [17] will be used. It is composed of 8 hlf-bridge sub-modules per rm. The picture of one sub-module is shown in igure 8. The used Microcontroller is Texs Instruments TMDX8069USB. The EtherCAT communiction is connected through piggybck crd with n ASIC ET1100 from Beckhoff, which is further connected to the microcontroller vi 10MHz SPI bus. The Hlf-bridge nd cpcitors re glvnic isolted from the control prt of the bord, llowing the high-voltge ground to flot s it desires. The power on the high voltge ground is supplied trough DC/DC converter for the lower Mosfet, while for the higher Mosfet bootstrp configurtion is used. The Driving IC provides insultion of the signls nd ded-time protection of 100us dely. Gte driver Current Mesurement Rely Tric driver DC RE&PQJ, ol.1, No.11, Mrch 013

5 igure 7 shows simplified electricl schemtic of the module. The blue wires present nlog mesurements, the ornge lines represent the PWM, the red ones the digitl signls while the blck ones the power connections. DC nd DC- re the terminls of the sub-modules. The current is mesured on the negtive side of the cpcitor, nd together with the voltge mesurement will is used for the blncing controller nd modultion. Both mesurements will lso provide digitl signl for the CPD when dngerous sitution is present (overvoltge/over-current) in order to trigger the protections. The protection is implemented using tric nd rely cross the connection terminls of the bord. In cse of 1 1-µC - EtherCAT Slve Controller 3 5 reg 4 Insulted DC/DC converter 5 oltge mesurement 6 -CPD terminl igure 8: Reduced Scle prototype fult the sub-module will be bypssed. The tric provides fst rection times until the rely which closes slower, will provide crowbr permnent connection. In order to synchronize the Microcontrollers, the communiction bord provides two synchroniztion signls which cn be configured to trigger on ll the modules t the sme time. These synchroniztion signls cn be used to inform the µc tht the communiction buffer holds new dt. Also it cn inform tht new communiction dt should be written in the buffer in order to be red by the pssing telegrm in the current communiction cycle. 8. ult tolernce As mentioned before, the MMC should continue proper opertion with one or more (bsed on design) fulty submodules. Among the fults which cn be hndled there re: over-current due to cpcitors short circuit, switching devices filure or communiction filure.. Detection nd bypssing of sub-module in cse of short-circuit or over current fult As described in the previous section, the bord hs different hrdwre implemented protections in order to hve fst rection time. Although ded-time is implemented in the modultion, the driving circuit is designed to not llow shoot-troughs. If one of the Mosfets will get blocked in close position, s soon s the other H-bridge with Driver 8 Bypss protection 9 Trigger button 10 Current mesurement 11 H-bridge connection Mosfet is closed, the cpcitors will be short-circuited nd the voltge cross their terminls will drop very fst. When the DC-link is short-circuited high current is generted which might overhet nd dmge the switching devices. The voltge nd current is mesured constntly in order to be used for the control, but t the sme time lso for protection. As soon s the voltge drops under pre-defined (non-operting) voltge, which mens there is short circuit in the H-bridge, or the current increses over the nominl vlue for more thn 100nS, the CPD will disble the modultion. The module is bypssed by enbling the tric through n optotric nd by closing the rely. The Tric is used for its fst rection time, but in order to limit the impct of the bypssed module, rely will be used to permnently bypss the sub-module. When the protection is ctivted, the CPD will lso signl the µc, nd t the next communiction cycle the mster will be informed bout the bypssed module. In cse the over current protection is triggered on too mny modules, the mster, will utomticlly open the circuit breker on the DC-link, signling DC-link short-circuit. All this will normlly hppen in communiction cycles which should tke mximum 100 microseconds. When only one module is bypssed, the mster reconfigures the rest of the sub-modules in order to compenste for the by-pssed module, while the µc from the by-pssed module will try to dignose the fult nd decide if it cn still prticipte in the modultion. b. Detection nd bypssing of sub-module in cse of communiction fult nd online reconfigurtion Unless messge is brodcsted, ech slve would normlly hve dtgrm ddress directly to it. EtherCAT hs different communiction fult detection mechnism built inside. The most esy to use is the working counter. As the telegrm leves the mster it will hve working counter (WKC) equl to n, where n is the number of slves tht telegrm is ddressed to. Bsed on the CMD byte, the slve will hve to red or write or red nd write in tht dtgrm or do nothing. Ech time the slves sees dtgrm ddressed to it, it will tke the WKC nd subtrct 1 for write commnd nd for red commnd, if the commnd issued by the mster ws successful. When the telegrm will return to the mster, it will look t ll the working counters nd compre them to the expected vlues, determining if the communiction ws or wsn t successful with one or more slves. In order to chieve communiction redundncy the simpler solution is to use ring configurtion s shown in igure 9. While the cble is intct, the sme telegrm is sent to both ports A nd B. The telegrm which leves port A (ornge) will pss through the of ech submodule, nd will get forwrded to the next opened port until it reches port B of the mster. The sme instnce of the telegrm will leve port B towrds port A. As it is not entering in ech sub-module on the min port (port zero), it will be directly forwrded to the next opened port until it reches port A of the mster. Normlly, he first slve will be chosen s reference clock RE&PQJ, ol.1, No.11, Mrch 013

6 Mster Port B Upper Arm Port A Mster Port B Upper Arm Port A on rel-time communiction where the crries the cpcitor blncing tsk in n utonomous wy. The s re switched t very low switching frequency (60 Hz) resulting in very high efficiency. In order to ensure high pprent switching frequency, ll re interleved by providing shift dely for the crrier. EtherCAT hs been showed to be good cndidte for complying with the requirements of rel-time control nd especilly for its bility to provide fult tolernt opertion nd on-line reconfigurtion during filure nd bypssing. Also it cn be designed with redundncy in order to ensure communiction optic fiber brek tolernce. A reduced scle prototype hs been built to vlidte the control strtegy, blncing controller nd communiction. In cse of filure (igure 9b), the telegrm which leves port A, will be returned by the of the second submodules s it noticed tht the output port got closed by the broken cble. It will return to the mster through the sme port (port A). The sme telegrm left t the sme time from port B of the mster, it will get to the now closed connection port of the 3 rd sub-module, nd it will be utomticlly forwrded to the first open port (bck). As it return it will pss through ech of the sub-modules. Both instnces of the telegrm should return t the sme time to the mster. The mster will notice tht ech telegrm hs n invlid WKC, but it will try to put the instnces together, observing tht they re forming vlid telegrm. At this point the first sub-module from port B will be designed s mster clock for the newly creted ring. This will permit the configurtion to continue running without ny problems. The sme pproch will be tken in cse of sub-module filure. The only difference will be tht the mster will retry to send the telegrm few times to be sure tht the wsn t busy t the moment when the telegrm pssed. In cse one of the sub-modules will be unble to communicte, the mster will detect the error for dtgrm designed for tht sub-module, will continue norml opertion with the rest of the sub-modules, nd will signl the control which sub-module is disconnected. The µc of the ffected sub-module will enter into sfe stte until communiction is restored nd will bypss the module in order to llow norml opertion of the MMC. 9. Conclusions ull Duplex ine igure 9 - Arm Redundncy rrngement() nd reconfigurtion (b) MMC topology proves its superiority ginst -level topology in efficiency, reduced filtering requirement nd fult tolernt opertion. The distribute nture of this converter clls for distributed control rchitecture bsed References [1]. Deng, S. Member, Z. Chen, nd S. Member, An Offshore Wind rm with DC Grid Connection nd Its Performnce under Power System Trnsients, pp. 1-8, 011. [] J. Svensson, Grid Connected oltge Source Converter Control Principles nd Wind Energy Applictions, no [3]. Srtenejs, Evlution nd Proposl of MMC-HDC Control Strtegies under Trnsient nd Stedy Stte Conditions Avenue des Renrdières Keywords MMC Inner Controller, Topology, 011. [4] J. Rodríguez, J. I. eon, S. Kouro, R. Portillo, nd M. A. M. Prts, The Age of Multilevel Converters Arrives, no. June, pp. 8-39, 008. [5] M. Sztykiel, R. d Silv, R. Teodorescu,. Zeni,. Helle, nd P. Kjer. "Modulr Multilevel Converter Modelling, Control nd Anlysis under Grid requency Devitions.", EPE Joint Wind Energy nd T&D Chpters Seminr. [6] B. Jcobson, P. Krlsson, nd G. Asplund, SC-HDC trnsmission with cscded two-level converters, 010. [7] R. Mrqur nd A. esnicr, Modulres Stromrichterkonzept für Netzkupplungsnwendung bei hohen Spnnungen, ETG- chtgung, Bd Nuheim, Germny, 00. [8]Q. Tu, Z. Xu, nd H. Hung, Prmeter design principle of the rm inductor in modulr multilevel converter bsed HDC, Power System Technology, pp. 0-5, 010. [9]S. Rohner, S. Bernet, M. Hiller, nd R. Sommer, Modultion, osses, nd Semiconductor Requirements of Modulr Multilevel Converters, IEEE Trnsctions on Industril Electronics, vol. 57, no. 8, pp , Aug [10]Z. i, P. Wng, H. Zhu, Z. Chu, nd Y. i, An Improved Pulse Wih Modultion Method for Chopper-Cell-Bsed Modulr Multilevel Converters, IEEE Trnsctions on Power Electronics, vol. 7, no. 8, pp , Aug. 01. [11] "IEEE Stndrd for Informtion technology--telecommunictions nd informtion exchnge between systems--ocl nd metropolitn re networks--specific requirements Prt 3: Crrier Sense Multiple Access with Collision Detection (CA/CD) Access Method nd Physicl yer Specifictions Amendment 8: MAC Control rme for Priority-bsed low Control," IEEE Std 80. 3bd-011 (Amendment to IEEE Std ), 011 [1] J. eld, "PROINET - sclble fctory communiction for ll pplictions," in ctory Communiction Systems, 004. Proceedings. 004 IEEE Interntionl Workshop on, 004. [13] IEC, "IEC Industril Communiction Networks ieldbus Specifictions," 007. [14] G. Prytz, "A performnce nlysis of EtherCAT nd PROINET IRT," in Emerging Technologies nd ctory Automtion, 008. ETA 008. IEEE Interntionl Conference on, 008, pp [15]"IEEE Stndrd for Precision Clock Synchroniztion Protocol for Networked Mesurement nd Control Systems," IEEE Std (Revision of IEEE Std ), pp. c1-69, 008. [16] Konstntinou, G.S. nd Agelidis,.G., "Performnce evlution of hlf-bridge cscded multilevel converters operted with multicrrier sinusoidl PWM techniques," in Industril Electronics nd Applictions, 009. ICIEA th IEEE Conference on, 009, pp [17] M. Hgiwr nd H. Akgi, "Control nd experiment of pulsewih-modulted modulr multilevel converters," Power Electronics, IEEE Trnsctions on, vol. 4, pp , RE&PQJ, ol.1, No.11, Mrch 013