Design and optimization of integrated transmission lines on scaled CMOS technologies

Transcription

1 Design and optimization of integrated transmission lines on scaled CMOS technologies F. Vecchi 1,2, M. Repossi 3, W. Eyssa 1,2, P. Arcioni 1, F. Svelto 1 1 Dipartimento di Elettronica, Università di Pavia, Italy 2 Istituto Universitario di Studi Superiori, Pavia 3 STMicroelectronics & Studio di Microelettronica, Pavia

2 Outline 2

3 Motivations 3

4 Microstrip (MS) 65 nm STMicroelectronics CMOS Technology Line Quality Factor (Q L )*: β / (2α) Pro: shielded from substrate losses (P + Doped Well) Con: only one degree of freedom 60 GHz with Z0 = 50 Ω: Q L 10.5 α = 1.2 db/mm * H. P. Hsu, On the general relation between α and Q (correspondence), IEEE Transaction on Microwave Theory and Techniques, Vol. 11, No. 4, July 1963, p

5 Coplanar Waveguide (CPW) Pro: two degrees of freedom (W and G) Con: sensitive to substrate losses (P + Doped Well) A careful analysis of metal and substrate losses is necessary in order to optimize performance for a given characteristic impedance * * F. Vecchi, M. Repossi, W. Eyssa, P. Arcioni, F. Svelto, Analysis of Loss Mechanisms in Coplanar Waveguides Integrated on Bulk CMOS Substrates, 39th European Microwave Conference, EuMC 2009, pp , September

6 CPW with P + Well (Simulations) Z 0 60 GHz Line Quality 60 GHz Z 0 Z 0 = GHz with Z0 = 50 Ω: Q L 7 α = 1.7 db/mm 6

7 CPW without P + Well (Simulations) Z 0 60 GHz Line Quality 60 GHz Z 0 Z 0 = GHz with Z0 = 50 Ω: Q L 12 α = 1 db/mm 7

8 Experiments (with and w/out P + Well) Very good agreement between simulations and measurements Substrate has to be accurately characterized in order to minimize losses 8

9 Grounded Coplanar Waveguide (G-CPW) Pro: two degrees of freedom (W and G) Pro: shielded from substrate losses (P + Doped Well) Is this the right solution? 9

10 Standard CPW Current Distribution Signal Mutual Coupling Magnetic Wall Metal 7 Ground Half T-Line Cross-Section Standard CPW (W = 9.5, G = 4) Negative Mutual Coupling between Signal and Ground Conductor (currents are equal and opposite) Total per length inductance depends on mutual coupling between signal and ground conductors 10

11 M1 Ground Effect (Current Distribution) Mutual Coupling Metal 1 Metal 7 Standard CPW (W = 9.5, G = 4) with Metal 1 Ground Plane (G-CPW) Negative Mutual Coupling between Signal and Ground Conductor (M1 & M7) Total per length inductance is lower than Standard CPW Increased per length capacitance due to Metal 1 Ground Plane 11

12 M1 Ground Effect (RLGC parameters) Substrate losses (G) are suppressed, metal losses (R) slightly increased Mutual coupling lowers L and increases C Z 0 lowers 12

13 G-CPW Optimization (Z 0 = 50 Ω) 75 % 13 % W = 3 µm G = 3 µm 12 % Loss Distribution 67 % 1 % W = 5 µm G = 10 µm 32 % Loss Distribution 13

14 Physical T-Line Model * To suppress substrate losses without impairing L and C and without increasing total resistance, we have to: Lower R p h Increase Z Shield * B. Kleveland, T. H. Lee, S. S. Wong, "50-GHz interconnect design in standard silicon technology, 1998 IEEE MTT-S International Microwave Symposium Digest, Vol. 3, June 1998, pp

15 Shield with Anisotropic Conductivity HFSS Simulation: CPW with anisotropic shield σ = 0 along Prop. Direction Metal σ along orthogonal direction Can be achieved with a periodic structure Difficult to analyze and optimize 15

16 Examples of periodic integrated TL Microstrip CPW Slow-Wave CPW CMOS substrate CMOS substrate CMOS substrate Dummy Metal Fills Floating Strips Lines not uniform in the propagation direction 2D E.M. analysis on the cross-section doesn t apply Conventional 3D analysis huge amount of CPU and memory resources However, all these structures are (or can be implemented as) periodic 16

17 Periodic Structure Analysis Structures inhomogeneous (but periodic) in the direction of propagation Floquet Analysis For a given frequency, an E.M. Field is calculated such that the following relations are satisfied: The Floquet port in HFSS is used exclusively with planar-periodic structures (not periodic in the direction of propagation) However, it is possible to calculate the eigenmodes of a structure with periodic boundary conditions imposing a phase delay (not attenuation) How to calculate the characteristic of the line? 17

18 Proposed Method* (1) We impose: We need: Transmission Line Q-Factor Generic Resonator Q-Factor * F. Vecchi, M. Repossi, W. Eyssa, P. Arcioni, F. Svelto: Design of Low-loss Transmission Lines in Scaled CMOS by Accurate Electromagnetic Simulations, IEEE Journal of Solid-State Circuits, Vol. 44, No. 9, September 2009, pp

19 Proposed Method (2) Current Integration Line CMOS substrate S Voltage Integration Line Characteristic impedance is calculate by means of the standard definitions Z pv, Z pi, Z vi Power flow is calculated by integrating the Poynting vector over the surface S Voltage and current are calculated by integrating electric and magnetic field over appropriate integrating lines (blue and red line, respectively) 19

20 Design example 1 Slow-Wave CPW (SW-CPW) * Smart use of metal dummy fills to increase the phase constant of the line Shorter lines needed in matching circuits, filters, Reduced area occupation As in G-CPW, substrate is shielded from the electric field almost no substrate losses Large gap and small line widths needed to keep impedance close to 50 Ω Increased conductor losses Design Rules Compliant * F. Vecchi, M. Repossi, W. Eyssa, P. Arcioni, F. Svelto: Design of Low-loss Transmission Lines in Scaled CMOS by Accurate Electromagnetic Simulations, IEEE Journal of Solid-State Circuits, Vol. 44, No. 9, September 2009, pp

21 SW-CPW Design Strips Geometry (M1 to M7) Grey areas denote unfeasible values due to Design Rules Lower W b /d to enhance Q L Lower D to enhance β 21

22 Experimental verifications SW-CPW Simulation time: 5 min. per frequency point 22

23 Design example 2 Shielded CPW (S-CPW) * Thin bars transverse to propagation Equivalent to a slotted G-CPW no longitudinal currents in the bottom ground plane As in G-CPW, substrate is shielded from the electric field almost no substrate losses The reduced additional capacitance of the shield allows for wider signal line width Reduced conductor losses Design Rules Compliant * F. Vecchi, M. Repossi, W. Eyssa, P. Arcioni, F. Svelto: Design of Low-loss Transmission Lines in Scaled CMOS by Accurate Electromagnetic Simulations, IEEE Journal of Solid-State Circuits, Vol. 44, No. 9, September 2009, pp

24 S-CPW Design Strips Geometry (M1) Grey areas denote unfeasible values due to Design Rules Lower W b /d to enhance Q L Lower D to enhance Q L and β 24

25 Experimental verifications S-CPW Simulation time: 5 min. per frequency point Best attenuation ever reported for standard scaled CMOS process 25

26 State-of-the-art of attenuation for integrated TL 26

27 State-of-the-art references 27

28 Conclusions 28

29 Publications W. Eyssa, M. Repossi, F. Vecchi, P. Arcioni and F. Svelto, Linee a Basse Perdite per Circuiti Integrati ad Onde Millimetriche in Tecnologia CMOS, XVII Riunione Nazionale di Elettromagnetismo, RiNEm 2008, September F. Vecchi, M. Repossi, W. Eyssa, P. Arcioni, F. Svelto: Design of Low-loss Transmission Lines in Scaled CMOS by Accurate Electromagnetic Simulations, IEEE Journal of Solid-State Circuits, Vol. 44, No. 9, September 2009, pp F. Vecchi, M. Repossi, W. Eyssa, P. Arcioni, F. Svelto: Analysis of Loss Mechanisms in Coplanar Waveguides Integrated on Bulk CMOS Substrates, 39th European Microwave Conference, EuMC 2009, pp , September