MDT10P General Description. 2. Features. 3. Applications

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Cory Stewart
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1 1. General This ROM-Based 8-bit micro-controller uses a fully static CMOS technology process to achieve high speed, small size, the low power and high noise immunity. On chip memory includes 2K words EPROM, and 80 bytes static RAM. 2. Features The followings are some of the features on the hardware and software : Fully CMOS static design 8-bit data bus On chip EPROM size : 2 K words Internal RAM size : 80 bytes (73 general purpose registers, 7 special registers) 36 single word instructions 14-bit instructions 2-level stacks Operating voltage : 2.3 ~ 5.5 Operating frequency : 0 ~ 20 MHz The most fast execution time is 200 ns under 20 MHz in all single cycle instructions except the branch instruction Addressing modes include direct, indirect and relative addressing modes Power-on Reset (POR) 4 types of power edge-detector reset: 1.8v, 2.1v, always enable 1.8v and Disable Sleep Mode for power saving 4 types of oscillator can be selected by programming option: RC-Low cost RC oscillator LFXT-Low frequency crystal oscillator XTAL-Standard crystal oscillator EXT-R-Low cost R oscillator 2 oscillator start-up time can be selected by programming option: EXT-R RC:150 s,20ms XT LF :20ms,80ms 8-bit real time clock/counter(rtcc) with 8-bit programmable prescaler On-chip RC oscillator based Watchdog Timer(WDT) 12 I/O pins with their own independent direction control 12 I/O pins own independent weak pull-high and can be enabled by software. WDT can be enabled by software if WDT Disable is selected in user option. 3. Applications The application areas of this MDT10P258 are from appliance motor control and high speed automotive to low power remote transmitters /receivers, pointing devices, and telecommunications processors. Such as Remote controller, small instruments, chargers, toy, automobile and PC peripheral etc. P /09 er. 1.0

2 4. Pin Assignment MDT10P258P11 MDT10P258S11 PA PA1 PA PA0 RTCC 3 16 OSC1 /MCLR 4 15 OSC2 ss 5 14 dd PB PB7 PB PB6 PB PB5 PB PB4 MDT10P258SS11 PA PA1 PA PA0 RTCC 3 18 OSC1 /MCLR 4 17 OSC2 SS 5 16 DD SS 6 15 DD PB PB7 PB PB6 PB PB5 PB PB4 5. Order Information MARK ROM (Words) RAM (Bytes) I/O Timer (8 bit) Package Mil MDT10P258P11 2K DIP 300 mil MDT10P258S11 2K SOP 300 mil MDT10P258SS11 2K SSOP 209 mil P /09 er. 1.0

3 6. Block Diagram Two Levels Stack 11 bits 11 bits EPROM 2048X14 14 bits RAM 73X8 Port PA0~PA3 4 bits Port A (pull hi) Program Counter Instruction Register Special Register MCLR OSC2 OSC1 D0~D7 Port PB0~PB7 8 bits Port B (pull hi) Oscillator Circuit Instruction Decoder Control Circuit Data 8-bit Power on Reset PED Working Register ALU Status Register 8-bit Timer/Counter Prescaler WDT/OST Timer RTCC P /09 er. 1.0

4 7. Pin Function Pin Name I/O Function PA0~PA3 I/O Port A, TTL input level PB0~PB7 I/O Port B, TTL input level RTCC I Real Time Clock/Counter, Schmitt Trigger input levels /MCLR I Master Clear, Schmitt Trigger input levels OSC1 I Oscillator Input OSC2 O Oscillator Output dd ss Power supply Ground 8. Memory Map (A) Register Map Address 00 Indirect Addressing Register 01 RTCC 02 PC 03 STATUS 04 MSR 05 Port A 06 Port B 07~0F Internal RAM 10~1F Internal RAM, Memory bank 0 30~3F Internal RAM, Memory bank 1 50~5F Internal RAM, Memory bank 2 70~7F Internal RAM, memory bank 3 (1) IAR ( Indirect Address Register) : R0 (2) RTCC (Real Time Counter/Counter Register) : R1 P /09 er. 1.0

5 (3) PC (Program Counter) : R2 Write PC, CALL --- always 0 JUMP, LJUMP, LCALL --- from instruction word RTWI, RET --- from STACK A10 A9 A8 A7~A0 Write PC, JUMP, CALL --- from STATUS b6 b5 RTWI, RET --- from STACK LJUMP, LCALL from instruction word Write PC --- from ALU JUMP, CALL, LJUMP, LCALL --- from instruction word RTWI, RET --- from STACK (4) STATUS (Status register) : R3 Bit Symbol Function C HC Z PF TF PAGE Carry bit Half Carry bit Zero bit Power loss Flag bit WDT Timer overflow Flag bit ROM page select bit : 00 : Page 0, 000H --- 1FFH 01 : Page 1, 200H --- 3FFH 10 : Page 2, 400H --- 5FFH 11 : Page 3, 600H --- 7FFH General purpose bit P /09 er. 1.0

6 (5) MSR (Memory Bank Select Register) : R4 Memory Bank Select Register : 00 : 10~1F 01 : 30~3F 10 : 50~5F 11 : 70~7F b7 b6 b5 b4 b3 b2 b1 b0 Read only, always read as 1 (6) PORT A : R5 PA3~PA0, I/O Register (7) PORT B : R6 PB7~PB0, I/O Register (8) TMR (Time Mode Register) Indirect Addressing Mode Bit Symbol Function Prescaler alue RTCC rate WDT rate 2 0 PS2 0 3 PSC 4 TCE 5 TCS 6 PHEN 7 WDTEN : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : : : 1 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 Prescaler assignment bit : 0 RTCC 1 Watchdog Timer RTCC signal Edge : 0 Increment on low-to-high transition on RTCC pin 1 Increment on high-to-low transition on RTCC pin RTCC signal set : 0 Internal instruction cycle clock 1 Transition on RTCC pin Global Pull High Enable bit : 0 Enable weak internal Pull High 1 Disable weak internal Pull High This bit will be ignored if the I/O pull-hi is disable in user option. Watchdog timer Enable bit : 0 Enable WDT 1 Disable WDT P /09 er. 1.0

7 (9) CPIO A, CPIO B (Control Port I/O Mode Register) The CPIO register is write-only = 0, I/O pin in output mode; = 1, I/O pin in input mode. (10) Set Pull high resistors The Pull high register is write-only = 0, Disable I/O pin Pull high resistor = 1, Enable I/O pin Pull high resistor Do the CPIO instructions twice within three instructions on the same I/O port, then the second CPIO instruction will set the corresponding pull-hi of I/O pins to enable if the PHEN bit is enable (PHEN=0). Correct instruction sequence to enable pull-high Ex1: LDWI 0FFH CPIO 06H First:set PortB to input LDWI 0FFH Second CPIO 06H Third:enable Pull high of PB0~7 Ex2: LDWI 0FFH CPIO 06H CPIO 06H First:set PortB to input Second:enable Pull high of PB0~7 Incorrect instruction sequence to enable pull-high Ex1: (over three instructions) LDWI 0FFH CPIO 06H First:set PortB to input LDWI 0FFH Second NOP Third CPIO 06H Fourth:set PortB to input Ex2: (Different port) LDWI 0FFH CPIO 06H First:set PortB to input CPIO 05H set PortA to input (11) EPROM Option by writer programming : OSC Type Ext-R XT LF RC Low cost external R oscillator Crystal oscillator Low frequency crystal oscillator Low cost RC oscillator OST 150 us\ 20 ms OST= 150 us (for RC) or 20ms (for crystal) 20 ms\80 ms OST= 20 ms (for RC) or 80ms (for crystal) P /09 er. 1.0

8 WDT Disable Enable Watchdog timer disable all the time (can be enabled by software,if software WDT enable) Watchdog timer enable all the time (always enable) PED Disable PED disable Low level 1.8 Mid level 2.1 L(all on) always Enable 1.8 Security Disable Enable Security Disable Security Enable Software WDT Enable Disable Freq x 2 Enable Disable I/O pull-hi Enable Disable CLKOUT Enable Disable Reset on Err Enable Disable WDT can be enabled by software WDT can t be enabled by software System clock is doubled System clock is the oscillation frequency Allow software to enable independent I/O pin pull-high Disable all pull-high resistors Allow OSC2 to output CLKOUT signal OSC2 will be floating The MCU will be reset if two illegal instructions are executed continuously. Disable the illegal instruction reset function (B) Program Memory Address 000-7FF 7FF Program memory The starting address of power on, external reset or WDT time-out reset. P /09 er. 1.0

9 8. Reset Condition for all Registers Register Address Power-On Reset /MCLR or WDT Reset CPIO A CPIO B TMR IAR 00h - - RTCC 01h xxxx xxxx uuuu uuuu PC 02h STATUS 03h xxx 000# #uuu MSR 04h 100x xxxx 100u uuuu PORT A 05h xxxx uuuu PORT B 06h xxxx xxxx uuuu uuuu Note : u=unchanged, x=unknown, - =unimplemented, read as 0 #=value depends on the condition of the following table Condition Status: bit 4 Status: bit 3 /MCLR reset (not during SLEEP) u u /MCLR reset during SLEEP 1 0 WDT reset (not during SLEEP) 0 1 WDT reset during SLEEP Instruction Set : Instruction Code Mnemonic Operands Function Operating Status NOP No operation None CLRWT Clear Watchdog timer 0 WT TF, PF SLEEP Sleep mode 0 WT, stop OSC TF, PF TMODE Load W to TMODE register W TMODE None RET Return Stack PC None rrr CPIO R Control I/O port register W CPIO r None rrrrrrr STWR R Store W to register W R None trrrrrrr LDR R, t Load register R t Z iiiiiiii LDWI I Load immediate to W I W None trrrrrrr SWAPR R, t Swap halves register [R(0~3) None R(4~7)] t trrrrrrr INCR R, t Increment register R + 1 t Z P /09 er. 1.0

10 Instruction Code MDT10P258 Mnemonic Operands Function Operating Status trrrrrrr INCRSZ R, t Increment register, skip if zero R + 1 t None trrrrrrr ADDWR R, t Add W and register W + R t C, HC, Z trrrrrrr SUBWR R, t Subtract W from register R -W t or C, HC, Z (R+/W+1 t) trrrrrrr DECR R, t Decrement register R -1 t Z trrrrrrr DECRSZ R, t Decrement register, skip if zero R - 1 t None trrrrrrr ANDWR R, t AND W and register R W t Z iiiiiiii ANDWI i AND W and immediate i W W Z trrrrrrr IORWR R, t Inclu. OR W and register R W t Z iiiiiiii IORWI i Inclu. OR W and immediate i W W Z trrrrrrr XORWR R, t Exclu. OR W and register R W t Z iiiiiiii XORWI i Exclu. OR W and immediate i W W Z trrrrrrr COMR R, t Complement register /R t Z trrrrrrr RRR R, t Rotate right register R(n) R(n-1), C C R(7), R(0) C trrrrrrr RLR R, t Rotate left register R(n) r(n+1), C C R(0), R(7) C xxxxxxx CLRW Clear working register 0 W Z rrrrrrr CLRR R Clear register 0 R Z 0000bb brrrrrrr BCR R, b Bit clear 0 R(b) None 0010bb brrrrrrr BSR R, b Bit set 1 R(b) None 0001bb brrrrrrr BTSC R, b Bit Test, skip if clear Skip if R(b)=0 None 0011bb brrrrrrr BTSS R, b Bit Test, skip if set Skip if R(b)=1 None 1000nn nnnnnnnn LCALL n Long CALL subroutine n PC, None PC+1 Stack 1010nn nnnnnnnn LJUMP n Long JUMP to address n PC None nnnnnnnn CALL n Call subroutine n PC, None PC+1 Stack iiiiiiii RTWI i Return, place immediate to W Stack PC,i W None 11001n nnnnnnnn JUMP n JUMP to address n PC None Note : W : Working register b : Bit position WT : Watchdog timer t : Target TMODE : TMODE mode register 0 : Working register CPIO : Control I/O port register 1 : General register TF : Timer overflow flag R : General register address PF : Power loss flag C : Carry flag PC : Program Counter HC : Half carry OSC : Oscillator Z : Zero flag Inclu. : Inclusive / : Complement Exclu. : Exclusive x : Don t care AND : Logic AND i : Immediate data ( 8 bits ) n : Immediate address 10. Electrical Characteristics P /09 er. 1.0

11 (Operating temperature at 25 ). Sym Condition Min Typ Max Unit dd Operating voltage IL Input Low oltage PA, PB dd= RTCC, /MCLR dd= IH Input high oltage PA, PB dd=5 2.0 dd RTCC, /MCLR dd=5 3.3 dd I IL Input leakage current dd=5 +/-1 µa OL Output Low oltage PA, PB dd=5, I OL =20mA 0.5 dd=5, I OL =5mA 0.2 OH Output High oltage PA, PB dd=5, I OH = -20mA 3.4 dd=5, I OH = -5mA 4.5 I slp Sleep current (WDT disable) dd =2.3 ~ A I slp Sleep current (WDT enable) dd =2.3 dd =3.0 dd =4.0 dd =5.0 dd = A A A A A pr Power Edge-detector Reset oltage Low level Mid level Twdt The basic WDT time-out cycle time dd = ms dd = ms dd = ms dd = ms dd = ms T FLT /MCLR filter dd = ns Icc Comparator Supply current (one comparator) dd=5.0v 15 A ref Input reference voltage dd=2.5v ~6.0 dd P /09 er. 1.0

12 11. Operating Current Temperature=25, the typical value as followings : 11.1 OSC Type=RC ; dd =5.0 ; PED=Disable Cext. (F) Rext. (Ohm) Frequency (Hz) Current (A) 4.7 K 9.16 M 1.40mA 10.0 K 5.6 M 1.00mA 3P 47.0 K 1.44 M 350 A K K 250 A K K 200 A K K 180 A 4.7 K 4.72 M 820µA 10.0 K 2.73 M 550 A 20P 47.0 K K 250 A K K 200 A K K 170 A K 67.6 K 160 A 4.7 K 1.68 M 400 A 10.0 K 934 K 300 A 100P 47.0 K K 200 A K K 175 A K 34.6 K 160 A K 21.8 K 150 A 4.7 K 716 K 300 A 10.0 K K 220 A 300P 47.0 K 87.6 K 170 A K 42.4 K 160 A K 14.2 K 155 A K 8.8 K 145 A P /09 er. 1.0

13 11.2 OSC Type=LF (OSC1&OSC2 External Cap about 10P); WDT-Disable ; PED=Disable oltage/frequency 32 K (Ext 50P) 455 K 1 M Sleep A 2.5@20.5 A 40.0 A <1.0 A A 46.1 A 70.0 A <1.0 A A 91.3 A A <1.0 A A 150 A A <1.0 A A A A <1.0 A 11.3 OSC Type=XT (OSC1&OSC2 External Cap about 10P); WDT-Enable ;PED=Disable oltage/frequency 1 M 4 M 10 M Sleep A A A <1.0 A A A A 1.2 A A A A 3.0 A A µa 1.1 ma 5.0 A A µa 1.5 ma 10.0 A 11.4 OSC Type=EXTR ; dd =5.0 PED=Enable Rext. (Ohm) Frequency (Hz) Current (A) M 1.7 m M 1.8 m 6.2 K M 2.8 m M 3.8 m M 4.3 m M 750 u M 1.1 m 15.0 K M 1.7 m M 2.4 m M 2.7 m K 220 u K 330 u 75.0 K M 600 u M 880 u M 1.1 m P /09 er. 1.0

14 Rext. (Ohm) Frequency (Hz) Current (A) K 100 u K 185 u K K 380 u K 640 u K 790 u K 45 u K 110 u K K 280 u K 510 u K 640 u K 30 u K 90 u 1.1 M K 250 u K 480 u K 615 u K 20 u 2.4 M K 80 u K 240 u K 470 u K 600 u P /09 er. 1.0

15 11.5 Power Edge-detector Reset oltage (Not in Sleep dd =5.0 (PED:Enable) pr(low level) pr(mid level) 1.6~1.8 pr : dd (Power Supply) 1.9~ Port A and Port B Equivalent Circuit Control Pull-high I/O Control D C K I/O Contr ol Latch Q Q B Pull high Resistor Write D G Data O/P Latch Q B Port I/O Pin Data Bus Rea d Q B G Data I/P Latch D TTL Input Level Input Resistor P /09 er. 1.0

16 13. MCLRB and RTCC Input Equivalent Circuit MCLRB R 1 K Schmitt Trigger RTCC R 1 K Schmitt Trigger P /09 er. 1.0

17 14. External Capacitor Selection For Crystal dd =5.0 Osc. Type Resonator Freq. Capacity Range 10 MHz 10 pf ~ 50 pf XT 4 MHz 10 pf ~ 50 pf 1 MHz 20 pf ~50 pf 1 MHz 20 pf ~ 30 pf LF 455 K 20 pf ~30 pf 32 K 20 pf ~30 pf XT Oscillator Mode LF Oscillator Mode Ext-R Oscillator Mode RC Oscillator Mode OSC1 MDT10P258 OSC2 OSC1 MDT10P258 OSC2 MDT10P258 OSC1 OSC2 Fosc/4 C1 C2 The above values of the external capacitor are for reference only but the higher capacitance also increases the start-up time. P /09 er. 1.0

On-chip RC oscillator based Watchdog Timer(WDT) can be operated freely 12 I/O pins with their own independent direction control 3. Applications The ap

On-chip RC oscillator based Watchdog Timer(WDT) can be operated freely 12 I/O pins with their own independent direction control 3. Applications The ap MDT2010 1. General Description This EPROM-Based 8-bit micro-controller uses a fully static CMOS design technology combines higher speeds and smaller size with the low power and high noise immunity of CMOS.