V DSS. 40V R DS(on) typ. 1.4mΩ max. 1.8mΩ 250Ac. I D (Silicon Limited) I D (Package Limited) 195A. HEXFET Power MOSFET.

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1 R DS (on), Drain-to -Source On Resistance (mω) I D, Drain Current (A) Applications l Brushed Motor drive applications l BLDC Motor drive applications l Battery powered circuits l Half-bridge and full-bridge topologies l Synchronous rectifier applications l Resonant mode power supplies l OR-ing and redundant power switches l DC/DC and AC/DC converters l DC/AC Inverters G D S StrongIRFET IRFS7437PbF IRFSL7437PbF HEXFET Power MOSFET V DSS 4V R DS(on) typ..4mω max..8mω 25Ac I D (Silicon Limited) I D (Package Limited) 95A Benefits l Improved Gate, Avalanche and Dynamic dv/dt Ruggedness l Fully Characterized Capacitance and Avalanche SOA l Enhanced body diode dv/dt and di/dt Capability l Lead-Free l Halogen-Free D G S D 2 Pak IRFS7437PbF D S D G TO-262 IRFSL7437PbF G D S Gate Drain Source Ordering Information Base part number Package Type Standard Pack Complete Part Form Quantity Number IRFSL7437PbF TO-262 Tube 5 IRFSL7437PbF IRFS7437PbF D2Pak Tube 5 IRFS7437PbF IRFS7437PbF D2Pak Tape and Reel Left 8 IRFS7437TRLPbF 6 I D = A 25 LIMITED BY PACKAGE T J = 25 C V GS, Gate-to-Source Voltage (V) T C, Case Temperature ( C) Fig. Typical On-Resistance vs. Gate Voltage Fig 2. Maximum Drain Current vs. Case Temperature

2 Absolute Maximum Ratings Symbol Parameter Max. Units I T C = 25 C Continuous Drain Current, V V (Silicon Limited) 25c I T C = C Continuous Drain Current, V V (Silicon Limited) 8 I T C = 25 C Continuous Drain Current, V V (Wire Bond Limited) 95 A I DM Pulsed Drain Current d P C = 25 C Maximum Power Dissipation 23 W Linear Derating Factor.5 W/ C V GS Gate-to-Source Voltage ± 2 V dv/dt Peak Diode Recovery f 3. V/ns T J Operating Junction and -55 to 75 T STG Storage Temperature Range Soldering Temperature, for seconds (.6mm from case) Mounting torque, 6-32 or M3 screw 3 lbfx in (.Nx m) C Avalanche Characteristics E AS (Thermally limited) Single Pulse Avalanche Energy e 35 mj E AS (tested) Single Pulse Avalanche Energy Tested Value k 5 I AR Avalanche Currentd See Fig. 4, 5, 22a, 22b A E AR Repetitive Avalanche Energy d mj Thermal Resistance Symbol Parameter Typ. Max. Units R θjc Junction-to-Case j.65 R θja Junction-to-Ambient (PCB Mount), D 2 Pak j 4 C/W (unless otherwise specified) Symbol Parameter Min. Typ. Max. Units V (BR)DSS Drain-to-Source Breakdown Voltage 4 V ΔV (BR)DSS /ΔT J Breakdown Voltage Temp. Coefficient.29 V/ C R DS(on) Static Drain-to-Source On-Resistance V GS(th) Gate Threshold Voltage V I DSS Drain-to-Source Leakage Current. μa 5 I GSS Gate-to-Source Forward Leakage na Gate-to-Source Reverse Leakage - R G Internal Gate Resistance 2.2 Ω Conditions V GS = V, I D = 25μA Reference to 25 C, I D = mad V GS = V, I D = A V GS = 6.V, I D = 5A V DS = V GS, I D = 5μA V DS = 4V, V GS = V V DS = 4V, V GS = V, T J = 25 C V GS = 2V V GS = -2V Notes: Calculated continuous current based on maximum allowable junction temperature. Bond wire current limit is 95A. Note that current limitations arising from heating of the device leads may occur with some lead mounting arrangements. (Refer to AN-4) Repetitive rating; pulse width limited by max. junction temperature. ƒ Limited by T Jmax, starting, L =.69mH R G = 25Ω, I AS = A, V GS =V. I SD A, di/dt 66A/μs, V DD V (BR)DSS, T J 75 C. Pulse width 4μs; duty cycle 2%. C oss eff. (TR) is a fixed capacitance that gives the same charging time as C oss while V DS is rising from to 8% V DSS. C oss eff. (ER) is a fixed capacitance that gives the same energy as C oss while V DS is rising from to 8% V DSS. ˆ R θ is measured at T J approximately 9 C. This value determined from sample failure population, starting, L=.95mH, R G = 25Ω, I AS = A, V GS =V 2

3 (unless otherwise specified) Symbol Parameter Min. Typ. Max. Units gfs Forward Transconductance 6 S Q g Total Gate Charge nc Q gs Gate-to-Source Charge 4 Q gd Gate-to-Drain ("Miller") Charge 5 Q sync Total Gate Charge Sync. (Q g - Q gd ) 99 t d(on) Turn-On Delay Time 9 ns t r Rise Time 7 t d(off) Turn-Off Delay Time 78 t f Fall Time 53 C iss Input Capacitance 733 pf C oss Output Capacitance 95 C rss Reverse Transfer Capacitance 745 C oss eff. (ER) Effective Output Capacitance (Energy Related) i 3 C oss eff. (TR) Effective Output Capacitance (Time Related)h 735 Diode Characteristics Symbol Parameter Min. Typ. Max. Units I S Continuous Source Current 25c A Conditions V DS = V, I D = A I D = A V DS =2V V GS = V g I D = A, V DS =2V, V GS = V V DD = 2V I D = 3A R G = 2.7Ω V GS = V g V GS = V V DS = 25V ƒ =. MHz, See Fig. 5 V GS = V, V DS = V to 32V, See Fig. V GS = V, V DS = V to 32V Conditions MOSFET symbol (Body Diode) showing the G I SM Pulsed Source Current A integral reverse (Body Diode)d p-n junction diode. V SD Diode Forward Voltage..3 V, I S = A, V GS = V g t rr Reverse Recovery Time 3 ns V R = 34V, 3 T J = 25 C I F = A Q rr Reverse Recovery Charge 24 nc di/dt = A/μs g 25 T J = 25 C I RRM Reverse Recovery Current.3 A t on Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LSLD) D S 3

4 C, Capacitance (pf) V GS, Gate-to-Source Voltage (V) I D, Drain-to-Source Current (A) R DS(on), Drain-to-Source On Resistance (Normalized) I D, Drain-to-Source Current (A) I D, Drain-to-Source Current (A) IRFS/SL7437PbF VGS TOP 5V V 8.V 7.V 6.V 5.5V 5.V BOTTOM 4.5V VGS TOP 5V V 8.V 7.V 6.V 5.5V 5.V BOTTOM 4.5V 4.5V 4.5V 6μs PULSE WIDTH Tj = 25 C. V DS, Drain-to-Source Voltage (V) Fig 3. Typical Output Characteristics 6μs PULSE WIDTH Tj = 75 C. V DS, Drain-to-Source Voltage (V) Fig 4. Typical Output Characteristics 2..8 I D = A V GS = V T J = 75 C V DS = V 6μs PULSE WIDTH V GS, Gate-to-Source Voltage (V) Fig 5. Typical Transfer Characteristics T J, Junction Temperature ( C) Fig 6. Normalized On-Resistance vs. Temperature V GS = V, f = MHZ C iss = C gs C gd, C ds SHORTED C rss = C gd C oss = C ds C gd C iss I D = A V DS = 32V V DS = 2V C oss 6 C rss 4 2 V DS, Drain-to-Source Voltage (V) Fig 7. Typical Capacitance vs. Drain-to-Source Voltage Q G Total Gate Charge (nc) Fig 8. Typical Gate Charge vs. Gate-to-Source Voltage 4

5 V (BR)DSS, Drain-to-Source Breakdown Voltage (V) I SD, Reverse Drain Current (A) R DS (on), Drain-to-Source On Resistance (mω) Energy (μj) I D, Drain-to-Source Current (A) IRFS/SL7437PbF T J = 75 C μsec msec Limited by Package msec V GS = V V SD, Source-to-Drain Voltage (V) Fig 9. Typical Source-Drain Diode Forward Voltage Id =.ma DC Tc = 25 C Tj = 75 C Single Pulse.. V DS, Drain-toSource Voltage (V) Fig. Maximum Safe Operating Area.2. OPERATION IN THIS AREA LIMITED BY R DS (on) T J, Temperature ( C ) Fig. Drain-to-Source Breakdown Voltage V DS, Drain-to-Source Voltage (V) Fig 2. Typical C OSS Stored Energy V GS = 5.5V V GS = 6.V V GS = 7.V VGS = 8.V VGS = V I D, Drain Current (A) Fig 3. Typical On-Resistance vs. Drain Current 5

6 E AR, Avalanche Energy (mj) Avalanche Current (A) IRFS/SL7437PbF D =.5 Thermal Response ( Z thjc ) SINGLE PULSE ( THERMAL RESPONSE ) Notes:. Duty Factor D = t/t2 2. Peak Tj = P dm x Zthjc Tc. E-6 E t, Rectangular Pulse Duration (sec) Fig 4. Maximum Effective Transient Thermal Impedance, Junction-to-Case Allowed avalanche Current vs avalanche pulsewidth, tav, assuming ΔTj = 5 C and Tstart =25 C (Single Pulse) Allowed avalanche Current vs avalanche pulsewidth, tav, assuming ΔΤ j = 25 C and Tstart = 5 C. (Single Pulse).E-6.E-5.E-4.E-3.E-2.E- tav (sec) Fig 5. Typical Avalanche Current vs.pulsewidth TOP Single Pulse BOTTOM % Duty Cycle I D = A Notes on Repetitive Avalanche Curves, Figures 4, 5: (For further info, see AN-5 at Avalanche failures assumption: Purely a thermal phenomenon and failure occurs at a temperature far in excess of T jmax. This is validated for every part type. 2. Safe operation in Avalanche is allowed as long ast jmax is not exceeded. 3. Equation below based on circuit and waveforms shown in Figures 22a, 22b. 4. P D (ave) = Average power dissipation per single avalanche pulse. 5. BV = Rated breakdown voltage (.3 factor accounts for voltage increase during avalanche). 6. I av = Allowable avalanche current. 7. ΔT = Allowable rise in junction temperature, not to exceed T jmax (assumed as 25 C in Figure 4, 5). t av = Average time in avalanche. D = Duty cycle in avalanche = t av f Z thjc (D, t av ) = Transient thermal resistance, see Figures 3) Starting T J, Junction Temperature ( C) Fig 6. Maximum Avalanche Energy vs. Temperature P D (ave) = /2 (.3 BV I av ) = DT/ Z thjc I av = 2DT/ [.3 BV Z th ] E AS (AR) = P D (ave) t av 6

7 Q RR (A) I RR (A) Q RR (A) V GS(th), Gate threshold Voltage (V) I RR (A) IRFS/SL7437PbF I F = 6A V R = 34V T J = 25 C I D = 5μA I D =.ma I D =.A T J, Temperature ( C ) Fig 7. Threshold Voltage vs. Temperature di F /dt (A/μs) Fig. 8 - Typical Recovery Current vs. di f /dt 8 I F = A V R = 34V T J = 25 C 4 2 I F = 6A V R = 34V T J = 25 C di F /dt (A/μs) Fig. 9 - Typical Recovery Current vs. di f /dt di F /dt (A/μs) Fig. 2 - Typical Stored Charge vs. di f /dt 4 2 I F = A V R = 34V T J = 25 C di F /dt (A/μs) Fig. 2 - Typical Stored Charge vs. di f /dt 7

8 - D.U.T ƒ - Circuit Layout Considerations Low Stray Inductance Ground Plane Low Leakage Inductance Current Transformer - Reverse Recovery Current Driver Gate Drive Period P.W. D.U.T. I SD Waveform Body Diode Forward Current di/dt D.U.T. V DS Waveform Diode Recovery dv/dt D = P.W. Period V GS =V V DD * R G dv/dt controlled by RG Driver same type as D.U.T. I SD controlled by Duty Factor "D" D.U.T. - Device Under Test V DD - Re-Applied Voltage Body Diode Inductor Curent Current Forward Drop Ripple 5% I SD * V GS = 5V for Logic Level Devices Fig 22. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET Power MOSFETs 5V tp V (BR)DSS V DS L DRIVER R G 2V V GS tp D.U.T IAS.Ω - V DD A I AS Fig 23a. Unclamped Inductive Test Circuit Fig 23b. Unclamped Inductive Waveforms V DS R D V DS V GS D.U.T. 9% R G - V DD VV GS Pulse Width µs Duty Factor. % % V GS t d(on) t r t d(off) t f Fig 24a. Switching Time Test Circuit Fig 24b. Switching Time Waveforms Current Regulator Same Type as D.U.T. Vds Id 5KΩ Vgs 2V.2μF.3μF V GS D.U.T. V - DS Vgs(th) 3mA I G I D Current Sampling Resistors Qgs Qgs2 Qgd Qgodr Fig 25a. Gate Charge Test Circuit Fig 25b. Gate Charge Waveform 8

9 D 2 Pak (TO-263AB) Package Outline Dimensions are shown in millimeters (inches) D 2 Pak (TO-263AB) Part Marking Information THIS IS AN IRF53S WIT H LOT CODE 824 ASSEMBLED ON WW 2, 2 IN THE ASSEMBLY LINE "L" INTERNATIONAL RECTIFIER LOGO AS S E MBL Y LOT CODE F53S PART NUMBER DAT E CODE YEAR = 2 WEEK 2 LINE L OR INTERNATIONAL RECTIFIER LOGO AS S EMB L Y LOT CODE F53S PART NUMBER DATE CODE P = DESIGNATES LEAD - FREE PRODUCT (OPTIONAL) YEAR = 2 WEEK 2 A = ASSEMBLY SITE CODE Note: For the most current drawing please refer to IR website at 9

10 TO-262 Package Outline Dimensions are shown in millimeters (inches) TO-262 Part Marking Information EXAMPLE: THIS IS AN IRL33L LOT CODE 789 ASSEMBLED ON WW 9, 997 IN THE ASSEMBLY LINE "C" INTERNATIONAL RECTIFIER LOGO ASSEMBLY LOT CODE PART NUMBER DATE CODE YEAR 7 = 997 WEEK 9 LINE C OR INTERNATIONAL RECTIFIER LOGO ASSEMBLY LOT CODE PART NUMBER DATE CODE P = DESIGNATES LEAD-FREE PRODUCT (OPTIONAL) YEAR 7 = 997 WEEK 9 A = ASSEMBLY SITE CODE Note: For the most current drawing please refer to IR website at

11 Qualification information Qualification level Industrial (per JEDEC JESD47F guidelines) Moisture Sensitivity Level D2Pak MS L (per JE DE C J-S T D-2D ) TO-262 Not applicable RoHS compliant Yes Qualification standards can be found at International Rectifier s web site: Higher qualification ratings may be available should the user have such requirements. Please contact your International Rectifier sales representative for further information: Applicable version of JEDEC standard at the time of product release. Data and specifications subject to change without notice. IR WORLD HEADQUARTERS: N Sepulveda., El Segundo, California 9245, USA Tel: (3) TAC Fax: (3) Visit us at for sales contact information.