Medium-Voltage SiC Power MOSFET Packaging: An International Collaboration
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1 Centre for Power Electronics Annual Conference Loughborough, UK Medium-Voltage SiC Power MOSFET Packaging: An International Collaboration Christina DiMarino, Bassem Mouawad, Mark Johnson, Dushan Boroyevich, Rolando Burgos July 5, 2018
2 Background High-voltage ( 10 kv) silicon carbide (SiC) devices increase the power density and reduce the complexity of high-power systems. Applications: urban distribution, wind turbines, more-electric ships Objective: develop an optimized package for 10 kv SiC MOSFETs 2
3 1 st -Gen. 10 kv, 120 A SiC MOSFET Module Testing I= C(dv/dt) 10 kv, 120 A SiC MOSFET/JBS Module 3
4 Objective: To develop a high-density, high-speed, 10 kv SiC MOSFET power module. Challenges: I. High Density + High Voltage = High Electric Field II. Fast Switching = Voltage Overshoot, Current Imbalance, EMI III. High Density + High Power = High Heat Flux Density 4
5 Substrate Design: Electric Field Reduction Simulated Electric Field 6 kv 0 V Substrate1 Substrate1 Substrate2 Heat Sink 6 kv 0 V Floating Heat Sink 6 kv 0 V Substrate1 Substrate2 Triple point 3 kv Heat Sink (mm) >50 % decrease in peak electric field 5 G1 S1 G2 DBA1 DBA2 D1 S1D2
6 Substrate Attach: Large-area Ag Sintering (250 C, 5 MPa) D1 XCT scan of DBA-DBA attach (50 x 50 mm) G1 S1 G2 S1D2 DBA1 DBA (mm) K/W thermal resistance 6
7 Die Attach: Pressure-less Ag Sintering (230 C for 90 min) D1 X-ray image of die attach layer 10 kv, 350 mω SiC MOSFET G1 S1 G2 S1D2 DBA1 DBA (mm) Low voiding content and 18.4 MPa bonding strength 7
8 Interconnect: Molybdenum Posts Instead of Wire Bonds D1 Material CTE Comparison Metals Semiconductors Ceramics G1 S1 G2 DBA1 DBA2 S1D (mm) Molybdenum increases reliability 8
9 Sintered molybdenum posts to 10 kv MOSFET Post Attach: Ag Sintering G1 S1 G2 D1 S1D2 DBA1 DBA (mm) >20 MPa bonding strength to die, >30 MPa to DBA 9
10 Top DBA Attach: Sn10/Pb88/Ag2 Solder Paste X-ray image of die, posts, and DBA in assembled module G1 S1 G2 D1 S1D2 S1D (mm) Good alignment is achieved during assembly 10
11 Wire-bond-less 10 kv SiC MOSFET Power Module D1 L power = 4 nh* L gate = 4 nh* *for each MOSFET G1 S1 G2 S1D2 18 W/mm 3 power density (mm) Low, symmetrical inductance and 4x higher density 11
12 10 kv, 350 mω SiC MOSFET Module Prototype 30 mm Mo Posts DBA3 DBA4 10 kv SiC MOSFET DBA1 DBA2 Spring Terminals Decoupling Capacitors 4 nh L power & L gate 18 W/mm K/W R th,j-a Integrated Direct-Substrate, Jet-Impingement Cooler 12
13 Thermal Management Spring connectors Decoupling capacitors Upper stacked substrate with vias Sintered interconnect with Mo posts Lower stacked substrate with screen and vias Integrated jet-impingement cooler Jet impingement cells 0.38 K/W junction-to-ambient thermal resistance 13
14 Double-Pulse Test Setup 20 kv Passive Probe (75 MHz) Inductor 30 kv Power Supply 14
15 Double-Pulse Test Setup 20 kv Passive Probe (75 MHz) 300 V Passive Probe (1 GHz) Decoupling Capacitors (1.2 µf, 6.6 kv) Gate Driver Inductor Module 15
16 10 kv Prototype DPT 13 ns 260 V/ns 45 ns 83 V/ns V DS V GS R G,ON = 0.33 Ω, R G,OFF = 0.17 Ω, I D = 20 A 13 ns switching at 5 kv 16
17 Embedded Common-Mode Screen D1 C D1 C D2 1/2V DC C D1 C D2 G 1 S 1 G 2 S 2 Middle Metal Layer S1D2 C P1 C P2 1/2V DC C D2 C D1 D1 C P1 C P2 I= C(dv/dt) 17
18 Common-Mode Screen Analysis C P1 C P2 C D2 I= C(dv/dt) 1/2V DC C D1 D1 1/2V DC C D1 C D2 D1 G 1 S 1 G 2 S 2 Middle Metal Layer S1D2 C P1 C P2 Z screen = ωl screen + ωl screen + Z screen Z gnd 1 + R jωc s Z gnd = ωl g R D jωc g P2 1 jωc D + R s ωl gnd + 1 jωc P2 + R g Low L screen High C D Low C P2 18
19 10 kv, 117 mω SiC MOSFET Module Prototype ωl screen + 1 jωc D + R s ωl gnd + 1 jωc P2 + R g L screen = 2 nh; C D = 680 pf; C P2 = 160 pf 19
20 Common-Mode Screen Waveforms ~2 A ~0.2 A R G = 0 Ω, I D = 20 A 10x lower ground current 20
21 Electric Field Reduction Partial Discharge Inception Voltage (rms) Case Air Silicone Gel Single DBA 1.7 kv 7.4 kv Stacked DBAs (middle floating) 1.7 kv 7.6 kv Stacked DBAs (middle at half the applied voltage) 2.6 kv >10.5 kv >50 % higher partial discharge inception voltage 21
22 Electric Field Reduction at the Module Terminals Cu Trace PCB Air Housing Encapsulation Springs Ellipse Air PCB Air Ceramic Electric field strength of air = 3 MV/m 22
23 Electric Field Reduction at the Module Terminals Cu Trace Field-Grading Plate PCB Housing Air Encapsulation Springs Ellipse Ceramic Air PCB Air Air PCB Air Electric field strength of air = 3 MV/m With Field-Grading Plate 23
24 Summary Summary and Future Work 4 nh power- and gate-loop inductances 18 W/mm 3 power density (4 W/mm 3 with cooler) 0.38 K/W (26 mm 2 K/W ) junction-to-ambient R th 13 ns switching at 5 kv 10x reduction in common-mode current >50 % higher partial discharge inception voltage Future Work Electromagnetic interference evaluation Wire bond module switching tests 24
25 Comparison of Multi-chip 10 kv SiC MOSFET Modules 10 kv, 120 A 10 kv, 240 A 10 kv, 60 A 10 kv, 60 A MOSFETs, 6 JBS MOSFETs 2017/ MOSFETs 2017/ MOSFETs L power 29 nh 15.8 nh 8.6 nh 4.4 nh 4x lower L gate 3.6 nh nh 3.8 nh 2x lower C hs 370 pf pf 45 pf 2x lower Power Density 0.99 W/mm W/mm W/mm W/mm 3 4x higher 25
26 Acknowledgments Amy Romero (VT) Bassem Mouawad (UoN) DOWA Dushan Boroyevich (VT) Engineering and Physical Sciences Research Council (EPSRC) G.Q. Lu (VT) HDI Mini-Consortium Members Jianfeng Li (UoN) Ke Li (UoN) Mark Johnson (UoN) Meiyu Wang (TJU) Office of Naval Research (ONR) Ray Li (HRL) Robert Skuriat (UoN) Rolando Burgos (VT) Rolls-Royce Shan Gao (VT) Wolfspeed Yansong Tan (TJU) Yue Xu (VT) Zhenwen Yang (TJU) 26
The Nottingham eprints service makes this work by researchers of the University of Nottingham available open access under the following conditions.
Di Marino, Christina and Boroyevich, Dushan and Burgos, Rolando and Johnson, Christopher Mark and Lu, G.-Q. (2017) Design and development of a highdensity, high-speed 10 kv SiC MOSFET module. In: 2017
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