DATASHEET EL5120, EL5220, EL5420. Features. Applications. 12MHz Rail-to-Rail Input-Output Op Amps. FN7186 Rev 8.00 Page 1 of 21.

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1 DTSHEET EL, EL, EL4 MHz Rail-to-Rail Input-Output Op mps The EL, EL, and EL4 are low power, high voltage, rail-to-rail input-output amplifiers. The EL contains a single amplifier, the EL contains two amplifiers, and the EL4 contains four amplifiers. Operating on supplies ranging from V to V, while consuming only µ per amplifier, the EL, EL, and EL4 have a bandwidth of MHz (-db). They also provide common mode input ability beyond the supply rails, as well as rail-to-rail output capability. This enables these amplifiers to offer maximum dynamic range at any supply voltage. The EL, EL, and EL4 also feature fast slewing and settling times, as well as a high output drive capability of m (sink and source). These features make these amplifiers ideal for use as voltage reference buffers in Thin Film Transistor Liquid Crystal Displays (TFT-LCD). Other applications include battery power, portable devices, and anywhere low power consumption is important. The EL4 is available in the space-saving 4 Ld TSSOP package, the industry-standard 4 Ld SOIC package, as well as the 6 Ld QFN package. The EL is available in the 8 Ld MSOP package and the 8Ld DFN package. The EL is available in the Ld TSOT package. ll feature a standard operational amplifier pin out. These amplifiers are specified for operation with an ambient and junction temperature range of -4 C to + C. Features MHz -db Bandwidth Supply Voltage = 4.V to 6.V Low Supply Current (per mplifier) = µ High Slew Rate = V/µs Unity-Gain Stable Beyond the Rails Input Capability Rail-to-Rail Output Swing Ultra-Small Package Pb-Free vailable (RoHS Compliant) pplications TFT-LCD Drive Circuits Electronics Notebooks Electronics Games Touch-Screen Displays Personal Communication Devices Personal Digital ssistants (PD) Portable Instrumentation Sampling DC mplifiers Wireless LNs Office utomation ctive Filters DC/DC Buffer FN786 Rev 8. FN786 Rev 8. Page of

2 Ordering Information PRT NUMBER (Note ) ELIWT-T7 (Notes, 4) (No longer available or supported) ELILZ-T (Notes,, 4) (No longer available or supported) PRT MRKING TEMP. RNGE ( C) PCKGE PKG. DWG. # K -4 to + Ld TSOT Tape and Reel MDP49 Z -4 to + 8 Ld DFN Tape and Reel (Pb-Free) L8.x ELCYZ (Note ) BB -4 to + 8 Ld MSOP (Pb-Free) MDP4 ELCYZ-T7 (Notes, ) BB -4 to + 8 Ld MSOP Tape and Reel (Pb-Free) MDP4 ELCYZ-T (Notes, ) BB -4 to + 8 Ld MSOP Tape and Reel (Pb-Free) MDP4 EL4CLZ (Note ) (No longer available or supported) 4CLZ -4 to + 6 Ld QFN (Pb-Free) MDP46 EL4CSZ (Note ) 4CSZ -4 to + 4 Ld SOIC (Pb-Free) MDP7 EL4CSZ-T7 (Notes, ) 4CSZ -4 to + 4 Ld SOIC Tape and Reel (Pb-Free) MDP7 EL4CSZ-T (Notes, ) 4CSZ -4 to + 4 Ld SOIC Tape and Reel (Pb-Free) MDP7 EL4CR (Note 4) (No longer available or supported) 4CR -4 to + 4 Ld TSSOP MDP44 EL4CRZ (Note ) 4CRZ -4 to + 4 Ld TSSOP (Pb-Free) M4.7 EL4CRZ-T7 (Notes, ) 4CRZ -4 to + 4 Ld TSSOP Tape and Reel (Pb-Free) M4.7 EL4CRZ-T (Notes, ) 4CRZ -4 to + 4 Ld TSSOP Tape and Reel (Pb-Free) M4.7. Please refer to TB47 for details on reel specifications.. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and % matte tin plate plus anneal (e termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-.. For Moisture Sensitivity Level (MSL), please see device information page for EL, EL, EL4. For more information on MSL please see tech brief TB6. 4. Not recommended for new designs. Refer to ELxT for possible substitutions. FN786 Rev 8. Page of

3 Pinouts VS+ VOUTB VINB- VINB+ VOUT VIN- VIN+ VS- 4 EL (8 LD MSOP) TOP VIEW VOUT 4 EL (8 LD DFN) TOP VIEW THERML PD THERML PD CONNECTS TO VS- NO LONGER VILBLE OR SUPPORTED VS+ VIN- VIN+ VS- VOUTB VINB- VINB+ VOUT VIN- VS- VIN+ EL ( LD TSOT) TOP VIEW VS+ VS- NO LONGER VILBLE OR SUPPORTED VOUT VINB- VIN- VIN+ VS+ VINB+ VINC- VOUTB EL4 (4 LD TSSOP, SOIC) TOP VIEW VOUTD VIND+ VINC+ 9 8 VIND- VS- VOUTC VIN+ VS+ VINB+ 4 NC 6 EL4 (6 LD QFN) TOP VIEW VOUT 6 VOUTB VOUTD 4 THERML PD 7 VOUTC NC 8 VIND+ VIN- VINB- VINC- VIND- NO LONGER VILBLE OR SUPPORTED 9 VINC+ THERML PD CONNECTS TO VS- FN786 Rev 8. Page of

4 bsolute Maximum Ratings (T = + C) Supply Voltage between V S + and V S V Input Voltage V S - -.V, V S +.V Maximum Continuous Output Current m Thermal Information Thermal Resistance (Typical) J ( C/W) Ld TSOT (Note ) Ld DFN (Note 6) Ld MSOP (Note ) Ld QFN (Note 6) Ld SOIC (Note ) Ld TSSOP (Note ) Storage Temperature C to + C Operating Junction Temperature Range C to + Power Dissipation See Curves Pb-Free Reflow Profile see link below CUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.. J is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB79 for details. 6. J is measured in free air with the component mounted on a high effective thermal conductivity test board with direct attach features. See Tech Brief TB79. IMPORTNT NOTE: ll parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: T J = T C = T Electrical Specifications V S + = +V, V S - = -V, R L = k and C L = pf to V, T = + C, unless otherwise specified. PRMETER DESCRIPTION CONDITIONS MIN TYP MX UNIT INPUT CHRCTERISTICS V OS Input Offset Voltage V CM = V mv TCV OS verage Offset Voltage Drift (Note 7) µv/ C I B Input Bias Current V CM = V n R IN Input Impedance G C IN Input Capacitance. pf CMIR Common-Mode Input Range V CMRR Common-Mode Rejection Ratio for V IN from -.V to +.V 7 db VOL Open Loop Gain -4.V V OUT 4.V 7 9 db OUTPUT CHRCTERISTICS V OL Output Swing Low I L = -m V V OH Output Swing High I L = m V I SC Short Circuit Current ± m I OUT Output Current ± m POWER SUPPLY PERFORMNCE PSRR Power Supply Rejection Ratio V S is moved from ±.V to ±7.7V 6 8 db I S Supply Current (Per mplifier) No load 7 µ DYNMIC PERFORMNCE SR Slew Rate (Note 8) -4.V V OUT 4.V, % to 8% V/µs t S Settling to +.% ( V = +) ( V = +), V O = V step ns BW -db Bandwidth R L = k, C L = pf MHz GBWP Gain-Bandwidth Product R L = k, C L = pf 8 MHz PM Phase Margin R L = k, C L = pf CS Channel Separation f = MHz (EL and EL4 only) 7 db 7. Measured over operating temperature range. 8. Slew rate is measured on rising and falling edges. FN786 Rev 8. Page 4 of

5 Electrical Specifications V S + = +V, V S - = V, R L = k and C L = pf to.v, T = + C, unless otherwise specified. PRMETER DESCRIPTION CONDITIONS MIN TYP MX UNIT INPUT CHRCTERISTICS V OS Input Offset Voltage V CM =.V mv TCV OS verage Offset Voltage Drift (Note 9) µv/ C I B Input Bias Current V CM =.V n R IN Input Impedance G C IN Input Capacitance. pf CMIR Common-Mode Input Range V CMRR Common-Mode Rejection Ratio for V IN from -.V to +.V 4 66 db VOL Open Loop Gain.V V OUT 4.V 7 9 db OUTPUT CHRCTERISTICS V OL Output Swing Low I L = -m 8 mv V OH Output Swing High I L = +m V I SC Short Circuit Current ± m I OUT Output Current ± m POWER SUPPLY PERFORMNCE PSRR Power Supply Rejection Ratio V S is moved from 4.V to.v 6 8 db I S Supply Current (Per mplifier) No load 7 µ DYNMIC PERFORMNCE SR Slew Rate (Note ) V V OUT 4V, % to 8% V/µs t S Settling to +.% ( V = +) ( V = +), V O = V step ns BW -db Bandwidth R L = k, C L = pf MHz GBWP Gain-Bandwidth Product R L = k, C L = pf 8 MHz PM Phase Margin R L = k, C L = pf CS Channel Separation f = MHz (EL and EL4 only) 7 db 9. Measured over operating temperature range.. Slew rate is measured on rising and falling edges. FN786 Rev 8. Page of

6 Electrical Specifications V S + = +V, V S - = V, R L = k and C L = pf to 7.V, T = + C, unless otherwise specified. PRMETER DESCRIPTION CONDITIONS MIN TYP MX UNIT INPUT CHRCTERISTICS V OS Input Offset Voltage V CM = 7.V 4 mv TCV OS verage Offset Voltage Drift (Note ) µv/ C I B Input Bias Current V CM = 7.V n R IN Input Impedance G C IN Input Capacitance. pf CMIR Common-Mode Input Range V CMRR Common-Mode Rejection Ratio for V IN from -.V to +.V 7 db VOL Open Loop Gain.V V OUT 4.V 7 9 db OUTPUT CHRCTERISTICS V OL Output Swing Low I L = -m 8 mv V OH Output Swing High I L = +m V I SC Short Circuit Current ± m I OUT Output Current ± m POWER SUPPLY PERFORMNCE PSRR Power Supply Rejection Ratio V S is moved from 4.V to.v 6 8 db I S Supply Current (Per mplifier) No load 7 µ DYNMIC PERFORMNCE SR Slew Rate (Note ) V V OUT 4V, % to 8% V/µs t S Settling to +.% ( V = +) ( V = +), V O = V step ns BW -db Bandwidth R L = k, C L = pf MHz GBWP Gain-Bandwidth Product R L = k, C L = pf 8 MHz PM Phase Margin R L = k, C L = pf CS Channel Separation f = MHz (EL and EL4 only) 7 db. Measured over operating temperature range. Slew rate is measured on rising and falling edges FN786 Rev 8. Page 6 of

7 Typical Performance Curves QUNTITY (MPLIFIERS) T = + C TYPICL PRODUCTION DISTRIBUTION QUNTITY (MPLIFIERS) TYPICL PRODUCTION DISTRIBUTION INPUT OFFSET VOLTGE (mv) INPUT OFFSET VOLTGE DRIFT, TCV OS (µv/ C) FIGURE. EL4 INPUT OFFSET VOLTGE DISTRIBUTION FIGURE. EL4 INPUT OFFSET VOLTGE DRIFT INPUT OFFSET VOLTGE (mv) - INPUT BIS CURRENT (n) TEMPERTURE ( C) - TEMPERTURE ( C) FIGURE. INPUT OFFSET VOLTGE vs TEMPERTURE FIGURE 4. INPUT BIS CURRENT vs TEMPERTURE OUTPUT HIGH VOLTGE (V) I OUT = m OUTPUT LOW VOLTGE (V) I OUT = -m TEMPERTURE ( C) TEMPERTURE ( C) FIGURE. OUTPUT HIGH VOLTGE vs TEMPERTURE FIGURE 6. OUTPUT LOW VOLTGE vs TEMPERTURE FN786 Rev 8. Page 7 of

8 Typical Performance Curves (Continued) R L = k.4 OPEN LOOP GIN (db) 9 8 SLEW RTE (V/µs)... - TEMPERTURE ( C) - TEMPERTURE ( C) FIGURE 7. OPEN LOOP GIN vs TEMPERTURE FIGURE 8. SLEW RTE vs TEMPERTURE SUPPLY CURRENT (m).. SUPPLY CURRENT (µ) T = + C.4 - TEMPERTURE ( C) SUPPLY VOLTGE (V) FIGURE 9. EL4 SUPPLY CURRENT PER MPLIFIER vs TEMPERTURE FIGURE. EL4 SUPPLY CURRENT PER MPLIFIER vs SUPPLY VOLTGE GIN (db) PHSE , T = + C GIN -8 R L = k to GND C L = pf to GND - - k k k M M M PHSE ( ) MGNITUDE (NORMLIZED) (db) - - C L = pf V = - k M M k k 6 M FREQUENCY (Hz) FREQUENCY (Hz) FIGURE. OPEN LOOP GIN ND PHSE vs FREQUENCY FIGURE. FREQUENCY RESPONSE FOR VRIOUS R L FN786 Rev 8. Page 8 of

9 Typical Performance Curves (Continued) MGNITUDE (NORMLIZED) (db) k R L = k V = pf M M pf pf pf M OUTPUT IMPEDNCE ( ) k V = T = + C k M M FREQUENCY (Hz) FREQUENCY (Hz) FIGURE. FREQUENCY RESPONSE FOR VRIOUS C L FIGURE 4. CLOSED LOOP OUTPUT IMPEDNCE vs FREQUENCY 8 MXIMUM OUTPUT SWING (V P-P ) T = + C V = R L = k C L = pf Distortion <% k k M M CMRR (db) 6 4 T = + C k k k M M FREQUENCY (Hz) FREQUENCY (Hz) FIGURE. MXIMUM OUTPUT SWING vs FREQUENCY FIGURE 6. CMRR vs FREQUENCY 8 PSRR+ 6 PSRR (db) 6 4 PSRR- T = + C k k k M M VOLTGE NOISE (nv/ Hz) k k k M M M FREQUENCY (Hz) FREQUENCY (Hz) FIGURE 7. PSRR vs FREQUENCY FIGURE 8. INPUT VOLTGE NOISE SPECTRL DENSITY vs FREQUENCY FN786 Rev 8. Page 9 of

10 Typical Performance Curves (Continued) THD+ N (%) R L = k. V = V IN = V RMS. k k k FREQUENCY (Hz) FIGURE 9. TOTL HRMONIC DISTORTION + NOISE vs FREQUENCY X-TLK (db) k DUL MESURED CHNNEL TO B QUD MESURED CHNNEL TO D OR B TO C OTHER COMBINTIONS YIELD IMPROVED REJECTION k k FREQUENCY (Hz) R L = k V = V IN = mv RMS FIGURE. CHNNEL SEPRTION vs FREQUENCY RESPONSE M 6M OVERSHOOT (%) 9 7 V = R L = k V IN = ±mv T = + C STEP SIZE (V) V = R L = k C L = pf T = + C.%.% k LOD CPCITNCE (pf) SETTLING TIME (ns) FIGURE. SMLL SIGNL OVERSHOOT vs LOD CPCITNCE FIGURE. SETTLING TIME vs STEP SIZE V µs mv ns T = + C V = R L = k C L = pf T = + C V = R L = k C L = pf FIGURE. LRGE SIGNL TRNSIENT RESPONSE FIGURE 4. SMLL SIGNL TRNSIENT RESPONSE FN786 Rev 8. Page of

11 Pin Descriptions EL EL EL4 LD TSOT 8 LD MSOP, 8 LD DFN 4 LD TSSOP, 4 LD SOIC 6 LD QFN PIN NME PIN FUNCTION EQUIVLENT CIRCUIT, 6 NC No Connect IN+ mplifier Non-Inverting Input (Reference Circuit ) IN- mplifier Inverting Input (Reference Circuit ) OUT mplifier Output (Reference Circuit ) VIN+ mplifier Non-Inverting Input (Reference Circuit ) 4 VIN- mplifier Inverting Input (Reference Circuit ) VOUT mplifier Output (Reference Circuit ) VOUT mplifier Output (Reference Circuit ) VIN- mplifier Inverting Input (Reference Circuit ) VIN+ mplifier Non-Inverting Input (Reference Circuit ) 8 4 VS+ Positive Power Supply 4 VINB+ mplifier B Non-Inverting Input (Reference Circuit ) 6 6 VINB- mplifier B Inverting Input (Reference Circuit ) VOUTB mplifier B Output (Reference Circuit ) 8 7 VOUTC mplifier C Output (Reference Circuit ) 9 8 VINC- mplifier C Inverting Input (Reference Circuit ) 9 VINC+ mplifier C Non-Inverting Input (Reference Circuit ) 4 VS- Negative Power Supply VIND+ mplifier D Non-Inverting Input (Reference Circuit ) VIND- mplifier D Inverting Input (Reference Circuit ) 4 4 VOUTD mplifier D Output (Reference Circuit ) V S+ V S+ V S- GND CIRCUIT CIRCUIT V S- FN786 Rev 8. Page of

12 pplications Information Product Description The EL, EL, and EL4 voltage feedback amplifiers are fabricated using a high voltage CMOS process. They exhibit rail-to-rail input and output capability, they are unity gain stable, and have low power consumption (µ per amplifier). These features make the EL, EL, and EL4 ideal for a wide range of generalpurpose applications. Connected in voltage follower mode and driving a load of k and pf, the EL, EL, and EL4 have a -db bandwidth of MHz while maintaining a V/µs slew rate. The EL is a single amplifier, the EL is a dual amplifier, and the EL4 is a quad amplifier. Operating Voltage, Input, and Output The EL, EL, and EL4 are specified with a single nominal supply voltage from V to V or a split supply with its total range from V to V. Correct operation is guaranteed for a supply range of 4.V to 6.V. Most EL, EL, and EL4 specifications are stable over both the full supply range and operating junction temperature range of -4 C to + C. Parameter variations with operating voltage and/or temperature are shown in the typical performance curves. The input common-mode voltage range of the EL, EL, and EL4 extends mv beyond the supply rails. The output swings of the EL, EL, and EL4 typically extend to within 8mV of positive and negative supply rails with load currents of m. Decreasing load currents will extend the output voltage range even closer to the supply rails. Figure shows the input and output waveforms for the device in the unity-gain configuration. Operation is from ±V supply with a k load connected to GND. The input is a V P-P sinusoid. The output voltage is approximately 9.98V P-P. T = + C V = V IN = V P-P FIGURE. OPERTION WITH RIL-TO-RIL INPUT ND OUTPUT Short Circuit Current Limit The EL, EL, and EL4 will limit the short circuit current to ±m if the output is directly shorted to the positive or the negative supply. If an output is shorted OUTPUT INPUT indefinitely, the power dissipation could easily increase such that the device may be damaged. Maximum reliability is maintained if the output continuous current never exceeds ±m. This limit is set by the design of the internal metal interconnects. Output Phase Reversal The EL, EL, and EL4 are immune to phase reversal as long as the input voltage is limited from (V S -) -.V to (V S +) +.V. Figure 6 shows a photo of the output of the device with the input voltage driven beyond the supply rails. lthough the device's output will not change phase, the input's overvoltage should be avoided. If an input voltage exceeds supply voltage by more than.6v, electrostatic protection diodes placed in the input stage of the device begin to conduct and overvoltage damage could occur. FIGURE 6. OPERTION WITH BEYOND-THE-RILS INPUT Power Dissipation With the high-output drive capability of the EL, EL, and EL4 amplifiers, it is possible to exceed the + C maximum operating junction temperature under certain load current conditions. Therefore, it is important to calculate the maximum junction temperature for the application to determine if load conditions need to be modified for the amplifier to remain in the safe operating area. The maximum power dissipation allowed in a package is determined according to Equation : where: V µs V T JMX T MX P DMX = J T JMX = Maximum junction temperature T MX = Maximum ambient temperature J = Thermal resistance of the package V S = ±.V T = + C V = V IN = 6V P-P P DMX = Maximum power dissipation in the package (EQ. ) The maximum power dissipation actually produced by an IC is the total quiescent supply current times the total power FN786 Rev 8. Page of

13 supply voltage, plus the power in the IC due to the loads as shown in Equation : P DMX = i V S I SMX + V S + V OUT i I LOD i when sourcing, and: when sinking. where: i = to for dual and to 4 for quad V S = Total supply voltage I SMX = Maximum supply current per amplifier V OUT i = Maximum output voltage of the application I LOD i = Load current (EQ. ) P DMX = i V S I SMX + V OUT i V S - I LOD i (EQ. ) If we set the two P DMX equations equal to each other, we can solve for R LOD i to avoid device overheat. Figure 7 provide a convenient way to see if the device will overheat. The maximum safe power dissipation can be found graphically, based on the package type and the ambient temperature. By using the previous equation, it is a simple matter to see if P DMX exceeds the device's power derating curves. To ensure proper operation, it is important to observe the recommended derating curves in Figure 7. JEDEC JESD-7 HIGH EFFECTIVE THERML CONDUCTIVITY TEST BORD POWER DISSIPTION (W) W.8W.W 87mW 467mW QFN6 J = 44 C/W DFN8 J = C/W SOIC4 J = 8 C/W TSSOP4 J = 9 C/W MSOP8 J = C/W TSOT J = 4 C/W 7 k with just.db of peaking, and pf with 6.4dB of peaking. If less peaking is desired in these applications, a small series resistor (usually between and ) can be placed in series with the output. However, this will obviously reduce the gain slightly. nother method of reducing peaking is to add a snubber circuit at the output. snubber is a shunt load consisting of a resistor in series with a capacitor. Values of and nf are typical. The advantage of a snubber is that it does not draw any DC load current or reduce the gain Power Supply Bypassing and Printed Circuit Board Layout The EL, EL, and EL4 can provide gain at high frequency. s with any high-frequency device, good printed circuit board layout is necessary for optimum performance. Ground plane construction is highly recommended, lead lengths should be as short as possible and the power supply pins must be well bypassed to reduce the risk of oscillation. For normal single supply operation, where the VS- pin is connected to ground, a.µf ceramic capacitor should be placed from VS+ to pin to VS- pin. 4.7µF tantalum capacitor should then be connected in parallel, placed in the region of the amplifier. One 4.7µF capacitor may be used for multiple devices. This same capacitor combination should be placed at each supply pin to ground if split supplies are to be used. MBIENT TEMPERTURE ( C) FIGURE 7. PCKGE POWER DISSIPTION vs MBIENT TEMPERTURE Unused mplifiers It is recommended that any unused amplifiers in a dual and a quad package be configured as a unity gain follower. The inverting input should be directly connected to the output and the non-inverting input tied to the ground plane. Driving Capacitive Loads The EL, EL, and EL4 can drive a wide range of capacitive loads. s load capacitance increases, however, the -db bandwidth of the device will decrease and the peaking will increase. The amplifiers drive pf loads in parallel with FN786 Rev 8. Page of

14 Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that you have the latest revision. DTE REVISION CHNGE FN Updated Ordering Information Table on page. - dded Revision History. - dded bout Intersil Verbiage. bout Intersil Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets. For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at You may report errors or suggestions for improving this datasheet by visiting Reliability reports are also available from our website at Copyright Intersil mericas LLC 4-. ll Rights Reserved. ll trademarks and registered trademarks are the property of their respective owners. For additional products, see Intersil products are manufactured, assembled and tested utilizing ISO9 quality systems as noted in the quality certifications found at Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. ccordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see FN786 Rev 8. Page 4 of

15 Package Outline Drawing L8.x 8 LED DUL FLT NO-LED PLSTIC PCKGE Rev, /. B PIN INDEX RE 6 PIN # INDEX RE X. 6X..8 +./-.. (4X). TOP VIEW 8X.4 ± /-. 8X. +.7/-.. M C B 4 BOTTOM VIEW SEE DETIL "X".9 ±. (.6) (.) (8X.6). MX SIDE VIEW. C C BSE PLNE SETING PLNE.8 C (.8)(.8). REF C (6X.) (8X.) TYPICL RECOMMENDED LND PTTERN. MX DETIL "X" Dimensions are in millimeters. Dimensions in ( ) for Reference Only. Dimensioning and tolerancing conform to SME Y4.m-994. Unless otherwise specified, tolerance : Decimal ±. Dimension applies to the metallized terminal and is measured between.mm and.mm from the terminal tip. Tiebar shown (if present) is a non-functional feature. The configuration of the pin # identifier is optional, but must be located within the zone indicated. The pin # identifier may be either a mold or mark feature. Compies to JEDEC MO-9 VCED-. FN786 Rev 8. Page of

16 Small Outline Package Family (SO) D h X 4 N (N/)+ E E PIN # I.D. MRK c SEE DETIL Äö B. M C B (N/) L C e H SETING PLNE GUGE PLNE..4 C. M C B b DETIL X L 4 Ð MDP7 SMLL OUTLINE PCKGE FMILY (SO) INCHES SO6 SO6 (. ) SO SO4 SO8 SYMBOL SO-8 SO-4 (. ) (SOL-6) (SOL-) (SOL-4) (SOL-8) TOLERNCE NOTES MX b c D , E E , e Basic - L L Basic - h Reference - N Reference - Rev. M /7. Plastic or metal protrusions of.6 maximum per side are not included.. Plastic interlead protrusions of. maximum per side are not included.. Dimensions D and E are measured at Datum Plane H. 4. Dimensioning and tolerancing per SME Y4.M-994 FN786 Rev 8. Page 6 of

17 Mini SO Package Family (MSOP). M C B D (N/)+ N MDP4 MINI SO PCKGE FMILY MILLIMETERS SYMBOL MSOP8 MSOP TOLERNCE NOTES.. Max. -.. ±. - E E PIN # I.D ±.9 - b.. +.7/-.8 - c.8.8 ±. - B (N/) D.. ±., E ±. - E.. ±., C e H e.6. Basic - L.. ±. - SETING PLNE. C N LEDS c L b SEE DETIL "X".8 M C B L.9.9 Basic - N 8 Reference - Rev. D /7. Plastic or metal protrusions of.mm maximum per side are not included.. Plastic interlead protrusions of.mm maximum per side are not included.. Dimensions D and E are measured at Datum Plane H. 4. Dimensioning and tolerancing per SME Y4.M-994. GUGE PLNE. L DETIL X Ð FN786 Rev 8. Page 7 of

18 Thin Shrink Small Outline Package Family (TSSOP) C E. M C B E B SETING PLNE. C N LEDS e N D TOP VIEW b SIDE VIEW SEE DETIL Äö (N/)+ (N/) PIN # I.D.. C B X N/ LED TIPS.. M C B H MDP44 THIN SHRINK SMLL OUTLINE PCKGE FMILY MILLIMETERS SYMBOL 4 LD 6 LD LD 4 LD 8 LD TOLERNCE..... Max..... ± ±. b /-.6 c /-.6 D ±. E Basic E ±. e Basic L ±. L..... Reference Rev. F /7. Dimension D does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed.mm per side.. Dimension E does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed.mm per side.. Dimensions D and E are measured at dtum Plane H. 4. Dimensioning and tolerancing per SME Y4.M-994. c END VIEW L DETIL X L GUGE PLNE. Ðê FN786 Rev 8. Page 8 of

19 QFN (Quad Flat No-Lead) Package Family X.7 C (E) C SETING PLNE N LEDS L N (N-) (N-) b (N/) e PIN # I.D. MRK TOP VIEW (N/). M C B (N-) (N-) N BOTTOM VIEW DETIL X. C.8 C SEE DETIL "X" N LEDS & EXPOSED PD SIDE VIEW C (c) D (D) 7 (L) NE N LEDS E B X.7 C PIN # I.D. MDP46 QFN (QUD FLT NO-LED) PCKGE FMILY (COMPLINT TO JEDEC MO-) MILLIMETERS SYMBOL QFN44 QFN QFN TOLERNCE NOTES ± /-. - b.... ±. - c.... Reference - D Basic - D /.48 Reference 8 E Basic - E /.4 Reference 8 e...8. Basic - L..4.. ±. - N 44 8 Reference 4 ND Reference 6 NE 8 9 Reference MILLIMETERS TOLER- SYMBOL QFN8 QFN QFN QFN6 NCE NOTES ± / -. - b..... ±. - c..... Reference - D Basic - D Reference - E Basic - E Reference - e Basic - L ±. - N Reference 4 ND 6 4 Reference 6 NE Reference Rev /7. Dimensioning and tolerancing per SME Y4.M Tiebar view shown is a non-functional feature.. Bottom-side pin # I.D. is a diepad chamfer as shown. 4. N is the total number of terminals on the device.. NE is the number of terminals on the E side of the package (or Y-direction). 6. ND is the number of terminals on the D side of the package (or X-direction). ND = (N/)-NE. 7. Inward end of terminal may be square or circular in shape with radius (b/) as shown. 8. If two values are listed, multiple exposed pad options are available. Refer to device-specific datasheet. FN786 Rev 8. Page 9 of

20 TSOT Package Family. C D X C E SETING PLNE. C NX e N. C -B X (L) 6 e 4 (N/) E D. C X N/ TIPS B ddd M C -B D b NX D H MDP49 TSOT PCKGE FMILY MILLIMETERS SYMBOL TSOT TSOT6 TSOT8 TOLERNCE... Max... ± ±. b ±.7 c /-.7 D Basic E Basic E Basic e Basic e Basic L ±. L Reference ddd... - N 6 8 Reference Rev. B /7. Plastic or metal protrusions of.mm maximum per side are not included.. Plastic interlead protrusions of.mm maximum per side are not included.. This dimension is measured at Datum Plane H. 4. Dimensioning and tolerancing per SME Y4.M Index area - Pin # I.D. will be located within the indicated zone (TSOT6 ND TSOT8 only). 6. TSOT version has no center lead (shown as a dashed line). GUGE PLNE. c L 4 Ð FN786 Rev 8. Page of

21 Package Outline Drawing M4.7 4 LED THIN SHRINK SMLL OUTLINE PCKGE (TSSOP) Rev, /9 4. ±. 8 SEE DETIL "X" ±. PIN # I.D. MRK. C B 7.6 B.9-. TOP VIEW END VIEW. REF H. C SETING PLNE. +./-.6. C. CB. MX.9 +./-.. MIN. MX GUGE PLNE ±. SIDE VIEW DETIL "X" (.4) (.6) (.6 TYP) (. TYP) TYPICL RECOMMENDED LND PTTERN. Dimension does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed. per side.. Dimension does not include interlead flash or protrusion. Interlead flash or protrusion shall not exceed. per side.. Dimensions are measured at datum plane H. 4. Dimensioning and tolerancing per SME Y4.M Dimension does not include dambar protrusion. llowable protrusion shall be.8mm total in excess of dimension at maximum material condition. Minimum space between protrusion and adjacent lead is.7mm. 6. Dimension in ( ) are for reference only. 7. Conforms to JEDEC MO-, variation B-. FN786 Rev 8. Page of