Applying the DDX-8000 in Binary Mode

Transcription

1 Applying the DDX-000 in Binary Mode For Applications Assistance Contact: Apogee Technical Support 9 Morgan Drive, Norwood, MA 0 voice: (7) fax: (7) apogee@apogeeddx.com CONTROLLED DOCUMENT: P_ _Rev05 Applying the DDX-000 in Binary Mode.doc DRN: PRELIMINARY Page of

2 Table of Contents. Introduction Binary compared to Ternary system: Advantages and Disadvantages Binary Advantages Binary Disadvantages Reference Designs (see Section for schematics)...3. Filter Components Design Considerations Clocking:...7. Layout Requirements and Recommendations DDX-000 Programming Guidelines Channel Mapping: Other Initialization: Start-Up:...0. Reference Schematics ch Schematic; //5/7, / (L/R/LS/RS, CTR/SUB as realized in RB-5) ch Schematic; //5, /3/ (L/R/SUB, LS/RS/CTR); ch Schematic; /3/ (L, R, SUB)...5 List of Figures Figure. Binary Output Filter Figure. Binary Output Filter with Crosstalk Improvement Modification 5 Figure 3. Output Power, Low THDN Figure. Output Power, 0% THDN Figure 5. Required MCU steps to eliminate POP caused by clock changes 7 Figure. Component (top) Side Component Placement Figure 7. Component Side Copper Layout Figure. Copper (bottom) Side Copper Layout 9 Figure 9. RB-5 Reference Board channel map 9 Figure 0. 5.ch Block Diagram Figure. 5.ch Processing Figure. 5.ch CTR, SUB outputs Figure 3. 5.ch L, R, LS, RS outputs Figure. 5.ch (Alternate) Block Diagram 3 Figure 5. 5.ch (Alt) Processing 3 Figure. 5.ch (Alt) L, R, SUB Outputs Figure 7. LS, RS, CTR Outputs Figure..ch Block Diagram 5 Figure 9..ch Processing 5 Figure..ch L, R, SUB Outputs List of Tables Table : Binary Filter Component Values... Table : Modified Binary Filter Component Values Morgan Drive, Norwood, MA 0 voice: (7) fax: (7) apogee@apogeeddx.com CONTROLLED DOCUMENT: P_ _Rev05 Applying the DDX-000 in Binary Mode.doc DRN: PRELIMINARY Page of

3 . Introduction With the release of the DDX-000 Digital Audio Processor, it is possible to operate in a single-ended binary mode, or differential DDX ternary mode. Binary Mode enables up to four output channels per power device (DDX-0 and DDX-00), which is double the channels available with DDX ternary operation. System complexity and cost are thus reduced. This Note will clarify several important points to assure a successful Binary mode design using Apogee Technology s DDX devices... Binary compared to Ternary system: Advantages and Disadvantages... Binary Advantages Reduced system cost Simpler, smaller design, lower parts count... Binary Disadvantages Less available power per channel Lower SNR Higher crosstalk Less Pop Immunity.. Reference Designs (see Section for schematics) Two of the most popular amplifier configurations are.ch (Left, Right and Subwoofer channels for stereo programs) and 5.ch (Left, Right, Center, Left Surround, Right Surround and Subwoofer channels for Surround Sound programs). Three designs are considered in Section ; two 5.ch and one.ch. The first design is 5.ch with channel layout L/R/LS/RS from the first power device, Ctr and Sub from the second. This design is realized in reference board RB-5, available from Apogee. The second design is also 5.ch. The channel layout provides operation flexibility in channels used, so that when the amplifier is operated as a.ch, the second power device is disabled by the system MCU with the signal. This assures that only the L, R and Sub channels are active and no hiss or noise can be produced by the unused LS, RS and Ctr channels. The third design is a.ch using a single power device. 9 Morgan Drive, Norwood, MA 0 voice: (7) fax: (7) apogee@apogeeddx.com CONTROLLED DOCUMENT: P_ _Rev05 Applying the DDX-000 in Binary Mode.doc DRN: PRELIMINARY Page 3 of

4 . Filter Components DDX-0/00 Binary Filter Component Values LS Ω Ω Ω L 7µH 33µH µh C 390nF 70nF 0nF R,.kΩ.7kΩ 3.kΩ C 0µF µf 3µF Table : Binary Filter Component Values Notes:. C is determined using the formula C = /(π*f 3dB *Z spkr ) with f 3dB =Hz.. C requires time to be charged to operating voltage before applying the output section to the speaker. If the speaker is connected before C is charged, the difference between the uncharged capacitor voltage and the operating voltage will cause an audible POP at the speakers. For no POP on start-up, the 0 or 00 power device is muted for or more RC Time Constants, where R= R and C= C. This delay is performed by the DDX-000 or system MCU. VB R 3.k L uh C OUTxx From DDX-0/00 Outputs (Half-Bridge). C 0nF R 3.k 3uF LS Ohm PGNDxx Figure. Binary Output Filter 9 Morgan Drive, Norwood, MA 0 voice: (7) fax: (7) apogee@apogeeddx.com CONTROLLED DOCUMENT: P_ _Rev05 Applying the DDX-000 in Binary Mode.doc DRN: PRELIMINARY Page of

5 For improved crosstalk performance, C can be split into two capacitors, one connecting to VB and one to ground as seen in Figure. C and C3 are µf for Ω speakers, 00µF for Ω speakers and 0µF for Ω speakers. LS Ω Ω Ω L 7µH 33µH µh C 390nF 70nF 0nF R,.kΩ.7kΩ 3.kΩ C,3 µf 00µF 0µF Table : Modified Binary Filter Component Values Note:. For no POP on start-up, the 0 or 00 power device is muted for or more RC Time Constants, where R= R and C= C. This delay is performed by the DDX-000 or system MCU. VB LS Ohm L uh R 3.k C 0uF OUTxx From DDX-0/00 Outputs (Half-Bridge). C 0nF R 3.k C3 0uF PGNDxx Figure. Binary Output Filter with Crosstalk Improvement Modification 9 Morgan Drive, Norwood, MA 0 voice: (7) fax: (7) apogee@apogeeddx.com CONTROLLED DOCUMENT: P_ _Rev05 Applying the DDX-000 in Binary Mode.doc DRN: PRELIMINARY Page 5 of

6 3. Design Considerations Output Power vs Supply <% THD Output Power (RMS Watts) 0 Ω Ω Ω 0 0 Power Supply Voltage (VDC) Ohm Load, Iout = 3.5A Ohm Load, Iout = 3.5A Ohm Load, Iout = 3.5A Figure 3. Output Power, Low THDN Output Power (RMS Watts) Output Power vs Supply 0% THD Ω Power Supply Voltage (VDC) Ohm Load, Iout = 3.5A Ohm Load, Iout = 3.5A Ohm Load, Iout = 3.5A Ω Ω Figure. Output Power, 0% THDN 9 Morgan Drive, Norwood, MA 0 voice: (7) fax: (7) apogee@apogeeddx.com CONTROLLED DOCUMENT: P_ _Rev05 Applying the DDX-000 in Binary Mode.doc DRN: PRELIMINARY Page of

7 3.. Clocking: When any of the PWM outputs are used in Binary Mode it is important that the proper steps be taken in order to eliminate or minimize the level at which a pop can be generated from the power stage. In the Binary Mode pops can occur when the Input clocking (, LRCLK, or BCLK) are changed or lost. Clock changes and Clock Losses can occur when there are changes between sources (changes between DVD, CD, Analog or any input source via a MUX interfaced to the DDX-000) or when the device/s interfacing to the DDX-000 can not provide a constant or stable clock source. This can cause the loss of either one or all of the serial clock inputs to the DDX-000 (, LRCLK or BCLK) depending on various MPEG, SPDIF, or Audio Decoder Devices. In a system, in which input clocks become unstable because of source switching, the MCU is always aware of changes between audio sources. When a change occurs the MCU must perform the following steps in-order to ensure that the pops be eliminated or minimized when a change in source occurs. Change in Source Requested Hard Mute and Power Down the Power Stage (Enable ) Change to Desired Source Unmute and Power Up the Power Stage (Disable ) Figure 5. Required MCU steps to eliminate POP caused by clock changes. Layout Requirements and Recommendations The placement of Power supply bypass capacitors for the DDX-0 or DDX-00 is very critical and we recommend following our Reference Board Designs exactly for these capacitors location & tracking. Figure, Figure 7 and Figure are shown here for reference, however it is suggested to take a close look at the PCB Gerber files and actual reference PCB before starting the PCB layout. There are 3 types of capacitors used for Power supply bypassing as follows, a) Bulk Bypass: This is normally an aluminum electrolytic type with the value 000uF/35V(DDX- 0), or 000uF/50V(DDX-00), % tolerance (C7 in the picture below). The placement is less critical but the traces supplying the power to the DDX chip is routed thru this capacitor, thus the traces must be routed directly to the power device. b) HF bypass: This is normally a Multilayer ceramic chip type SMD package with value 00nF,, 0%. (C37 & C in the figures below) The placement of this capacitor is very critical. It is recommended to follow exact placement & tracking as per our Reference PCB Designs. The GND connection trace must be connected directly to DDX-0/00 GND pins on component layer copper from at least one of the HF bypass capacitors. c) HF bypass: This is normally a tantalum capacitor in SMD package with the value of uf, 0% (C33 & C0 in the figures below). This is also very critical in terms of placement & highly recommended to follow the Apogee Ref PCB design. If Tantalum type can t be used then Multilayer Ceramic Chip type with SMD package can be substituted. Aluminum electrolytic will not work at these locations due to high frequency operation. d) Speaker Ground return: For crosstalk reduction, it is imperative to provide short, direct paths from the speaker s ground connection to the Bulk Bypass capacitor and PGND pins of the power device. 9 Morgan Drive, Norwood, MA 0 voice: (7) fax: (7) apogee@apogeeddx.com CONTROLLED DOCUMENT: P_ _Rev05 Applying the DDX-000 in Binary Mode.doc DRN: PRELIMINARY Page 7 of

8 Figure. Component (top) Side Component Placement Figure 7. Component Side Copper Layout 9 Morgan Drive, Norwood, MA 0 voice: (7) fax: (7) apogee@apogeeddx.com CONTROLLED DOCUMENT: P_ _Rev05 Applying the DDX-000 in Binary Mode.doc DRN: PRELIMINARY Page of

9 5. DDX-000 Programming Guidelines Figure. Copper (bottom) Side Copper Layout 5.. Channel Mapping: Several differences exist between software control of the DDX-000 for ternary(ddx) operation and binary operation. First and most importantly is the need to map channels internally for best performance. This is accomplished using the channel mapping feature of the DDX-000. It must be remembered that the channel mapping feature occurs first in the signal processing chain and therefore all other operations will need to account for the mapping of the channels. As an example here is a block diagram of the inputs and outputs for a binary set-up consistent with the RB-5 Reference Board. The actual channels at the input and output can be changed from this example for certain designs. But it is very important for performance that the outputs shown are used and that they are assigned to the DDX-0/00 in the manner described in this AppNote. L/R LS/RS C/LFE SDI SDI SDI3 DDX000 DDXAB DDXAB DDX3AB DDXAB DDX5AB DDXAB DDX7AB DDXAB RS L C R LFE LS Figure 9. RB-5 Reference Board channel map 9 Morgan Drive, Norwood, MA 0 voice: (7) fax: (7) apogee@apogeeddx.com CONTROLLED DOCUMENT: P_ _Rev05 Applying the DDX-000 in Binary Mode.doc DRN: PRELIMINARY Page 9 of

10 To perform this channel mapping via IC; Register Address Register Data Comment h b Map In > Out, Map In > Out h 000xxxxb Map In5 > Out 3h 00000b Map In > Out5, Map In > Out h xxxx000b Map In3 > Out7 5.. Other Initialization: Other initialization and settings can be performed consistently with ternary DDX-000 applications with the exception that channels will be different internally because of the channel mapping performed. Note that IS outputs follow output channel mapping selections. Please refer to AppNote: I²C Procedure For 5. Applications Using the DDX Start-Up: To prevent a pop sound at start in a binary system it is necessary to let the output bias voltage charge. This requires a delay at start-up before the power devices are turned on and the DDX000 is un-muted. Therefore after initialization is performed the following steps should be taken. The wait state can be adjusted depending on the individual system. Register Address Register Data Comment 03h xxxxb Set All Channels to Binary Output Wait Wait Wait State for ~.5s 05h b Configuration Register F, Set 07h xxxxxxxxb Unmute, Set Master Volume 5. Source Switching During source switching it may be necessary to disable the power devices to insure that no pop sounds occur at the speaker output. This is accomplish by first hard muting the device, then powering down the power devices via before the clocks become unstable. Register Address Register Data Comment 07h b Set Master Hard Mute 05h 0xxxxxxxb Source Switching 05h xxxxxxxb un 07h xxxxxxxxb Reset Master Volume Setting 9 Morgan Drive, Norwood, MA 0 voice: (7) fax: (7) apogee@apogeeddx.com CONTROLLED DOCUMENT: P_ _Rev05 Applying the DDX-000 in Binary Mode.doc DRN: PRELIMINARY Page 0 of

11 Reference Schematics Applying the DDX-000/xxx in Binary Mode ch Schematic; //5/7, / (L/R/LS/RS, CTR/SUB as realized in RB-5) SCH_A_INPUT TA0 TA TA TA0 TA TA TA0 TA TA SPEAKER OUTPUT CH CH CH CH CH CH SCH_A_INPUT CH7_A CH7_A CH7_A CH5 CH7 CH5 CH7 CH5 CH7 Sch_CH57_Out CH CH CH CH CH CH Sch_B_Processing Sch_CH_Out Figure 0. 5.ch Block Diagram C C9 C0 C R NS R0 NS C EIA005 R9 0 C3 C C9 C R 0 TA TA TA0 C MVO TEST_MODE VDD3.3_ GND_ VDD.5_ SDI_7 SDI_5 SDI_3 SDI_ I I VDD3.3_ GND_ VDD.5_ RESET PLL_BYPASS PWDN SDO_7 SDO_5 VDD.5_7 GND_7 VDD3.3_7 SDO_3 SDO_ O O VDD.5_ GND_ VDD3.3_ OUT_A OUT_B SA XTI PLL_FILTER VDDA_PLL GNDA_PLL VDD3.3_PLL CKOUT VDD.5_3 GND_3 VDD3.3_3 OUT_B OUT_A OUT7_B OUT7_A U3 OUT_A 7 OUT_B VDD.5_5 5 GND_5 VDD3.3_5 3 OUT3_A OUT3_B OUT_A 0 OUT_B 39 OUT5_A 3 OUT5_B 37 VDD.5_ 3 GND_ 35 VDD3.3_ 3 OUT_A 33 OUT_B DDX-000 C C C7 C5.UF.3VDC EIA3_A C C.UF.3VDC EIA3_A CH7_A Rx 0 (0) Note: Make a provision for an filter as shown. Initially, Rx=0 and C3 is OPEN. Some system configurations may require this filter. Contact Apogee tech support for specific application guidance. C3 OPEN (7pF) R NS R3 NS C5 C C7 VDDA L 00 ohm@00mhz EIA005 R 3.0K C3 00PF C9 C UF.3VDC EIA35_B L 00 ohm@00mhz EIA005 C C3 0PF C33 00PF GNDA Figure. 5.ch Processing 9 Morgan Drive, Norwood, MA 0 voice: (7) fax: (7) apogee@apogeeddx.com CONTROLLED DOCUMENT: P_ _Rev05 Applying the DDX-000 in Binary Mode.doc DRN: PRELIMINARY Page of

12 Applying the DDX-000/xxx in Binary Mode L3 33uH C3 CH C39 R 0K C0 U 9 GNDREF GNDR VREG VREG 3 VL CONFIG 5 PWRDN NC VCCP PGNDP PGNDN VCCN V C37 000UF C UF C C35 R7 C3 R5 R V UF C3 7 TRI-STATE FAULT 0 C3 R 0K C9 C5 TWARN 9 INLA INLB 3 INRA 3 INRB 33 VREG 3 VREG 35 3 DDX0 H 35WX-HS VCCP PGNDP PGNDN VCCN GNDS V C UF C7 L 5uH R C5 L5 5uH C5 R.7 R.7 C5 C C53 C50 C C55 C5 CH Figure. 5.ch CTR, SUB outputs L 33uH C57 CH7 C R9 0K C3 U5 9 GNDREF GNDR VREG VREG 3 VL CONFIG 5 PWRDN TRI-STATE 7 FAULT NC VCCP PGNDP PGNDN VCCN V C0 000UF C UF C C5 C59 UF R3 R R5 C V R C5 C7 C R7 R C9 UF L7 33uH CH5 C70 R33 0K CH7_A C TWARN INLA INLB INRA INRB VREG VREG VCCP PGNDP PGNDN VCCN V C7 UF C7 L 33uH C73 R3 C7 R R3 V C7 UF C75 CH C7 3 DDX0 H 35WX-HS GNDS R3 C0 L9 33uH C R35 R3 C C79 CH UF Figure 3. 5.ch L, R, LS, RS outputs 9 Morgan Drive, Norwood, MA 0 voice: (7) fax: (7) apogee@apogeeddx.com CONTROLLED DOCUMENT: P_ _Rev05 Applying the DDX-000 in Binary Mode.doc DRN: PRELIMINARY Page of

13 ch Schematic; //5, /3/ (L/R/SUB, LS/RS/CTR); This channel mapping locates the L,R and SUB on one power device, LS, RS and CTR on the other. This allows 5. or. channel operation. In.ch operation, the second power device is turned off. SCH_A_INPUT TA0 TA TA TA0 TA TA TA0 TA TA SPEAKER OUTPUT CH CH CH SCH_A_INPUT CH CH5 CH CH5 CH CH5 Sch_CH5_Out CH CH3 CH CH3 CH CH3 CH CH CH Sch_B_Processing Sch_CH3_Out Figure. 5.ch (Alternate) Block Diagram C C9 C0 C R0 NS C EIA005 C3 C C9 C TA TA TA0 R 0 C C3 7PF MVO TEST_MODE VDD3.3_ GND_ VDD.5_ SDI_7 SDI_5 SDI_3 SDI_ I I VDD3.3_ GND_ VDD.5_ RESET PLL_BYPASS PWDN SDO_7 SDO_5 VDD.5_7 GND_7 VDD3.3_7 SDO_3 SDO_ O O VDD.5_ GND_ VDD3.3_ OUT_A OUT_B SA XTI PLL_FILTER VDDA_PLL GNDA_PLL VDD3.3_PLL CKOUT VDD.5_3 GND_3 VDD3.3_3 OUT_B OUT_A OUT7_B OUT7_A U3 OUT_A 7 OUT_B VDD.5_5 5 GND_5 VDD3.3_5 3 OUT3_A OUT3_B OUT_A 0 OUT_B 39 OUT5_A 3 OUT5_B 37 VDD.5_ 3 GND_ 35 VDD3.3_ 3 OUT_A 33 OUT_B DDX-000 C C C7 C5.UF.3VDC EIA3_A C C.UF.3VDC EIA3_A R NS R3 C5 C C7 NS VDDA L 00 ohm@00mhz EIA005 R 3.0K C3 00PF C9 C UF.3VDC EIA35_B L 00 ohm@00mhz EIA005 C C3 0PF C33 00PF GNDA Figure 5. 5.ch (Alt) Processing 9 Morgan Drive, Norwood, MA 0 voice: (7) fax: (7) apogee@apogeeddx.com CONTROLLED DOCUMENT: P_ _Rev05 Applying the DDX-000 in Binary Mode.doc DRN: PRELIMINARY Page 3 of

14 Applying the DDX-000/xxx in Binary Mode L 33uH C57 CH C3 C39 C0 R 0K U 9 GNDREF GNDR VREG VREG 3 VL CONFIG 5 PWRDN TRI-STATE 7 FAULT NC VCCP PGNDP PGNDN VCCN V C37 000UF C C5 R5 C59 R3 R R UF C5 C C7 C R7 R C9 UF L7 33uH CH3 V UF C R 0K C9 C5 TWARN 9 INLA INLB 3 INRA 3 INRB 33 VREG 3 VREG 35 3 DDX0 H 35WX-HS VCCP PGNDP PGNDN VCCN GNDS V C UF C7 L 5uH R C5 L5 5uH C5 R.7 R.7 C5 C C53 C50 C C55 C5 CH Figure. 5.ch (Alt) L, R, SUB Outputs L 33uH CH C C3 C70 R9 0K R33 0K C77 C7 U5 9 GNDREF GNDR VREG VREG 3 VL CONFIG 5 PWRDN TRI-STATE 7 FAULT TWARN 9 INLA INLB 3 INRA 3 INRB 33 VREG 3 VREG 35 3 DDX0 H 35WX-HS NC VCCP PGNDP PGNDN VCCN VCCP PGNDP PGNDN VCCN GNDS V V C0 000UF C UF C C7 UF C7 C73 R3 R3 C0 L9 33uH L3 33uH C35 R7 C7 C C3 R R35 R5 R3 V R3 R V C7 UF C UF C3 UF C75 C79 C3 CH CH5 Figure 7. LS, RS, CTR Outputs 9 Morgan Drive, Norwood, MA 0 voice: (7) fax: (7) apogee@apogeeddx.com CONTROLLED DOCUMENT: P_ _Rev05 Applying the DDX-000 in Binary Mode.doc DRN: PRELIMINARY Page of

15 5...ch Schematic; /3/ (L, R, SUB) SCH_A_INPUT TA0 TA0 TA0 SCH_A_INPUT SPEAKER OUTPUT CH CH CH CH3 CH3 CH3 CH CH CH Sch_B_Processing Sch_CH3_Out Figure..ch Block Diagram C C9 C0 C R NS R0 NS C EIA005 R9 0 C3 C C9 C TA TA TA0 R 0 C C3 7PF MVO TEST_MODE VDD3.3_ GND_ VDD.5_ SDI_7 SDI_5 SDI_3 SDI_ I I VDD3.3_ GND_ VDD.5_ RESET PLL_BYPASS PWDN SDO_7 SDO_5 VDD.5_7 GND_7 VDD3.3_7 SDO_3 SDO_ O O VDD.5_ GND_ VDD3.3_ OUT_A OUT_B SA XTI PLL_FILTER VDDA_PLL GNDA_PLL VDD3.3_PLL CKOUT VDD.5_3 GND_3 VDD3.3_3 OUT_B OUT_A OUT7_B OUT7_A U3 OUT_A 7 OUT_B VDD.5_5 5 GND_5 VDD3.3_5 3 OUT3_A OUT3_B OUT_A 0 OUT_B 39 OUT5_A 3 OUT5_B 37 VDD.5_ 3 GND_ 35 VDD3.3_ 3 OUT_A 33 OUT_B DDX-000 C C C7 C5.UF.3VDC EIA3_A C C.UF.3VDC EIA3_A R NS R3 C5 C C7 NS VDDA L 00 ohm@00mhz EIA005 R 3.0K C3 00PF C9 C UF.3VDC EIA35_B L 00 ohm@00mhz EIA005 C C3 0PF C33 00PF GNDA Figure 9..ch Processing 9 Morgan Drive, Norwood, MA 0 voice: (7) fax: (7) apogee@apogeeddx.com CONTROLLED DOCUMENT: P_ _Rev05 Applying the DDX-000 in Binary Mode.doc DRN: PRELIMINARY Page 5 of

16 Applying the DDX-000/xxx in Binary Mode L 33uH C57 CH C3 C39 R 0K C0 U 9 GNDREF GNDR VREG VREG 3 VL CONFIG 5 PWRDN TRI-STATE 7 FAULT NC VCCP PGNDP PGNDN VCCN V C37 000UF C UF C C5 R5 R C7 L7 33uH C59 C R3 R7 R V R UF C9 UF C C5 CH3 R 0K C9 C5 TWARN 9 INLA INLB 3 INRA 3 INRB 33 VREG 3 VREG 35 3 DDX0 H 35WX-HS VCCP PGNDP PGNDN VCCN GNDS V C UF C7 L 5uH R C5 L5 5uH C5 R.7 R.7 C5 C C53 C50 C C55 C5 CH Figure..ch L, R, SUB Outputs 9 Morgan Drive, Norwood, MA 0 voice: (7) fax: (7) apogee@apogeeddx.com CONTROLLED DOCUMENT: P_ _Rev05 Applying the DDX-000 in Binary Mode.doc DRN: PRELIMINARY Page of