Comparison of commutation transients of inverters with silicon carbide JFETs with and without body diodes.

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1 NORPIE 1 Comparison of commutation transients of inverters with silicon carbide JFETs with and without body diodes. Björn Ållebrand and Hans-Peter Nee Abstract An inverter could be built by using silcon carbide power switches only. This can be done by using SiC JFETs which can conduct current in both directions. An interesting question is how an inverter using SiC JFETs with a body diode compares with an inverter using SiC JFETs without body diodes. This will be discussed in this paper. SiC diode would have a far to high voltage drop compared to the SiC JFETs. I. INTRODUCTION Silicon carbide has been pointed out for long as the material that will replace silicon as the dominating semiconductor material for switching power applications []. The reason for this is that the drift resistance in SiC power devices can theoretically be up to 7 times lower than in silicon power devices of equal area while the drift region can sustain the same blocking voltage [6]. Additionally, silicon carbide can withstand higher temperatures than silicon. In inverters today the IGBT is the normally used component. Since an IGBT cannot conduct current in the reverse direction, an anti-parallell power diode is needed. However, a SiC JFET can conduct current in both forward and reverse direction eliminating the need for a power diode as first suggested in [1]. II. INVERTER TOPOLOGY In Fig. 1, a conventional topology for a voltage-type inverter is shown. This inverter utilizes IGBTs with anti-parallell diodes. Fig.. An inverter with SiC JFETs. III. PROPERTIES OF SIC JFETS The properties of SiC JFETs are not very well known compared to MOSFETs and IGBTs. Therefore, in this section the properties of SiC JFETs will be discussed. The JFET is a normally-on device. This means that if no voltage or zero voltage is applied to the gate the device is conducting. A negative gate voltage is required to turn the device off. Additionally, the threshold voltage (the turn-off voltage) for SiC JFETs is higher than compared to IGBTs and MOSFETs. It is in the range of -15 to -3 V. As discussed in [3], the gate capacitances of SiC JFETs will probably be significantly higher than comparable Si IGBTs. Together, the capacitance and the high gate voltage contributes to put higher demands on the gate drive circuit. M Fig. 1. A standard inverter with IGBTs and diodes. In Fig., it is shown how a voltage-type inverter can be designed utilizing SiC JFETs. Notice that no anti-parallell diodes are used. Therefore only six components are needed compared to twelve for the IGBT inverter. This also means that the hightemperature capabilities of the SiC JFETs can be utilized since there are no Si components. Additinally, as explained in [1], a B. Ållebrand is a Ph.D. Student at Electrical Machines and Power Electronics, Royal Institute of Technology (KTH), Stockholm, Sweden. H. Nee is Professor at Electrical Machines and Power Electronics, Royal Institute of Technology (KTH), Stockholm, Sweden. M However, there are different designs of SiC JFETs and in this section two different structures will be discussed, the buried gate JFET [7] and the vertical JFET [8]. A normal structure of a SIC buried gate JFET (bg-jfet)can be found in Fig. 3 and a SiC vertical JFET structure (VJFET) can be seen in Fig.. The main difference between a SiC bg-jfet and a SiC VJFET is the existence of the body diode in the VJFET. This body diode can be seen in Fig.. It is a bipolar diode and it is quite fast because it is a SiC diode, [9]. But due to the high bandgap of silicon carbide (around 3 ev) it has a forward voltage drop of approximately 3V, causing losses when conducting high currents. However, this diode can be used during the commutation procedure as shown in [5]. IV. COMMUTATION PROCEDURE Compared to a normal inverter the main difference is that there are no anti-parallell silicon diodes. This means that a different commutation strategy has to be used. How blanking

2 NORPIE 11 SOURCE N P GATE DRAIN Fig. 3. A buried gate JFET (bg-jfet) structure. p+ n n+ Source p+ n+ Drain Gate Fig.. A vertical JFET (VJFET) structure. times affect the commutation procedure for SiC JFETs without body diodes was investigated in []. It was shown that a strategy involving temporary short-circuits increases the switching losses. Therefore, postive blanking times should be used. This means that the commutation procedure for inverters utilizing SiC JFETs with body diodes will not be the same as for inverters utilizing SiC JFETs without body diodes. The commutation procedure is for SiC JFETs with body diodes is described completely in [5]. Below the two commutation procedures are described briefly. A. Commutation procedue for SiC JFET without internal SiC body diodes To understand the principle of operation the simple chopper circuit in Fig. 5 is studied. Assume that JFET Q1 is conducting and JFET Q is not conducting, i.e. turned off. When JFET Q1 is given a negative gate voltage in an attempt to turn it off, the current through JFET Q1 has no place to commutate. Therefore Q1 cannot be turned off and will continue to conduct in the saturation region, which means that there will be large losses during this time. This continues until JFET Q is turned on. Now, the current can begin to commutate through JFET Q. As soon as the current through JFET Q reaches the load current, JFET Q1 will turn off as the gate-source voltage across Q1 is close to the threshold voltage. At this stage the commutation process is completed. For the commutation process when JFET Q is turned off, JFET Q recieves a negative gate voltage. However, due to the reverse direction of the current through the JFET, it is not the gatesource voltage that controls the current through the JFET, but the gate-drain voltage. This applied negative gate voltage cannot change the current. Instead, the JFET has to operate in the saturation region. This situation will remain until JFET Q1 is turned on. At this stage the commutation process is initiated. The current through JFET Q1 increases, while the current through JFET Q decreases. When the current through JFET Q reaches zero, JFET Q will stop conducting immediately due to the negative gate voltage applied and the fact that it is now the gate-source voltage that determines if JFET Q is on or off. B. Commutation procedue for SiC JFET with internal SiC body diodes For a circuit utilizing SiC JFETs with internal SiC diodes there is not much difference in the commutation procedure from switches with anti-parallell diodes. The main difference is that the internal diodes are silicon carbide diodes, which means that there will be nearly no reverse recovery and that the voltage drop will be approximately 3 Volts due to the high bandgap of SiC JFETs, [9]. See [5] for a more detailed description of the commutation procedure. C. Main differences The main difference compared to circuits utilizing swicthes with anti-parallell diodes is that the JFET with no internal diode will operate for a short time period in the saturation region. V. SIMULATIONS Simulations have been performed using Capture/PSpice. A simple stepdown converter as shown in Fig. 5 was investigated. This could represent one bridge leg of a three-phase inverter. The dc-link voltage was 5 V and the load current was A. The PSpice parameters used in the simulations were based on SiC JFETs obtained from SiCED and from [7]. The internal body-diode of the SiC JFET was modelled as an ideal diode with a forward voltage drop of 3V. In these simulations a positive blanking time was used both in the turn-on of JFET Q1 and turn-off of JFET Q1. Lsigma Q1 Q Fig. 5. One bridge leg of a threephase inverter. In Fig. 6 the currents can be seen for both cases, for SiC JFETs with body diodes and for SiC JFETs without body diodes. They are very simular. The switching losses for a SiC JFET without body diode will be slightly higher than compared to a SiC JFET with a body diode, as seen in Tables I and II, assuming a switching frequency of 1 khz. I

3 NORPIE 1 VJFET turn-on Q1,66 turn-off Q,16 bg-jfet turn-on Q1 3,1 turn-off Q,33 TABLE I LOSSES AT TURN-ON OF JFET Q1 AND TURN-OFF OF JFET Q. VJFET turn-off Q1,58 turn-on Q,8 bg-jfet turn-off Q1,58 turn-on Q,8 TABLE II LOSSES AT TURN-ON OF JFET Q AND TURN-OFF OF JFET Q1. The losses when JFET Q1 turns off and JFET Q turns on are in the two cases almost equal. When JFET Q1 turns on and JFET Q turns off, however, the JFET with body diode will have slightly lower switching losses. Unfortunately, despite using a positive blanking time, a shortcircuit occurs causing excessive losses. The explanation to this is given in the next section. Current (A) Fig. 6. Currents during turn-off of Q. The solid line is the drain current through JFET Q with body diode. The dashdotted line is the drain current through JFET Q1 without body diode, and the dashed line is the current through the body diode of JFET Q. VI. SHORT-CIRCUIT CURRENT As shown in the simulations and in [5], a short-circuit occurs when Q1 turns on and Q turns off. This is because the lower JFET turns on unintentionally during the switching transient. Creating a short-circuit in the bridge leg as seen for the drain currents in Fig. 6. Why this phenomenon occurs can be explained by studying the switching transients for an inverter with SiC JFETs with internal body diodes as these switching transients are more simpler than inverters utilizing bg-jfets. In Figures 7-9 the switching transients can be seen. A. Phase I A negative voltage is applied to the gate of JFET Q1 and it turns off, meanwhile the current commutates over to the SiC body diode. Now both JFETs are blocking. B. Phase II Zero Volts is applied to the gate of JFET Q1 and the gatesource voltage rapidly drops towards the threshold voltage and JFET Q1 turns on. Now the JFET will enter the saturation region and the drain current will slowly increase and the body diode current will decrease towards zero. As soon as the body diode current reaches zero this phase ends. C. Phase III Since the current through the body diode is zero, JFET Q can start to block voltage. The gate-drain capacitance starts to charge. For this to happen a current is required and part of this current discharges the gate-source capacitance. Due to the high gate-drain capacitance of these JFETs, the gate-source capacitance of JFET Q discharges and the gate-source voltage quickly reaches the threshold voltage, and the JFET turns on. Now both JFETs are conducting and there is a short-circuit in main circuit. At the end of phase III JFET Q is blocking the dc-link voltage. D. Phase IV In this phase, JFET Q is in the off-state and JFET Q1 has been turned on. However, there will be oscillations in the circuit due to the stray inductance and the gate capacitances. Depending on these parameters, JFET Q may turn on again for a very short time as these oscillations are dampened. E. Phase V At the start of phase V the switching transients have decayed and steady state conditons applies. VII. HOW TO REDUCE THE SHORT-CIRCUIT CURRENT The short circuit which occurs in phase III has to be reduced or the low on-state losses of the SiC JFET cannot be properly utilized. The most obviuos choice would be to reduce the the gate-drain capacitance. This can be arranged by redesigning the structure of the SiC JFETs. But this will probably lead to a higher onstate resistance, which is not desired. Another way would be to increase the gate-source voltage from for instance -35 V to -7 V. A higher voltage, however puts higher demands on the gate drive circuit and the JFETs may be designed for a lower gate-source voltage, such as - V. This may lead to that the SiC JFET structure must be changed. But this is an effective way of reducing these short circuits currents.

4 NORPIE 13 Drain currents (A) A. New simulations with reduced gate-drain capacitance New simulations were performed with the gate-drain capacitance reduced to half. The results from these simulations can be found in tables III and IV. Assuming a switching frequency of 1 khz. VJFET turn-on Q1,6 turn-off Q 1,16 bg-jfet turn-on Q1,8 turn-off Q 1,38 TABLE III LOSSES AT TURN-ON OF JFET Q1 AND TURN-OFF OF JFET Q FOR LOWER GATE-DRAIN CAPACITANCE. Fig. 7. Drain currents for the turn-off of JFET Q and turn-on of JFET Q1. The solid line is the drain current through JFET Q1. The dotted line is the drain current through JFET Q Drain source voltages (V) VFFET turn-off Q1, turn-on Q, bg-jfet turn-off Q1,1 turn-on Q,8 TABLE IV LOSSES AT TURN-ON OF JFET Q AND TURN-OFF OF JFET Q1 FOR LOWER GATE-DRAIN CAPACITANCE Fig. 8. Drain-source voltages for the turn-off of JFET Q and turn-on of JFET Q1. The solid line is the drain-source voltage over JFET Q1. The dotted line is the drain-source voltage over JFET Q Gate source voltages (V) Fig. 9. Gate-source voltages for the turn-off of JFET Q and turn-on of JFET Q1. The solid line is the gate-source voltage over JFET Q1. The dotted line is the gate-source voltage over JFET Q Now the losses are approxiamtely four times lower and this is because the short-circuit current is lower. With these capacitance values, the switching losses are lower that the on-state losses. B. New simulations with increased turn off voltage In these simulations the turn off voltage was increased from -35 V to -7 V. As seen in Fig 1 the short-circuit current is nearly neglible. VIII. CONCLUSION Using an inverter with only SiC JFETs is possible. The different SiC JFET structures should not change the principle of operation much. The only difference is a small difference in the switching losses. SiC JFETs with internal body diodes are slightly better. A drawback is that short-circuit currents will occur and this increases the switching losses. The short-circuit currents are hard to reduce and must probably be dealt with by redesigning the structures of the SiC JFETs or increasing the turn off voltage. These problems are likely to be less significant with larger JFETs than those discussed in this paper. REFERENCES [1] B. Ållebrand and H.-P. Nee, On the possibility to use SiC JFETs in Power Electronic circuits, in Proceedings of the 9th Conference on Power Electronics and Applications, EPE 1, Graz, Austria, 1. [] B. Ållebrand and H.-P. Nee, On the choice of blanking times at turn-on and turn-off for the diode-less SiC-JFET inverter bridge, in Proceedings

5 NORPIE drain currents (A) time (s) Fig. 1. Drain currents for the turn-off of JFET Q and turn-on of JFET Q1. The dotted line is the drain current through JFET Q1. The solid line is the drain current through JFET Q. of the 9th Conference on Power Electronics and Applications, EPE 1, Graz, Austria, 1. [3] B. Ållebrand Gate Control and System Aspects of Silicon Carbide JFETs, Licentiate Thesis, KTH, Royal Institute of Technology,. [] M. Bhatnagar and B. Baliga, Comparison of 6H-SiC, 3C-SiC and Si for Power Devices, IEEE Transactions on Electron Devices, vol. 3, pp , March [5] C. Rebbereh, H. Schieling and M. Braun First inverter using silicon carbide power switches only, in Proceedings of the 1th Conference on Power Electronics and Applications, EPE 3, Toulouse, France, 3. [6] Dietrich Stephani - Prospects of SiC Power Devices from the state of the art to future trends, keynote speech at PCIM [7] Sang-Mo Koo, Design and Process Isuues of Junction- and Ferroelectric- Field effect Transostors in Silicon Carbide, Ph.D Thesis, KTH, Royal Institute of Technology, 3. [8] P. Friedrichs, H. Mitlehner et al., The vertical silicon carbide VJFET - a fast ans low oss solid state power switching device, in Proceedings of the 9th Conference on Power Electronics and Applications, EPE 1 [9] H. Lendenmann, A. Mukhitdinov, F. Dahlquist, H. Bleichner, M. Irwin, R. Söderholm, and P. Skytt,.5 kv H-SiC diodes with ideal forward characteristic, in Proceedings of 1 International Symposium on Power Semiconductor Devices and ICs, Osaka, 1.

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