Trench MOS Having Source with Waffle Patterns
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1 POSTER 2018, PRAGUE MAY 10 1 Trench MOS Having Source with Waffle Patterns Patrik VACULA 1, 2, Vlastimil KOTĚ 1, 2, Dalibor BARRI 1, 2 1 Dept. of Microelectronics, Czech Technical University, Technická 2, Praha, Czech Republic 2 STMicroelectronics s.r.o., Pobřežni 620/3, Praha, Czech Republic vaculpat@fel.cvut.cz, kotevlas@fel.cvut.cz, barridal@fel.cvut.cz Abstract. In power MOSFETs devices can be recognized trends to replace planar gate by trench gate structures. The power devices with planar gates are simplier to fabricate and have higher maturity than non-planar power MOSFETs. In contrast Trench MOSFETs have a better performance but are more complex to fabricate and due to this have lower maturity. Proposed paper describe two new trench MOSFET structures with different gate patterns with optimized drain to source to On resistance. In general, for power MOSFET s structures comparison the specific On resistance on area is used. This paper uses a normalized gate perimeter of element pattern, as an alternative figure of merit for a different trench MOSFET structure comparison because it is proportional to channel width and to drain to source resistance. Advantages and drawbacks of proposed new power MOSFETs structures are described. Keywords Trench MOSFET, gate patterns, specific On resistance, waffle pattern 1. Introduction Improvement of power Metal Oxide Semiconductor field effect transistor (MOSFET) properties are in general driven by applications need. It is possible to recognized two main trends. First motivation is coming from portable applications and requires devices miniaturization. The second one is driven by environment saving and requires higher devices efficiency. All of those needs are possible to reach by decreasing drain and source resistance per area of turned on a power transistor, named as a specific On resistance. 2. Introduction of Drift MOSFET Structure Planar power MOSFETs are still most widely used structures in Integrated Circuits (IC). Its main advantages are simple fabrication and due to this better maturity and reliable. One of the representation of lateral planar MOSFET is Drift MOSFET shown in Fig. 1. Let s the first consider simple DC electrical model of a low power MOSFET structure for gate electrode in linear region is Fig. 1. Lateral channel orientation of Drift MOSFET = X POLY L POLY (1) where I ch is a channel current between drain and source, V GS is a gate to source voltage and V TH is threshold voltage of the MOSFET. The µ is a charge-carrier effective mobility and C OX is a gate oxide capacitance per unit area. The W is a width of channel and L is a length of channel. And V DS is a voltage between drain terminals to source terminal. For the Drift MOSFET shown in Fig. 1, the width of the channel W is equal to L POLY dimension and length of the channel L is equal to the X POLY dimension. The total On-resistance R ON for the power MOSFET structure is obtained by the sum of all the resistances because they are considered to be in series in the current path between the source and the drain electrodes [1], [2] = !" + + (2) where R CS is resistance of source contacts and R N+ is source resistance, R ch is a channel resistance, R A is an accumulation resistance. The R JFET is a JFET resistance located in area between accumulation and drift region, R D is a Drift region resistance and R CD is resistance of drain contacts. Contributions from the drain and source contacts (R CS, R CD), the source resistance R N+, are very small compare to channel resistance R ch and will be neglected in this comparison. Based on [3] also the accumulation resistance R A, the JFET resistance R JFET and Drift region resistance R D are small compare to channel resistance R ch and will be considered as negligible in this comparison.
2 2 P. VACULA, V. KOTĚ, D. BARRI, TRENCH MOS HAVING SOURCE WITH WAFFLE PATTERNS In this work, the resistance of channel area R ch will be considered only. For MOSFET in linear region with drain to source voltage V DS on channel area the resistance in the inversion layer is as follows #$% = & '( ) *+ =, & -(. & /0. (3) 3. Introduction of Trench MOSFET Structure The Trench MOSFET shown in Fig. 2 is currently widely used architecture as overcoming the Drift MOSFET architecture and Double diffused MOSFET (DMOS) architecture in terms of specific On resistance. The MOSFETs using the trench gate allow to reach lower specific On-resistance hence vertical structure is enhancing the channel density. To improve the specific On resistance of the Trench MOSFET architecture the different trench gate pattern like Waffle [4] or hexagon in XtreMOS [5] was used. #$% = & '( ) *+ = 1, & -(. & /0. (4) X POLY Fig. 2. Vertical channel orientation of Trench MOSFET The Trench MOSFET in linear region with source to drain voltage V DS have channel resistance R ch-trmos as follows [3] To decrease channel resistance of the Trench MOSFET its width W should be made larger and its channel length L should be made as small as possible. Unfortunately, however reducing the channel length of the standard structure result in drastic reduction in its breakdown voltage [2]. From that reason, channel length L should be fixed, and we can simplify channel resistance by considering that is inversely proportional to width of channel W or to Perimeter of polysilicon gate P POLY #$% (5) 4. Trench MOSFET with Source with Waffle Pattern Due to improvement of specific On-Resistance the new architecture of Trench MOSFET with Source with Waffle pattern is proposed and shown in Fig. 3. New Trench MOSFET is vertical structure with lateral connection of all terminals. A gate is vertical trench, a source and a bulk are on top and a drain is at the bottom and is laterally connected. A bulk implant is located between gates and is on surface connected via salicide with the source. When spacing between gates segments S POLY is smaller than dimension of gate segment X POLY then sum of gates perimeters, (which is equivalent to channel width) is larger than for conventional Trench MOSFET (Fig. 4). Trench MOSFET with source with Waffle pattern by using segmented trench gates, have a larger gate perimeter (equivalent to channel width) than conventional Trench MOSFET (Fig. 2). Due to this, we can expect lower specific On resistance for Trench MOSFET with source with Waffle pattern. Fig. 3. Proposal of new Trench MOS with Source with Waffle pattern
3 POSTER 2018, PRAGUE MAY 10 3 From equations (7) and (8) we can get formula for side length of regular polygon s as follows ; = 2 G H 4 ABC D E. (9) I By insertion (9) to equation (6) we can get direct relation between perimeter P P of regular polygon on number of sides n and on its area A P as follows a) b) Fig. 4. Top view on channel width for: a) Trench MOSFET b) improved channel width of Trench MOSFET with Source with Waffle pattern 8 = = 2 9 GH 4 ABC D E. (10) I For comparison of polygon let s consider unit polygon area equal to one. Than we get following Tab Trench MOSFET with Triangle Gate Pattern The Trench MOSFET with Source with Waffle pattern overcome conventional Trench MOSFET structures because by using multi square trench gate we can fit more gate perimeter per area. To find even better topology we have to find 2D polygon with even larger perimeter P P per area first. Let s consider basic formulas for calculation of the perimeter of regular polygon P P and area of the regular polygon A P with n sides and with length of side s 8 3 = 9 ; (6) < = = 1 >? 9 ; = 1 >? 8= (7) where ap is an apothem and define shortest distance from side of polygon to the center and should be calculated as follows >? ABC D E. (8) Polygon triangle square pentagon hexagon circle Sides n infinite Perimeter P P Tab. 1. Dependence of Perimeter of regular polygon on number of polygon sides n for polygons with unit area (A P=1). From Tab. 1 we can see that square is not an optimal polygon in terms of perimeter. The largest perimeter for unit area is for polygon with triangle shape. Another conclusion is that when number of polygon sides is increase the perimeter is decreased. To get Trench MOSFET with lower specific On resistance we have to choice trench gate with triangle pattern shown in Fig. 5. The higher perimeter means higher channel width and it means lower resistance. Fig. 5. Proposal of new Trench MOSFET with Triangle gate pattern (Triangle MOSFET)
4 4 P. VACULA, V. KOTĚ, D. BARRI, TRENCH MOS HAVING SOURCE WITH WAFFLE PATTERNS The 3D visualization and patterns proposals described in the paper was defined in cooperation with Ing. Miloš Vacula from STMicroelectronics in Prague. The trench MOSFET with source with waffle pattern and trench MOSFET with triangle gate pattern proposals was defined in cooperation with Ing. Adam Kubačák from STMicroelectronics in Prague. Fig.6. Comparison of Drift MOSFET with Trench MOSFET with Trench MOSFET with Source with Waffle pattern and with MOSFET with Triangle gate pattern based on normalized gate perimeter (equivalent to channel width) When spacing between polysilicon gates S POLY is smaller than dimension of polysilicon gate X POLY then sum of gates perimeters which is equivalent to channel width is larger than for Trench MOSFET with source with Waffle pattern or for conventional Trench MOSFET (Fig. 6). The trench MOSFET with Triangle gate have lower specific On resistance than Trench MOSFET with source with Waffle pattern or conventional Trench MOSFET hence Trench MOSFET with Triangle gate have larger gate perimeter (equivalent to channel width) per area. 5. Conclusion In this publication was described two new Trench MOSFET structures with optimized specific On resistance. The first structure is Trench MOSFET with Source with Waffle pattern and second structure is Trench MOSFET with Triangle gate pattern. If gates segments spacing are smaller than segment dimensions then booth new structure have better specific On resistance than Drift MOSFET or Trench MOSFET. Smallest specific On resistance is reach for Trench MOSFET with Triangle gate pattern. Due to sharp edges of gate segment the lower break down voltage is expected for Triangle gate pattern. Trench MOSFET with Source with Waffle pattern should be good compromise due to lower specific On resistance and higher break down voltage. For different trench MOSFET structures comparison, the normalized gate segment perimeter was used as alternative figure of merit to specific On resistance. Acknowledgements Research described in the paper was supervised by prof. Ing. Miroslav Husák, CSc, FEE CTU in Prague and it is part of the CTU SGS grant No. SGS17/188/OHK3/3T/13 (Mikro a nanostruktury a soucastky). References [1] BALIGA, B. J. Advanced Power MOSFET Concepts. New York (NY, USA): Springer, [2] RAKESH, V., NARESH, P. Comparative study of power MOSFET device structures. Indian Journal of Pure & Applied Physics, 2005, vol. 43, no. 12, p [3] NARAZAKI, A., MARUYAMA, J., KAYUMI, T., HAMACHI, H., MORITANI, J., HINE, S. A 0.35 um Trench Gate MOSFET with an ultra low on state resistance and a high destruction immunity during the inductive switching. In The 12 th International Symposium on Power Semiconductors and IC's (ISPSD 2000). Toulouse (France), 2000, p [4] VARADARAJAN, K. R., CHOW, T. P., WANG, J., LIU, R., GONZALEZ, F. 250V Integrable Silicon Lateral Trench Power MOSFETs with Superior Specific On-Resistance. In Proceedings of the 19th International Symposium on Power Semiconductor Devices and IC's, Jeju Island (South Korea), 2007, p [5] MOENS, P., BAUWENS, F., DESOETE, B., BAELE, J., VERSHININ, K., ZIAD, H., SHANKARA NARAYANAN, E.M., TACK, M. Record-low on-resistance for 0.35 μm based integrated XtreMOS TM Transistors. In Proceedings of the 19th International Symposium on Power Semiconductor Devices and IC's, Jeju Island (South Korea), 2007, p About Authors... Patrik VACULA was born in Humenné, Slovak Republic in Master s degree in Electronics and Multimedia Communications Engineering, he completed at TU FEI in Kosice in Currently he is working at STMicroelectronics as member of Technical Staff IC layout engineer responsible for entire BE IC development flow including power MOS integration. He is a PhD. student in the Department of Microelectronics at the Czech Technical University where his research interests is power MOSFET optimization. Vlastimil KOTE was born in Roudnice nad Labem, Czech Republic in He received his Bachelor s degree in electrical engineering from Czech Technical University in Prague in 2009, and Master s degree in electrical engineering from CTU in Prague in Currently, he is working at STMicroelectronics, Prague as IC Layout Staff Engineer. He attends the post-gradual study in the Department of Microelectronics at CTU in Prague where his research interests include structures of semiconductor devices, physical design, electrical circuit theory, and IC design methodology development. Dalibor BARRI was born in Prague, Czech Republic in He received his B.Sc. and M.Sc. degree in Electronics from the Czech Technical University (CTU), Prague, in
5 POSTER 2018, PRAGUE MAY and 2007, respectively. He worked at EMicroelectronics for five years as an analog IC front-end designer. At present time, he works at STMicroelectronics as an analog IC back-end designer. He is a Ph.D. student, and his topic of the thesis is to invent a novel tool for an automatic or semi-automatic layout of the analog integrated circuits.
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