GaN Reliability Through Integration and Application Relevant Stress Testing

Transcription

1 GaN Reliability Through Integration and Application Relevant Stress Testing APEC 2018 PSMA Sponsored Industry Session: Reliability and Ruggedness How to Address these Challenges in Wide Bandgap Semiconductor Devices Thursday March 8 th, 2018 Dr. Nick Fichtenbaum, Co-Founder & VP Engineering Nick.Fichtenbaum@navitassemi.com

2 GaN Device Implementations Fundamental GaN Material Properties G D 10 30V S1 S2

3 Gate Protection is Paramount in GaN dmode (Dielectric Based Gate) Max V GS similar to Si devices Need to manage max negative gate bias on GaN for reliability Slew rate control important with multiple chips in a package emode (pgan Based Gate) G S1 D S V V GS needs to be managed Clamp diodes & current based-drive Layout optimization GaN Power IC (integrated regulator + driver) C dv/dt Induced Turn-on concern Negative gate drive Minimize parasitics GaN Power IC (integrated driver)

4 Clean, Controlled FET Gate Discrete driver Gate loop inductance creates overshoot (even with good layout) idrive GaN Power IC No gate loop parasitic Clean and fast gate signal 2 V Overshoot Discrete Driver & Discrete FET GaN Power IC V GS V GS 4V Undershoot

5 Integrated Drive Simple & Robust Wide Range V CC (10-30V) Total layout flexibility & simplicity Regulator ensures V GS within SOA Under voltage lockout protects the driver & FET when full power supply is not available PWM Hysteresis for noise immunity Gate protected from external noise (Not pinned out of package) No inductance or ringing in gate loop

6 Shoot-Through Protection in Half-Bridge Half-Bridge GaN Power IC Non-Overlapping Logic Input (Typical Operation) Gate-HighSide Overlapping Logic Input (Power IC Protection Mode) Gate-HighSide INPUT- HighSide Gate-LowSide INPUT- HighSide Gate-LowSide Non-overlapping Input Overlapping Input INPUT- LowSide INPUT- LowSide High-side and Low-side gates never overlap due to shoot-through protection in power IC

7 Die Stress Package Stress Is Typical Si JEDEC Qual Sufficient? Typical Si-Based Qual Plan Reference Test Conditions Duration Lots S.S. Preconditioning (MSL1): JESD22-A113 Moisture Preconditioning + 3x reflow: J-STD-020 HAST, UHAST, TC & PC N/A JESD22-A104 Temperature Cycle: -55 C / 150 C 1,000cy 3 77 JESD22-A122 Power Cycle: Delta Tj = 100 C 10,000cy 3 77 JESD22-A110 Highly Accelerated Stress Test: 130 C / 85%RH / 100V V DS 96hrs 3 77 JESD22-A108 High Temperature Reverse Bias: 150 C / 520V V DS 1,000hrs 3 77 JESD22-A108 High Temperature Gate Bias: 150 C / 6V V GS 1,000hrs 3 77 JS Human Body Model ESD N/A 1 3 JS Charged Device Model ESD N/A 1 3 New GaN Standards Needed Courtesy: Stephanie Watts Butler (Texas Instruments) and Tim McDonald (Infineon) From GaNSPEC DWG to JEDEC JC-70.1: An update on industry qualification standards for Gallium Nitride power conversion devices

8 Beyond JEDEC -- Lifetime based on HTRB? Bodos Power Electronics Conference 2017, Munich Airport Hilton, December 05, 2017 Lifetime = A (V γ ) (e E A kt) HTRB 100 ppm is > 20 yrs at application condition P. Gassot, et al. Bodo Power Conference Munich, Dec. 2017

9 Beyond JEDEC Implications for GaN Power ICs? How2PowerToday: September 2015 issue Bodos Power Electronics Conference 2017, Munich Airport Hilton, December 05, 2017

10 Use Mission Profile to Define GaN Qualification Quality Objectives (Typical app. lifetime, FIT rates) Application Profile (Voltage, Current, Frequency) Test Methodologies (Removal of defects) Failure Modes (Device Structure, Process) GaN Power IC Qualification Plan Lifetime Models (HTOL, HTRB, GaN IC) Production Release

11 38 mm Typical Application (Consumer Chargers) MacBook <100 khz <6.5 W/in 3, 92% Navitas ~300 khz 24 W/in 3, 94% = 45 cc cased ACF (ZVS) Topology 300kHz 1 MHz 120 V 240 V AC 15.5 mm 46 mm

12 38 mm Application Profile for ACF Charger Navitas ~300 khz 24 W/in 3, 94% = 45 cc cased Full Power Mode Voltage Current Turn-ON Turn-OFF Frequency, Duty Cycle 15.5 mm 46 mm Application Factors Voltage ( V) Current (1-3 A) Frequency (100-1,000 khz) Temperature ( C) Duty Cycle Turn-on / Turn-off Profile ZVS vs. Hard-Switching

13 ZVS Application Profile (FET) 1 I DS vs. V DS (Load Line) 4 3 V DS PWM 3 High-Side Diode Conduction I DS ON-State 4 2 Soft-Switching or ZVS (Zero-Voltage Switching) represents an application relevant stress on the power FET 2 1 Blocking Mode

14 ZVS Application Profile (IC) V CC Stress applied to internal circuits V GS Ringing Max V GS C dv dt Stress applied to driver on each switching cycle Driver run at application frequency & duty cycle Driver components stressed

15 ZVS High Temp Op Life (HTOL) Circuit 500 khz V CC PWM V DD REG D VSW D Z dv/dt V DD + - V CC S D il Low side gate 500 khz PWM V DD REG HTOL Circuit Variables D Z dv/dt S Voltage Current Frequency Temperature Duty Cycle L-C load applied to half-bridge topology along with complementary inputs & dead time setting to achieve soft-switching Power consumption is the only loss elements (DUT, Inductor) since energy is recycled many cells in parallel Circuit allows for same application stress on GaN Power IC as customer application (Voltage, Current, Frequency) Applies application conditions to the driver & integrated IC so power IC is also qualified in the same test

16 ZVS HTOL Applied to Statistical Sample Sizes Matches all elements of application profile FET & IC Many cells in parallel Statistical sample sizes Low total power consumption Conditions changeable to develop lifetime and acceleration models HTOL Mother Board Qualification Lifetime Models Early Life Failure Rate 3 Lots x 77 Parts Voltage Current Frequency Temperature 3 Lots x 1,000 Parts

17 HTOL-based Lifetime Model T=125 C, Voltage Acceleration Voltage/ Temperature Time to Fail hrs 1 (Voltage) n= V= 600 V, Temperature Acceleration Time to Fail hrs e Ea=0.62eV kt

18 Lifetime Estimation in Charger Application (ACF) E a 1 1 ( ) Temperature Acceleration Factor AF temp = e k T application T reliability Voltage Acceleration Factor AF voltage = ( V reliability ) n V application E a = 0.62eV n = 21 Total Acceleration Factor AF Total = AFTE MP x AFVOLTAGE Lifetime estimate in application = AFTo tal x Time to failure in reliability (TTFreliability) ACF Charger Full-Power Profile AC line Voltage (V) Rectified AC voltage (V) Reflected Voltage (V) Switch Voltage (V) Full power Temp ( C) Lifetime = AFTotal x TTFre liability = V AC input Predicted lifetime in charger application (ACF) exceeds 10yr lifetime requirement

19 Die Stress Package Stress Beyond JEDEC Qual Plan for GaN GaN-Based Qual Plan Reference Test Conditions Duration Lots S.S. Preconditioning (MSL1): JESD22-A113 Moisture Preconditioning + 3x reflow: N/A J-STD-020 HAST, UHAST, TC & PC JESD22-A104 JESD22-A122 Temperature Cycle: -55 C / 150 C Power Cycle: Delta Tj = 100 C 1,000cy ,000cy 3 77 Lifetime Models (HTOL, HTRB) JESD22-A110 JESD22-A108 JESD22-A108 Highly Accelerated Stress Test: 130 C / 85%RH / 100V V DS 96hrs 3 77 High Temperature Reverse Bias: 150 C / 520V V DS 1,000hrs 3 77 High Temperature Gate Bias: 150 C / 6V V GS 1,000hrs 3 77 Failure Modes Established JESD22-A108 High Temperature Operating Life 1,000hrs 3 77 JS Human Body Model ESD N/A 1 3 JS Charged Device Model ESD N/A 1 3 Application Specific HTOL Test Bench