DRF2018A113 Low Power Audio FM Transmitter Module V1.00

Transcription

1 DRF2018A113 Low Power Audio FM Transmitter Module V1.00 Features Audio PLL transmitter module 433/868/915Mhz ISM frequency band 13dBm Max. output power Phase noise: -94dBc/Hz Multiple channels Audio response:55~22khz Supply voltage 4.2~9.0V Application Car Audio /Car Speaker Wireless Microphone Ordinary sound box DESCRIPTION DRF2018A113 is a low-cost sub-1 GHz FM transmitter module designed for operations in the unlicensed ISM (Industrial Scientific Medical) and it aims at UHF wireless audio applications. The transmitter module consists of RF transmitting, audio amplifying, stereo modulation and MCU frequency control circuits. Users only need to add an antenna, au audio socket/mic and a DIP switch for frequency setting to construct a wireless audio transmitting system. With audio receiver module DRF2018A010, the communication distance can reach 200~300 meters in open area. MIC MIC Amplification DRF2018A113 Mono Amplification RF transmitting Stereo Amplification Figure 1: DRF2018A113 Transmitting System Revision 1.00 Page 1 of 10 Dec. 2010

2 PIN FUNCTIONS DRF2008A113 Figure 2: DRF2018A113 Pin Layout PIN Name Function Description 1 MODE Input Mode selection. High MCU mode; Low ROM mode 2 H/L Input High/low output power selection. Low 12±1dBm; High 1±1dBm 3 GND Ground Ground (0V) 4 VDD --- Test port 5 AF --- Test port 6 TXEN Input PA Enable. Low PA is off; PLL is on. ANT port radiation power: -56dBm High PA is on 7 GND Ground Ground (0V) 8 ANT Output 50Ω impedance. Recommended: connecting external antenna with a serial 10nH inductor. 9 Cm Input Common port. In ROM mode, it should be set to logic High 10 D4 Input ROM control bit (5 th ) for selecting frequency band. D7~D4 can select 16 frequency bands. D7~D5 are connected to fixed level (High/Low) on board so users need to specify the frequency band in part name. For more details, please check the ROM Logic Control Table on Page D3 Input ROM control bit (4 th ) for selecting channel. It is used together with D2~D0 for 16- channel selection 12 D2/CLK Input ROM control bit (3 rd ) / Clock input port of MCU. On the rising edge of clock, data is input to 18-bit shift register of serial interface 13 D1/DATA Input ROM control bit (2 nd ) / Data input port of MCU. The LSB is input first and the last two bits is group identification code. 14 D0/EN Input ROM control bit (1 st ) / Enable pin. At high level data in shift register will be loaded in latch distinguished b group identification code. 15 GND Ground Ground (0V) 16 BATT Power Positive pole of power supply 17 L_in Input Stereo signal input, Left channel Revision 1.00 Page 2 of 10 Dec. 2010

3 18 GND Ground Ground (0V) 19 R_in Input Stereo signal input, Right channel 20 MIC Input MIC voice signal input 21 GND Ground Ground (0V) 22 LINE Input Mono signal input Table 1 DRF2018A113 Pin functions ELECTRICAL SPECIFICATIONS Symbol Parameter (condition) Min. Typ. Max. Units VDD Supply Voltage V Temp Operating temperature range C RH Operating relative humidity % Freq Frequency range MHz MHz MHz C FREQ Crystal Frequency 20 MHz Mod Modulation type FM CH SP Channel space KHz IDD Transmit 55 ma Pout Output H/L= dbm dbm Pn Phase Noise@10KHz Dev.,50Hz loop bandwidth -113 dbm Z IN Audio input impedance 600 ohm F RES Transmitting frequency 55 22K Hz FDEV Modulation 1KHz, 15mV ±18 ±20 ±22 KHz SINAD Signal to noise and distortion ratio@ 1KHz signal 53 db & 40K F DEV SNR Signal to noise ratio@1khz signal & 40K F DEV 54 db D MOD Modulation distortion@1khz signal 1.0 % ZANT Antenna Impedance 50 Ohm Table 2 DRF2018A113 Electrical Specifications Revision 1.00 Page 3 of 10 Dec. 2010

4 ABSOLUTE MAXIMUM RATINGS DRF2008A113 Symbol Parameter Min. Max. Units VCC Supply Voltage V VI Input voltage -0.3 VCC+0.3 V VO Output voltage -0.3 VCC+0.3 V TST Storage temperature C Table 3 DRF2018A113 Maximum Ratings APPLICATION INFORMATION 1. MCU MODE If MODE pin is set to High, DRF2018A113 will work in MCU mode under which D2/CLK, D1/DATA and D0/EN are functioned as input ports of serial data. Binary serial data is input from D1/DATA pin and transformed to parallel data by internal serial-to-parallel converting circuit. After analyzing group identification code (GIC), data will be transferred to reference frequency-dividing counter and channel frequency-dividing counter. Each bit of data is read into shift register at the rising edge of clock signal. LSB is input first and the last two bits (GIC) are used to decode the address of internal registers. At the rising edge of EN pin, data in shift register is loaded into counter designated by GIC. >=1us >=0.2us >=0.2us CLK DATA LSB >=0.2us bit1 bit2 bit3 GC2 MSB GC1 >=0.1us >=0.2us >=0.1us EN >=0.2us Figure 3: DRF2018A113 Serial Port Timing Sequence Notes: ⑴ LSB is input first to shift register ⑵ Module being powered on, the reference frequency divider is configured first and then the channel frequency divider. GIC1 (MSB) GIC2 (LSB) Counter Typ. Revision 1.00 Page 4 of 10 Dec. 2010

5 1 0 Channel frequency-dividing counter 1 1 Reference frequency-dividing counter Table 4 Group Identification Code 1.1 Reference Frequency-dividing Counter R Reference frequency-dividing counter provides reference frequency for PLL. It includes a fixed 1/2 divider and a 10-bit programmable divider. The 10-bit divider can program the division ratio between 3 and Due to the fixed 1/2 divider, the total division ratio for reference divider can be set from 6 to LSB MSB R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 GIC2=1 GIC1=1 Table 5 Counter R Command Word Division ratio of the programmable 10bit R counter: Division ratio (R) R10 R9 R8 R7 R6 R5 R4 R3 R2 R Table 6 Division ratio of Counter R R=R1*2 0 +R2* R10*2 9 (R 3) 1.2 Channel Frequency-dividing Counter N The programmable frequency-dividing counter consists of a 4-bit swallow counter and a 12-bit pulse counter, in conjunction with the 64/68 prescaler to provide division ratio range from 192 to LSB MSB N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 N15 N16 GC2=0 GC1=1 ---Swallow counter Pulse counter GIC Table 7 Counter N Command Word Revision 1.00 Page 5 of 10 Dec. 2010

6 Swallow counter division ratio (A) Division ratio (A) N4 N3 N2 N Table 8 Swallow Counter Division Ratio A=N1*2 0 +N2* N4*2 3 Division ratio range: 0 ~ 15 Pulse counter division ratio (B) Division ratio (B) N16 N15 N14 N13 N12 N11 N10 N9 N8 N7 N6 N Table 9 Pulse Counter Division Ratio B=N5*2 0 +N6* N16*2 11 Division ratio range: 3 ~ 4095 (B A) Total division ratio of programmable Counter N: N=4*(16*B+A) (B A) Division ratio range: 192 ~ Configuration Example VCO frequency 863MHz and Reference frequency 25 KHz (@ 20MHz crystal) 1) Total number of frequency division: 2R=20MHZ 25KHz = 800 2) Programmable division ratio: R=800 2=400 3) R in Binary format (10bits): R= ) Group identification code: 11 5) Counter R command word (12bits) LSB MSB ) Total number of frequency division: 4 (16*B + A) = 863MHz 25KHz = *B + A = ) Pulse counter division ratio (12 bits): B = Int ( ) =539 = ) Swallow counter division ratio (4 bits): A= *539=6=0110 9) N in Binary format (16bits): ) Group identification code: 10 Revision 1.00 Page 6 of 10 Dec. 2010

7 11) Counter N command word (18bits) LSB MSB Timing sequence example Based on the calculation result from the foresaid example, two command words can be sent by external MCU according to the timing sequence diagram showed as below: 12-bit Counter R first 18-bit Counter N second Figure 4: Timing Sequence Example 2. ROM MODE If MODE pin is set to Low, DRF2018A113 will work in ROM mode. The 8-bit data pins (D0~D7) are used to select bandwidth (1.5~30MHz). ROM Control Logic Table contains the preset frequency points in different frequency bands (Referring to Table7). In this mode no external MCU is needed so the development time and cost can be minimized to the least. 433MHz Frequency Band with 16 channels Channel D7 D6 D5 D4 D3 D2 D1 D0 TX Freq.(MHz) RX Freq. (MHz) Revision 1.00 Page 7 of 10 Dec. 2010

8 MHz Frequency Band with 7 channels Channel D7 D6 D5 D4 D3 D2 D1 D0 TX Freq.(MHz) RX Freq. (MHz) MHz Frequency Band with 16 channels Channel D7 D6 D5 D4 D3 D2 D1 D0 TX Freq.(MHz) RX Freq. (MHz) Table 10 ROM Control Logic Table Revision 1.00 Page 8 of 10 Dec. 2010

9 Connection diagram in ROM mode DRF2008A113 Figure 5: Connection Diagram in ROM Mode Mechanical Data Unit: mm Figure 6: DRF2018A113 Mechanical Data Revision 1.00 Page 9 of 10 Dec. 2010

10 Ordering Information DRF2008A113 DRF 2018 A S Num Symbol Meaning 1 Module category RF module 2 Module type 2018 series 3 Module Function Audio FM module 4 Communication way 0: Receiver, 1: Transmitter, 2: Transceiver 5 Power 13dBm output power 6 Freq. Band 043: 433MHz 7 Package SMD package Table 11 Ordering information Dorji Applied Technologies A division of Dorji Industrial Group Co., Ltd Add.: Xinchenhuayuan 2, Dalangnanlu, Longhua, Baoan district, Shenzhen, China Tel: Fax.: sales@rfmodule.me Web: Dorji Industrial Group Co., Ltd reserves the right to make corrections, modifications, improvements and other changes to its products and services at any time and to discontinue any product or service without notice. Customers are expected to visit websites for getting newest product information before placing orders. These products are not designed for use in life support appliances, devices or other products where malfunction of these products might result in personal injury. Customers using these products in such applications do so at their own risk and agree to fully indemnify Dorji Industrial Group for any damages resulting from improper use. Revision 1.00 Page 10 of 10 Dec. 2010