A SURVEY ON RECONFIGURABLE LOW COMPLEXITY ARCHITECTURES FOR FIR FILTERS

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1 A SURVEY ON RECONFIGURABLE LOW COMPLEXITY ARCHITECTURES FOR FIR FILTERS 1 S.KARTHICK, 2 Dr. S. VALARMATHY, 3 R.Nirmal Kumar, 1 Assistant Professor (Sr.G), 2 Professor& Head, 3 Assistant Professor Department of Electronics and Communication Engineering, Bannari Amman Institute of Technology, Sathyamangalam. Abstract -Finite Impulse Response (FIR) filters are widely applied in multistandard wireless communications. The two key requirements of FIR filters are reconfigurability and low complexity. The researches have been introduced many architectures for above key metrics.for reconfigurable FIR filter, two architectures was implemented, namely Constant Shift Method [CSM] and Programmable Shift Method [PSM]. The complexity of linear phase FIR filters is dominated by the number of adders (subtractors) in the coefficient multiplier. The Common Subexpression Elimination (CSE) algorithm was introduced for reducing the number of adders in the multipliers and also dynamically reconfigurable filters can be efficiently implemented based on Canonic Signed Digit (CSD) representation of coefficients. It is well known that the two classes of common subexpression elimination techniques(verticaland horizontal) minimize the two main cost metrics namely logic operators and logic depths in realizing finite impulse response (FIR) filters. A new CSE algorithm using binary representation of coefficients was imtroduced for the implementation of higher order FIR filters with a fewer number of adders than CSD-based CSE methods A new greedy CSE algorithm based on CSD representation of coefficients multipliers was introduced for implementing low complexity higher order FIR filters. Design examples shows that the filter architectures offer power reduction and good area and speed improvement over the existing FIR filter implementation. Keywords- Software Defined Radio (SDR), channelizer, FIR filter, common subexpression elimination. 148 I. INTRODUCTION FIR DIGITAL filters find extensive applications in mobile communication systems for applications such as channelization,channel equalization, matched filtering, and pulse shaping, due to their absolute stability and linear phase properties.the filters employed in mobile systems must be realized to consume less power and operate at high speed. Recently, with the advent of software defined radio (SDR) technology,finite impulse response (FIR) filter research has been focused on reconfigurable realizations. The fundamental idea of an SDR is to replace most of the analog signal processing in the transceivers with digital signal processing in order to provide the advantage of flexibility through reconfiguration.this will enable different air-interfaces to be implemented on a single generic hardware platform to support multistandard wireless communications [1].The aim of the wireless communication receiver is to realize its applications in mobile, low area and low power is possible by implementation of FIR channel filter. Wideband receivers in SDR must be realized to meet the stringent specifications of low power consumption and high speed. Reconfigurability of the receiver to work with different wireless communication standards is another key requirement in an SDR. The most computationally intensive part of an SDR receiver is the channelizer since it operates at the highest sampling rate [2]. It extracts multiple narrowband channels from a wideband signal using a bank of FIR filters, called channel filters. In [3], the filter multiplications are done via state machines in an iterative shift and add component and as a result of this there is huge savings in area. For lower order filters, the approach in [3] offers good trade-off between speed and area. But in general, the channel filters in wireless communication receivers need to be of high order to achieve sharp transition band and low adjacent channel attenuation requirements. For such applications, the approach in [3] results in low speed of operation. The complexity of FIR filters is dominated by the complexity of coefficient multipliers. It is well known that the common subexpression elimination (CSE) methods based on canonical signed digit (CSD) coefficients produce low complexity FIR filter coefficient multipliers [4]. The goal of CSE is to identify multiple occurrences of identical bit patterns that are present in the CSD representation of coefficients, and eliminate these redundant multiplications. A modification of the 2-bit CSE technique in [4] for identifying the proper patterns for

2 elimination of redundant computations and to maximize the optimization impact was proposed in [5]. In [6], the technique in [4] was modified to minimize the logic depth (LD) (LD is defined as the number of adder-steps in a maximal path of decomposed multiplications [7]) and thus to improve the speed of operation. In [8], we have proposed the binary common subexpression elimination (BCSE) method which provided improved adder reductions and thus low complexity FIR filters compared to [3] [6]. In [9], a method based on the pseudo floating point method was used to encode the filter coefficients and thus to reduce the complexity of the filter. But the method in [9] is limited to filter lengths less than 40. In general, the methods in [3] [7] are only suitable for application specific filters where the coefficients are fixed and hence not suitable for reconfigurable filters. The works in [11] [15] and [10], [16] present reconfigurable FIR filter architectures. In [11], a CSD based digit reconfigurable FIR filter architecture was proposed. This architecture was independent of the number of taps because the number of taps and nonzero digits in each tap were arbitrarily assigned.the intention of the authors was to reduce the precision of coefficients and thus the filter complexity without affecting the filter performance. But the architecture in [11] demanded huge hardware resources and this makes the method infeasible for power constrained SDR receiver applications. In [12], a highspeed programmable CSD based FIR filter was proposed. The filter architecture consisted of a programmable CSD based Booth encoding scheme and partial product Wallace adder tree. The final adder was a carry lookahead adder. Though this method offered a high speed solution, the resulting filters consume more power. Another high-speed programmable FIR filter based on polyphase decomposition was proposed in [13].However, this method used the built-in block multipliers of Virtex II field-programmable gate array (FPGA) and therewas no consideration for the complexity reduction of the FIR filter. In [14], the concept of reconfigurable multiplier block (ReMB) was introduced. The ReMB will generate all the coefficient products and a multiplexer will select the required ones depending on the input. It was shown that by pushing the multiplexer deep into the multiplier block design, the redundancy can be reduced. The resulting specialized multiplier design can be more efficient in terms of area and computational complexity compared to the general-purpose multiplier plus the coefficient store [14]. But the ReMB proposed in [14] has its area, power, and speed dependent on the filter-length making them inappropriate for higher order FIR filters. In [15], a multiplexed multiple constant multiplications (MMCM) approach was proposed. This method 149 considers the coefficient set as a constant and uses the graph dependence (GD) algorithms for reducing redundancy. But this method follows a directed acyclic graph structure which will result in long LD and thus gives lower speed of operation. In this paper, CSD AND BINARY based CSE algorithgms(vertical and horizontal) are investigated A new CSE method using a binary representation of filter coefficients, which can completely exploit the symmetry of FIR filter coefficients. The complexity of coefficient multipliers can be reduced by combining three techniques: BHSE, BVSE, and BSSE.It offers a good tradeoff between LD and LOs, particularly for higher order filters. This paper is organized as follows. The CSE method is reviewed in section II. The greedy common subexpression elimination algorithm is proposed in Section III. In Section IV, the CSE and BINARY CSE FIR filter architecture is introduced. HCSE and VCSE methodintroduced in V. Section VI provides the conclusion.and future work. 2 COMMON SUBEXPRESSION ELIMINATION A CSE algorithm using binary representation of coefficients for the implementation of higher order FIR filter with a fewer number of adders than CSD-based CSE methods is used. CSE method is more efficient in reducing the number of adders needed to realize the multipliers when the filter coefficients are represented in the binary form. The observation is that the number of unpaired bits (bits that do not form Common Subexpressions (CSs)) is considerably few for binary coefficients compared to CSD coefficients, particularly for higher order FIR filters. The Binary CSE (BCSE) algorithm deals with elimination of redundant binary common subexpression that occurs within the coefficients. The BCSE technique focuses on eliminating redundant computations in coefficient multipliers by reusing the most common binary bit patterns (BCSs) present in coefficients [9]. The number of BCSs that can be formed in an n-bit binary number is 2n (n + 1). For example, a 3-bit binary representation can form four BCSs, which are [0 1 1], [1 0 1], [1 1 0] and [1 1 1]. These BCSs can be expressed as [0 1 1] = x2 = x + x (1) [1 0 1] = x3 = x + x (2) [1 1 0] = x4 = x + x (3) [1 1 1] = x5 = x + x + x (4) where x is the input signal. Note that other BCSs such as [0 0 1], [0 1 0] and [1 0 0] do not require any adder for implementation as they have only one nonzero bit. A straightforward realization of above BCSs would

3 require five adders. However x2 can be obtained from x4 by a right shift operation (without using any extra adders). x2 = x + x = (x + ) = x4 (5) Also, x5 can be obtained from x4 using an adder: x5 = x + x + x = x4 + x. (6) Thus, only three adders are needed to realize the BCSs x2 to x5. The number of adders required for all the possible n-bit binary subexpressions is 2n 1 1. The number of adders needed to implement the coefficient multipliers using the binary representation-based BCSE is considerably less than the CSD-based CSE methods. 3 GREEDY COMMON SUBEXPRESSION ELIMINATION ALGORITHM The new CSE algorithm combines three techniques, binary Horizontal Subexpression Elimination (HCSE), binary Vertical Subexpression Elimination (VCSE) and hardwiring of the final stages, which reduces the number of adders. This technique focuses on eliminating redundancy by searching and selecting patterns with a look ahead technique in coefficient multiplier [10]. The previous methods only based on (BCSs), for example x3 to x6 are formed from the binary representation of coefficient as follows. [0 1 1] = x3 = x1 + x1 (7) [1 0 1] = x4 = x1 + x1 (8) [1 1 0] = x5= x1 + x1 (9) [1 1 1] = x6 = x1 + x1+ x1 (10) A direct realization of the BHCSs (7) to (10) would require 5 adders. But as x5 can be obtained from x3 by a shift operation and x6 from x5 using an adder, only 3 adders are required to realize the BHCSs. x3= x1+ x1 = x1+ 2-1x1 ) = 2-1x8 (11) x6 = x1 + x1 + x1 = x8 + x1 (12) The main disadvantage of the BHCSs is formed without a look-ahead and therefore many bits are left ungrouped after obtaining the BHCSs. The proposed CSE method can be explained using the example of a 12-tap FIR filter coefficients shown in Table I. Table I Filter Coefficients Representation Of CSD The patterns are obtained based on a look-ahead method, as shown in Table II and III. Table II shows the conventional horizontal subexpression formation for an example filter h0 and h1, whereas Table III shows the same fusing our look-ahead method. In Table II the two bits are ungrouped. Whereas in Table III all the bits are grouped this minimizes the number of adders. The HCSs x3= [1 0 1], x4 = [1 0-1], x5 = [ ],x6 = [ ] and VCS x2 = [1 1]. Table II Sequential Grouping (Horizontal Method) Table III Look Ahead Method Grouping Table IV formed by Table I by substituting HCSs, [1001] =5, [101] =3 and VCS [11] =2. Supersubexpression (SSs) is formed by identical shifts between them or an HCS and nonzero bits. In Table II, the SS 8 and SS 9 are formed. From the HCS [101] and the bit '1'and '-1' with a shift difference of one between them. (as in h3 and h4 ). From Table IV, the output of the example can be expressed as yk = x2 + x6 + x3 + x2[- 1]+ x6[-1]+ x3[- 2]+ x9[ -3]+ x2[-3] + x9[ -4] + x5[ -5]+ x5[ -5] (13) The number of Multiplier Block Adders (MBAs) required to implement the filter using the direct method (method using shifts and adds) in Table I is 18. The proposed Greedy CSE method needs only 11 MBAs (6 for subexpressions and 5 for actual realization), which is a reduction of 39% over the direct method. The reduced percentage is larger when higher order filters are considered. In greedy CSE method coefficient are 150

4 fixed realize low complexitysolution in application of specific filters. In SDR receivers, the channel filter coefficients need to be changed as the filter specification. So, reconfigurability is needed for SDR channel filters. In next section two architectures are proposed that incorporates reconfigurability into the greedy CSE based low complexity filter architecture. 4 FIR FILTER ARCHITECTURE [1 0 1], [1 1 0], and [1 1 1]. These BCSs can be expressed as [0 1 1] = x2 = 2 1x + 2 2x, [1 0 1] = x3 = x + 2 2x, [1 1 0]= x4 = x + 2 1x, and [1 1 1]= x5 = x + 2 1x + 2 2x, where x is the input signal. Note that other BCSs such as [0 0 1], [0 1 0], and [1 0 0] do not require any adder for implementation as they have only one nonzero bit. A straightforward realization of above BCSs would require five adders. However x2 can be obtained from x4 by a right shift operation (without using any extra adders): x2 = 2 1x + 2 2x = 2 1(x + 2 1x) =2 1x4. Also, x5 can be obtained from x4 using an adder: x5 = x + 2 1x + 2 2x = x x. Fig.1.Transposed direct from of an FIR filter A filter is used to modify an input signal in order to facilitate further processing. A digital filter works on a digital input (a sequence of numbers, resulting from sampling and quantizing ann banalog signal) and produces a digital output. In Fig. 1, PE-i represents the processing element corresponding to the i th coefficient. PE performs the coefficient multiplication operation with the help of a shift and add unit which will be explained in the latter part of this section. The architecture of PE is different for proposed CSM and PSM. In the CSM, the filter coefficients are partitioned into fixed groups and hence the PE architecture involves constant shifters. But in the PSM, the PE consists of programmable shifters (PS). The FIR filter architecture can be realized in a serial way in which the same PE is used for generation of all partial products by convolving the coefficients with the input signal (h x[n]) or in a parallel way, where parallel PE architectures are employed. The first option is used when power consumption and area are of prime concern. 4.1 REVIEW OF BCSE METHOD This section reviews the BCSE algorithm, which deals with the elimination of redundant binary common subexpressions (BCSs) that occur within the coefficients. The BCSE technique focuses on eliminating redundant computations in coefficient multipliers by reusing the most common binary bit patterns (BCSs) present in coefficients. An n-bit binary number can form 2n (n + 1) BCSs among themselves. For example, a 3-bit binary representation can form four BCSs, which are [0 1 1], Thus, only three adders are needed to realize the BCSs x2 to x5. The number of adders required for all the possible n-bit binary subexpressions is 2n 1 1. The number of adders needed to implement the coefficient multipliers using the binary representation-based BCSE is considerably less than the CSD-based CSE methods. The proposed FIR filter architecture is based on transposed direct form as shown in Fig. 1. In the transposed direct form, the coefficient multipliers (shown as dotted outline in Fig. 1) share the same input and hence commonly known as multiplier block (MB). The MB reduces the complexity of the FIR filter implementations, by exploiting the redundancy in MCM. Thus, redundant computations (partial product additions in the multiplier) are eliminated using BCSE. The BCSE method in was formulated as a low complexity solution to realize application specific filters where the coefficients are fixed. In the case of channel filters for SDR receivers, the coefficients need to be changed as the filter specification changes with the communication standard. Therefore, reconfigurability is a necessary requirement for SDR channel filters. In the researches introduced, two architectures that incorporate reconfigurability into the BCSE-based low complexity filter architecture. 4.2 FIR FILTER USING CSE ALGORITHM In this section, the architecture of the proposed FIR filter is presented. Our architecture is based on the transposed direct form FIR filter structure as shown in Fig. 1. The dotted portion in Fig. 1 represents the MB. In Fig. 1, PE-i represents the processing element corresponding to the ith coefficient. PE performs the coefficient multiplication operation with the help of a shift and add unit which will be explained in the latter part of this section 151

5 Fig. 2. Architecture of the proposed method.. The architecture of PE is different for proposed CSM and PSM. In the CSM, the filter coefficients are partitioned into fixed groups and hence the PE architecture involves constant shifters. But in the PSM, the PE consists of programmable shifters (PS). The FIR filter architecture can be realized in a serial way in which the same PE is used for generation of all partial products by convolving the coefficients with the input signal (h x[n]) or in a parallel way, where parallel PE architectures are employed. The first option is used when power consumption and area are of prime concern. The basic architecture of the PE (dotted portion) is shown in Fig. 2. The functions of different blocks of the PE are explained below. 1) Shift and Add Unit: It is well known that one of the efficient ways to reduce the complexity of multiplication operation is to realize it using shift and add operations. In contrast to conventional shift and add units used in previously proposed reconfigurable filter architectures, we use the BCSs-based shift and add unit in CSM and PSM architectures. The architecture of shift and add unit is shown in Fig Fig. 3. Architecture of shift and add unit. The shift and add unit is used to realize all the 3-bit BCSs of the input signal ranging from [0 0 0] to [1 1 1]. In Fig. 3, x>>k represents the input x shifted right by k units. All the 3-bit BCSs [0 1 1], [1 0 1], [1 1 0], and [1 1 1] of a 3-bit number are generated using only three adders, whereas a conventional shift and add unit would require five adders. Since the shifts to obtain the BCSs are known beforehand, PS are not required. All these eight BCSs (including [000]) are then fed to the multiplexer unit. In both the architectures (CSM and PSM) proposed in this paper, we use the same shift and add unit. Thus, the use of 3-bit BCSs reduces the number of adders needed to implement the shift and add unit compared to conventional shift and add units. 2) Multiplexer Unit: The multiplexer units are used to select the appropriate output from the shift and add unit. All the multiplexers will share the outputs of the shift and add unit. The inputs to the multiplexers are the 8/4 inputs from the shift and add unit and hence 8:1/4:1 multiplexer units are employed in the architecture. The select signals of the multiplexers are the filter coefficients which are previously stored in a look up table (LUT). The CSM and PSM architectures basically differ in the way filter coefficients are stored in the LUT. In the CSM, the coefficients are directly stored in LUTs without any modification whereas in PSM, the coefficients are stored in a coded format. The number of multiplexers will also be different for PSM and CSM. In CSM, the number of multiplexers will be dependent on the number of groups after the partitioning of the filter coefficient into fixed groups. The number of multiplexers in the PSM is dependent on the number of non-zero operands in the coefficient for the worst case after the application of BCSE algorithm. 3) Final Shifter Unit: The final shifter unit will perform the shifting operation after all the intermediate additions (i.e., intra-coefficient additions) are done. This can be illustrated using the output expression y = 2 4x + 2 6x x x. (1) By coefficient-partitioning [16], we obtain y = 2 4(x + 2 2x) (x + 2 1x). (2) After obtaining the intermediate sums (x + 2 2x) and (x + 2 1x) from the shift and add units with the help of multiplexer unit, the final shifter unit will perform the shift operations 2 4and 2 15 in (2). The PSM and CSM architectures also differ in the nature of final shifters. In the CSM, the final shifts are constants and hence no PS are required. In the PSM, we have used PS. 4) Final Adder Unit: This unit will compute the sum of all the intermediate additions 2 4(x + 2 2x) and 2 15(x +2 1x) as in (2). As the filter specifications of different communication standards are different, the coefficients change with the standards. In conventional reconfigurable filters, the new coefficient set

6 corresponding to the filter specification of the new communication standard is loaded in the LUT. Subsequently, the shift and add unit performs a bitwise addition after appropriate shifts. On the contrary, the CSM and PSM architectures perform a binary common subexpression (BCS)-wise addition (instead bitwise addition). Thus, the same hardware architecture can be used for different filter specifications to achieve the necessary reconfigurability.moreover, the BCS-based shift and add unit reduces addition operations and hence offers hardware complexity reduction. A. ARCHITECTURE OF CSM The CSM architecture is quite straight forward. The basic design in this approach is to store the coefficients directly in the LUT. These coefficients are divided into groups of 3-bits and are used as the select signal for the multiplexers. In this architecture the number of multiplexer units required is [n/3], where n is the wordlength of the filter coefficients. For example, if the filter coefficients are 9-bit, then the number of multiplexers required is 3. This approach can be explained with the help of a 9-bit coefficient h= This h is the worst-case 9-bit coefficient since all the bits are nonzero. Since n=9, the number of multiplexers required is 3. The coefficient h is expressed as y =2-1x+2-2x +2-3x +2-4x +2-5x +2-6x +2-7x +2-8x+2-9x (14) By partitioning equation (8), we obtain h = 2-1 (x +2-1x+2-2x +2-3x +2-4x +2-5x +2-6x +2-7x+2-8x) (15) h = 2-1 (x +2-1x+2-2x +2-3 (x +2-1x +2-2x) +2-6(x +2-1x+2-2x) (16) Now the terms (x +2-1x +2-2x) and (x +2-1x) can be obtained from the shift and add unit. Then by using the 3 multiplexers, precisely using two 8:1 and one 4:1 (for the last two bits of the filter coefficients), the intermediate sums shown inside the brackets of (16) can be obtained. The final shifter unit will perform the shift operations 2 1, 2 3 and 2 6. Since these shifts are always constant, programmable shifters are not required. The final adder unit will add all the intermediate sums to obtain h*x [1]. The CSM architecture for the 16-bit filter coefficient is shown in Fig. 2. The steps involved in CSM are as follows: Step 1: Get the input x. Step 2: Get the coefficients from the LUT and use as the select signal for the multiplexers. Step 3: Perform the final shifting function on the output of the multiplexer. Fig. 2 CSM Architecture for 16bit coefficient Step 4: Perform the addition of intermediate sums using the final adder unit. Step 5: Store the final result, h*x, in the delay unit D. Step 6: Go to step 2 if the coefficients in the LUT are not finished, else go to 1. The three most significant bits of the coefficient will be given as the select signal to the Mux1, the next 3-bits to Mux2 and so on till the least significant bits to the last multiplexer. B. ARCHITECTURE OF PROGRAMMABLE SHIFT METHOD The PSM approach is based on the common subexpression elimination algorithm presented. Unlike the CSM method where constant shifts are used, the PSM employs programmable shifters. The advantage of PSM over CSM is that the former architecture always ensures the minimum number of additions and thus minimum power consumption. This is because PSM has a pre analysis part. The filter coefficients are analyzed using the CSE algorithm [7]. Thus the redundant computations (additions) are eliminated and the resulting coefficients in a coded format are stored in the LUT. The coding can be explained as given below. Consider the coefficient h, h = [ ] (17) By using the CSE, substituting 2= [1 1], 3= [1 0 1], (16) becomes h = [ ] (18) Then (12) will be stored in the LUT as [{1, 3}, {6, 2}, {10, 3}, {15, 2}] which can be represented as {x,y}, 153

7 where x represents the shift value and the y represents the BCS (7) to (10). The LUT contains the data in the form {x,y}. Since x can have 8 possible combinations (from [000] to [111]), it requires 3 bits, and y can have values from [0001] to [1111] for a 16-bit coefficient and hence requires 4 bits. (It must be noted that 2 1 is being applied always after final addition (17) and hence 2 16 will not occur). Thus for storing {x,y} 7 bits are required. The shift and add unit is identical for both PSM and CSM. The number of multiplexer units required can be obtained from the filter coefficients after the application of greedy CSE. The number of multiplexers will be corresponding to the coefficient that has the maximum number of operands. The architecture for the PSM method with programmable shifts (PS) is shown in Fig. 3. The steps involved in PSM are as follows: Step 1: Obtain the BCSs from filter coefficients using CSE algorithm. Step 2: Store the resultant coefficients in the prescribed format as in (18) in the LUT. Step 3: Get the input x. Step 4: Get the coefficients from the LUT and use as the select signal for the multiplexers and the programmable shifters. Step 5: Perform the final shifting function on the output of the multiplexer using PS. Step 6: Perform the addition of intermediate sums using the final adder unit. 5.CSE CLASSIFICATION FOR REDUCING LOGIC OPERATORS AND LOGIC DEPTH The CSE techniques utilize the CSs that occur within the CSD representation of the filter coefficients called HCSs and that occur among the adjacent coefficients called VCSs to eliminate redundant computations. In this section, we provide a brief review of the HCSE and VCSE techniques. A. HORIZONTAL CSE (HCSE) HCSE utilizes CSs that occur within each coefficient to eliminate redundant computations. The coefficient hk = is used as an example to illustrate the HCSE method [3]. In direct implementation (i.e., implementation of the multiplier using shifts and adds without using CSE), the filter tap output is yk = 2 1x1 2 3x x x1+2 9x x x1 2 16x1 (1) where x1 is the input signal. It requires seven LOs (adders and/or subtractors) to implement (1). The bit patterns [1 0 1] and [1 0 1] are repeated twice in hk, which can be expressed as CSs (x2 = x x1 and x3 = x1 2 2x1, respectively). Using CSs, the output (1) can be expressed as yk = 2 1x x x x3. (2) Note that only five LOs [two LOs for CSs x2 and x3, and three LOs for (2)] are needed for HCSE implementation, which is a saving of two LOs when compared to direct implementation. Fig. 3 PSM architecture for 16bit coefficient Step 7: Store the final result, h*x, in the delay unit D Step 8: Go to step 4 if the coefficients in the LUT are not finished, else go to B. VERTICAL CSE (VCSE) The VCSE utilizes CSs that exist across adjacent coefficients to eliminate redundant computations. The coefficient multipliers are realized by employing vertical CSs of [1 1] and [1 1]. The VCS of [1 1] can be expressed as x4 = x1 + x1[ 1], and the VCS of [1 1] can be expressed as x5 = x1 x1[ 1], where x1[ 1] represents the input x1 delayed by one unit. (ex)by using VCSs, the output y0 corresponding to coefficients h0 and h1 can be expressed as y0 = 2 1x x5 2 6x x1. (3) The output y0 requires three LOs for (3) and two LOs for x4 and x5, with a total of five LOs, whereas direct implementation would require six LOs. In general, VCSE offers reduction of LOs due to the occurrence of many vertical CSs in the coefficient set. However, CSD-based VCSE fails to exploit the symmetry of coefficients in implementing the filter. For the symmetric part of (3), by using the same VCSs, the expression for the output of coefficients h2 and h3 is given by y2 = 2 1x4[ 2] 2 3x5[ 2] 2 6x4[ 2] +

8 2 8x1[ 3].(4) There are two issues (constraints) related to symmetry exploitation in VCSE using CSD representation of filter coefficients, first, due to the differences in signs of the second terms in (3) and (4), and second, delay differences for the fourth terms in (3) and (4). Hence, (4) cannot be directly obtained from its symmetric part (3) by a simple delay operation; instead, extra LOs are needed to compensate the sign and delay differences. This requirement of extra LOs poses constraints in reducing the number of LOs in CSD-based VCSE method [8]. In binarybased approach, only the second problem of delay difference will occur. There are no sign problems as there are no negative bits in binary. This makes binary-based CSE method more efficient for VCSE compared to the CSDbased approach. Filters used in wireless communication receivers are mainly linear phase (symmetric coefficients) to avoid phase distortions. Hence, binarybased VCSE is more feasible and will result in better reduction of adders compared to CSD-VCSE for these filters.(in binary based csd no -ve signs are there in coeficients.it's only consist of 0's and 1's).This is the main difference between CSE and BINARY based CSE in horizontal,vertical classification B. BINARY SS ELIMINATION (BSSE) If two or more common BCSs occur among different coefficientsand if these BCSs are having identical shifts between them, then they are known as CBCS. BSSE involves the grouping of CBCS terms shared among coefficients. Each coefficient is compared with the remaining coefficients for CBCSs. If more than one common BHCS occur between a coefficient pair, the CBCSs can be grouped together to eliminate redundant computations. The steps for BSSE are as follows. the next level. This is done as follows. Set i0 = 1 initially. a) Compute the largest CI Cmax i0,jm of the i0 th row from Ci,j i=i0,j=i0+1:j=jl, where jm corresponds to the column in which the largest CI lies. b) Check all the CIs in the jm column to find whether any other CI greater than Cmax i0,jm exists.if no such CI exists, choose Cmax i0,jm as the largest CI of the i0th row, and group the corresponding pair [h(i0),h(jm)]. Otherwise, choose the second largest CI of the i0th row as the largest CI, and obtain the CBCS from respective coefficient pair. Step 3) Let the largest CI obtained in previous step be Ci0jh.Replace all the elements of corresponding rows and columns with zero to exclude the coefficient pair chosen earlier from further search. Step 4) If i0 L, set i0 = i0 + 1, and go to step 2). Thus,determine all the CBCSs, and eliminate them from the filter coefficient set as all these CBCSs need to be implemented only once.c. EXAMPLES OF 6 TAP FILTER FOR HCSE AND VCSE BD BHSE deals with the elimination of redundant binary horizontal CSs (BHCSs) that occur within a coefficient. Step 1) Let Cij represent the CI of the coefficient pair h(i) and h(j), and L is the number of filter taps. Definition of CI: The CI of a coefficient pair is defined as the number of CBCSs obtained after BHSE algorithm. Thus, the CI of a coefficient pair is given by the number of identical shifts between the BHCSs present in the coefficient pair. Determine the CIs of all the coefficient pairs and form the correlation matrix C[hij ] Step 2) The correlation matrix C[hij ] is scanned rowwise, and the coefficient pair corresponding to the largest CI is grouped together to extract the CBCS of each row. It may be noted that, while selecting the best coefficient pairs, matching at one level must take into account how a particular match influences matching at A.filter implementation using HCSEmethod. 155

9 B.filter implementation using VCSEmethod. 6.CONCLUSION AND FUTURE WORK The two new approaches are CSM and PSM, for implementing reconfigurable higher order filters with low complexity. The proposed CSM and PSM methods make use of architectures with fixed number of multiplexers and the reduction in complexity is achieved by applying the greedy CSE algorithm. The CSM architecture results in high speed filters and PSM architecture results in low area and thus low power filter implementations. The PSM also provides the flexibility of changing the filter coefficient wordlengths dynamically. The reconfigurable architectures can be easily modified to employ any common subexpression elimination (CSE) method, which results in architectures that offers good area and power reductions and speed improvement reconfigurable FIR filter implementations.binary besed fir filter gives better reduction than csd based CSE method.then in classes of CSE,the VCSE gives better adder reduction than HCSE.These techniques are used in fir filter for reconfigurablity and low complexity.so I am going to simulate and compare the results of above techniques(csd and binary based cse,greedy,vcse and HCSE) for find the best one adder reduction method. REFERENCES [1] T. Hentschel and G. Fettweis, Software radio receivers, in CDMA Techniques for Third Generation Mobile Systems. Dordrecht, The Netherlands: Kluwer Academic, 1999, pp [2] J. Mitola, Object-oriented approaches to wireless systems engineering, in Software Radio Architecture. New York: Wiley, [3] Y. Linn, Efficient loop filter design in FPGAs for phase lock loops in high-data rate wireless receivers: Theory and case study, in Proc. 6th Annu. Wireless Telecommun. Symp., Pomona, CA, Apr. 2007, pp [4] R. I. Hartley, Subexpression sharing in filters using canonic signed digit multipliers, IEEE Trans. Circuits Syst. II, vol. 43, no. 10, pp , Oct [5] R. Pasko, P. Schaumont, V. Derudder, S. Vernalde, and D. Durackova, A new algorithm for elimination of common subexpressions, IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 18, no. 1, pp , Jan [6] M. M. Peiro, E. I. Boemo, and L. Wanhammar, Design of high-speed multiplierless filters using a nonrecursive signed common subexpression algorithm, IEEE Trans. Circuits Syst. II, vol. 49, no. 3, pp , Mar [7] A. P. Vinod and E. M.-K. Lai, On the implementation of efficient channel filters for wideband receivers by optimizing common subexpression elimination methods, IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 24, no. 2, pp , Feb [8] R. Mahesh and A. P. Vinod, A new common subexpression elimination algorithm for realizing low complexity higher order digital filters, IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 27, no. 2, pp , Feb [9] A. P. Vinod and E. Lai, Low power and high-speed implementation of FIR filters for software defined radio receivers, IEEE Trans. Wireless Commun., vol. 5, no. 7, pp , Jul [10] K. Muhammad and K. Roy, Reduced computational redundancy implementation of DSP algorithms using computation sharing vector scaling, IEEE Trans. Very Large Scale Integr. Syst., vol. 10, no. 3, pp , Jun [11] K. H. Chen and T. D. Chiueh, A low-power digitbased reconfigurable FIR filter, IEEE Trans. Circuits Syst. II, vol. 53, no. 8, pp , Aug [12] T. Zhangwen, J. Zhang, and H. Min, A highspeed, programmable, CSD coefficient FIR filter, IEEE Trans. Consumer Electron., vol. 48, no. 4, pp , Nov [13] X. Chenghuan, C. He, Z. Shunan, and W. Hua, Design and implementation of a high-speed programmable polyphase FIR filter, in Proc. 5th Int. Conf. Applicat.-Specific Integr. Circuit, vol. 2. Oct. 2003, pp

10 [14] S. S. Demirsoy, I. Kale, and A. G. Dempster, Efficient implementation of digital filters using novel reconfigurable multiplier blocks, in Proc. 38th Asilomar Conf. Signals Syst. Comput., vol. 1. Nov. 2004, pp [15] P. Tummeltshammer, J. C. Hoe, and M. Puschel, Multiplexed multiple constant multiplication, IEEE Trans. Comput.-Aided Design Integr. Circuits, vol. 26, no. 9, pp , Sep [16] J. Park, W. Jeong, H. Mahmoodi-Meimand, Y. Wang, H. Choo, and K.Roy, Computation sharing programmable FIR filter for low-power and high-performance applications, IEEE J. Solid State Circuits, vol. 39, no. 2, pp , Feb [77] A. P. Vinod and E. Lai, Low power and highspeed implementation of FIR filters for software defined radio receivers, IEEE Trans. Wireless Commun., vol. 5, no. 7, pp , Jul