Precision Unity Gain DIFFERENTIAL AMPLIFIER

Transcription

1 INA0 Precision Unity Gain DIFFERENTIAL AMPLIFIER FEATURES CMR 8dB min OVER TEMPERATURE GAIN ERROR: 0.0% max NONLINEARITY: 0.00% max NO EXTERNAL ADJUSTMENTS REQUIRED EASY TO USE COMPLETE SOLUTION HIGHLY VERSATILE LOW COST PLASTIC DIP, TO-99 HERMETIC METAL, AND SO-8 SOIC PACKAGES APPLICATIONS DIFFERENTIAL AMPLIFIER INSTRUMENTATION AMPLIFIER BUILDING BLOCK UNITY-GAIN INVERTING AMPLIFIER GAIN-OF-/ AMPLIFIER NONINVERTING GAIN-OF- AMPLIFIER AVERAGE VALUE AMPLIFIER ABSOLUTE VALUE AMPLIFIER SUMMING AMPLIFIER SYNCHRONOUS DEMODULATOR CURRENT RECEIVER WITH COMPLIANCE TO RAILS ma TO 0mA TRANSMITTER VOLTAGE-CONTROLLED CURRENT SOURCE ALL-PASS FILTERS DESCRIPTION The INA0 is a monolithic Gain = differential amplifier consisting of a precision op amp and on-chip metal film resistors. The resistors are laser trimmed for accurate gain and high common-mode rejection. Excellent TCR tracking of the resistors maintains gain accuracy and common-mode rejection over temperature. The differential amplifier is the foundation of many commonly used circuits. The INA0 provides this precision circuit function without using an expensive precision resistor network. The INA0 is available in 8-pin plastic DIP, SO-8 surface-mount and TO-99 metal packages. In +In kω kω kω kω 7 Sense V+ Output V Ref International Airport Industrial Park Mailing Address: PO Box 00, Tucson, AZ 87 Street Address: 70 S. Tucson Blvd., Tucson, AZ 870 Tel: (0) 7- Twx: Internet: FAXLine: (800) 8- (US/Canada Only) Cable: BBRCORP Telex: 0-9 FAX: (0) Immediate Product Info: (800) 8-98 Burr-Brown Corporation PDS-7G Printed in U.S.A. August, 99 SBOS

2 SPECIFICATIONS ELECTRICAL At + C, V CC = ±V, unless otherwise noted. INA0AM INA0BM INA0KP, KU PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS GAIN Initial () V/V Error % vs Temperature ppm/ C Nonlinearity () % OUTPUT Rated Voltage I O = +0mA, ma 0 V Rated Current V O = 0V +0, ma Impedance 0.0 Ω Current Limit To Common +0/ 0 ma Capacitive Load Stable Operation 000 pf INPUT Impedance () Differential 0 kω Common-Mode 0 kω Voltage Range () Differential ±0 V Common-Mode ±0 V Common-Mode Rejection () T A = T MIN to T MAX db OFFSET VOLTAGE RTO (), (7) Initial µv vs Temperature 0 0 µv/ C vs Supply ±V S = V to 8V µv/v vs Time 0 µv/mo OUTPUT NOISE VOLTAGE RTO (), (8) f B = 0.0Hz to 0Hz. µvp-p f O = 0kHz 0 nv/ Hz DYNAMIC RESPONSE Small Signal Bandwidth db MHz Full Power Bandwidth V O = 0Vp-p 0 0 khz Slew Rate V/µs Settling Time: 0.% V O = 0V Step µs 0.0% V O = 0V Step µs 0.0% V CM = 0V Step, V DIFF = 0V. µs POWER SUPPLY Rated ± V Voltage Range Derated Performance ± ±8 V Quiescent Current V O = 0V ±. ± ma TEMPERATURE RANGE Specification 0 +8 C Operation C Storage C Specification same as for INA0AM. NOTES: () Connected as difference amplifier (see Figure ). () Nonlinearity is the maximum peak deviation from the best-fit straight line as a percent of full-scale peakto-peak output. () kω resistors are ratio matched but have ±0% absolute value. () Maximum input voltage without protection is 0V more than either ±V supply (±V). Limit I IN to ma. () With zero source impedance (see Maintaining CMR section). () Referred to output in unity-gain difference configuration. Note that this circuit has a gain of for the operational amplifier s offset voltage and noise voltage. (7) Includes effects of amplifier s input bias and offset currents. (8) Includes effects of amplifier s input current noise and thermal noise contribution of resistor network. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. INA0

3 PIN CONFIGURATIONS Top View TO-99 Top View DIP/SOIC Tab 8 No Internal Connection Ref 7 V+ Ref () 8 No Internal Connection In 7 V+ In Output +In Output +In Sense INA0AM INA0BM V Case internally connected to V. Make no connection. V Sense NOTE: () Performance grade identifier box for small outline surface mount. Blank indicates K grade. Part is marked INA0U. ABSOLUTE MAXIMUM RATINGS Supply... ±8V Input Voltage Range... ±V S Operating Temperature Range: M... C to + C P, U... 0 C to +8 C Storage Temperature Range: M... C to +0 C P, U... 0 C to + C Lead Temperature (soldering, 0s) M, P C Wave Soldering (s, max) U C Output Short Circuit to Common... Continuous PACKAGE/ORDERING INFORMATION PACKAGE DRAWING TEMPERATURE PRODUCT PACKAGE NUMBER () RANGE ELECTROSTATIC DISCHARGE SENSITIVITY This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. INA0AM TO-99 Metal 00 0 C to +8 C INA0BM TO-99 Metal 00 0 C to +8 C INA0KP 8-Pin Plastic DIP 00 0 C to +8 C INA0KU 8-Pin SOIC 8 0 C to +8 C NOTE: () For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. INA0

4 TYPICAL PERFORMANCE CURVES At T A = C, V S = ±V, unless otherwise noted. STEP RESPONSE SMALL SIGNAL RESPONSE (No Load) Output Voltage (V) 0 to +0 Output Voltage (mv) Time (µs) Time (µs) SMALL SIGNAL RESPONSE (R LOAD = Ω, C LOAD = 000pF) 7. MAXIMUM V OUT vs I OUT (Negative Swing) V S = ±8V Output Voltage (mv) V OUT (V) V S = ±V V S = ±V. V S = ±V 0 0 Time (µs) I OUT (ma) V OUT (V) MAXIMUM V OUT vs I OUT (Positive Swing) V S = ±8V V S = ±V V S = ±V CMR (db) CMR vs FREQUENCY BM AM, KP, U. V S = ±V I OUT (ma) k 0k 00k Frequency (Hz) INA0

5 TYPICAL PERFORMANCE CURVES (CONT) At T A = C, V S = ±V, unless otherwise noted. 0 POWER SUPPLY REJECTION vs FREQUENCY COMMON-MODE INPUT RANGE vs SUPPLY (Difference Amplifier Connected, V OUT = 0) 0 0 PSRR (db) V Input Range (V) 8 Negative CMV Positive CMV 0 V k 0k 00k Frequency (Hz) 0 ± ± ±9 ± ± ±8 ± Supply Voltage (V) APPLICATION INFORMATION Figure shows the basic connections required for operation of the INA0. Power supply bypass capacitors should be connected close to the device pins. The differential input signal is connected to pins and as shown. The source impedances connected to the inputs must be nearly equal to assure good common-mode rejection. A Ω mismatch in source impedance will degrade the common-mode rejection of a typical device to approximately 80dB. If the source has a known mismatch in source impedance, an additional resistor in series with one input can be used to preserve good common-mode rejection. The output is referred to the output reference terminal (pin ) which is normally grounded. A voltage applied to the Ref terminal will be summed with the output signal. This can be used to null offset voltage as shown in Figure. The source impedance of a signal applied to the Ref terminal should be less than 0Ω to maintain good common-mode rejection. Do not interchange pins and or pins and, even though nominal resistor values are equal. These resistors are laser trimmed for precise resistor ratios to achieve accurate gain and highest CMR. Interchanging these pins would not provide specified performance. V µf INA0 R R V kω kω R V kω R kω V+ µf 7 V OUT = V V FIGURE. Basic Power Supply and Signal Connections. INA0

6 INA0 V V R R In A R INA0 V O R V 0Ω R R 0utput R +V V A V O = V V Offset Adjustment Range = ±00µV FIGURE. Offset Adjustment. 0Ω 99kΩ V 00kΩ +In V O = ( + R /R ) (V V ) For low source impedance applications, an input stage using OPA7 op amps will give the best low noise, offset, and temperature drift performance. At source impedances above about 0kΩ, the bias current noise of the OPA7 reacting with the input impedance begins to dominate the noise performance. For these applications, using the OPA or dual OPA FET input op amp will provide lower noise performance. For lower cost use the OPA plastic. To construct an electrometer use the OPA8. INA0BM R R GAIN CMRR MAX NOISE AT khz A, A (Ω) (Ω) (V/V) (db) I B (nv/ HZ) In V R R kω kω OPA7A 0..k nA OPAB 0 0k 00 0 pa 0 OPA8LM 0 0k fA 8 FIGURE. Precision Instrumentation Amplifier. +In V R kω R kω INA0 = V V Gain Error = 0.00% CMR = 00dB Nonlinearity = 0.000% FIGURE. Precision Difference Amplifier. V 00Ω % 00Ω % 0 to V I IN 0 to 0mA FIGURE. Current Receiver with Compliance to Rails. INA0

7 INA0 INA0 V V FIGURE. Precision Unity-Gain Inverting Amplifier. +V = V Gain Error = 0.0% maximum Nonlinearity = 0.00% maximum Gain Drift = ppm/ C +0V Out FIGURE 9. Precision Unity-Gain Buffer. V+ = V Gain Error = 0.00% maximum INA0 7 V+ REF0 INA0 0V Out (V+)/ Common Common FIGURE 0. Pseudoground Generator. FIGURE 7. ±0V Precision Voltage Reference. V+ INA0 INA0 REF0 +V Out V V V Out = (V + V )/, ±0.0% maximum FIGURE. Precision Average Value Amplifier. FIGURE 8. ±V Precision Voltage Reference. 7 INA0

8 INA0 INA0 0 to +0V Output ±ppm/ C () Output V 0V to +0V Input = V Gain Error = 0.0% maximum Gain Drift = ppm/ C FIGURE. Precision (G = ) Amplifier. Device VFC0 VFC00 DAC80 DAC70 XTR0 Output 0-0kHz 0-F CLOCK / 0-FS ( bits) 0-FS ( bits) -0mA INA0 REF0 0V NOTE: () Unipolar Input Device. FIGURE. Precision Bipolar Offsetting. V V R R INA0 = V + V, ±0.0% maximum FIGURE. Precision Summing Amplifier. V INA0 V ( )( ) = + R V + V R For G=0, See INA0. FIGURE. Precision Summing Amplifier with Gain. V ±0V = / V = V /, ±0.0% FIGURE. Precision Gain = / Amplifier. INA0 8

9 Noise (0Hz hum) Offset Adjust 7 8 INA0AG Transducer or Analog Signal A 0kΩ 0kΩ 0kΩ R G 0 0kΩ 0kΩ A Output A 0kΩ Noise (0Hz hum) Shield 00kΩ 9 Common +V CC V CC INA0 FIGURE 7. Instrumentation Amplifier Guard Drive Generator. INA0 INA0 V V V = V + V V V V FIGURE 8. Precision Summing Instrumentation Amplifier. 9 INA0

10 V INA0 INA0 R V R V I O = (V V ) (/k + /R) For R 00 Ω, Figure will provide superior performance. Load I O FIGURE 9. Precision Voltage-to-Current Converter with Differential Inputs. V INA0 V INA0 R V = (V V ) FIGURE. Differential Output Difference Amplifier. I O = (V V )/R I O Load V INA0 FIGURE 0. Differential Input Voltage-to-Current Converter for Low I OUT. R 00 Ω V INA0 V I O = (V V )/R R Gate can be +V CC V R R < 00Ω Load I O R V Gate can be +V S V FIGURE. Isolating Current Source with Buffering Amplifier for Greater Accuracy. I O = (V V ) (/k + /R) Load I O FIGURE. Isolating Current Source. INA0 0

11 Window Center Window Span Window Span 0 to +V INA0 Lower Limit 0 V IN Window 9 Comparator 7 Upper Limit HI GO LO Window Center ±0V 8 FIGURE. Window Comparator with Window Span and Window Center Inputs. INA0 Window Center + Window Span In V () INA0 V+ R R R R kω R V +In () Load I O I O = (E E ) ( +R /R ) (/k + /R) NOTE: () See Figure for op amp recommendation. FIGURE. Precision Voltage-Controlled Current Source with Buffered Differential Inputs and Gain. INA0 V DG88 V O Logic In Logic In 0 V O V +V FIGURE. Digitally Controlled Gain of ± Amplifier. INA0

12 INA0 V R R A R 9.Ω R A = 00 (V V ) R 9.Ω R R A V Conventional Instrumentation Amplifier (e.g., INA0 or INA0) A = 00 INA0 A = FIGURE 7. Boosting Instrumentation Amplifier Common-Mode Range From ± to ±7.V with 0V Full-Scale Output. INA0 R R D 0pF R = V V Input OPA D R kω R FIGURE 8. Precision Absolute Value Buffer. 0 to 0V In.kΩ 0kΩ kω +V OPA7 INA0 0.Ω REF0 0V 0. Ω to 0mA Out R LOAD FIGURE 9. Precision -0mA Current Transmitter. INA0

13 PACKAGE OPTION ADDENDUM -Aug-08 PACKAGING INFORMATION Orderable Device Status () Package Type Package Drawing Pins Package Qty Eco Plan INA0AM NRND TO-99 LMC 8 Green (RoHS & no Sb/Br) INA0BM NRND TO-99 LMC 8 Green (RoHS & no Sb/Br) INA0KP ACTIVE PDIP P 8 0 Green (RoHS & no Sb/Br) INA0KPG ACTIVE PDIP P 8 0 Green (RoHS & no Sb/Br) INA0KU ACTIVE SOIC D 8 7 Green (RoHS & no Sb/Br) INA0KU/K ACTIVE SOIC D 8 00 Green (RoHS & no Sb/Br) INA0KU/KE ACTIVE SOIC D 8 00 Green (RoHS & no Sb/Br) INA0KUE ACTIVE SOIC D 8 7 Green (RoHS & no Sb/Br) () Lead/Ball Finish () MSL Peak Temp () Op Temp ( C) AU N / A for Pkg Type INA0AM AU N / A for Pkg Type INA0BM CU NIPDAU Call TI N / A for Pkg Type INA0KP Call TI N / A for Pkg Type INA0KP CU NIPDAU-DCC Level--0C-8 HR -0 to 8 INA 0U CU NIPDAU-DCC Level--0C-8 HR -0 to 8 INA 0U CU NIPDAU-DCC Level--0C-8 HR -0 to 8 INA 0U CU NIPDAU-DCC Level--0C-8 HR -0 to 8 INA 0U Device Marking (/) Samples () The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. () RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 0 RoHS substances, including the requirement that RoHS substance do not exceed 0.% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=000ppm threshold. Antimony trioxide based flame retardants must also meet the <=000ppm threshold requirement. () MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. () There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. Addendum-Page

14 PACKAGE OPTION ADDENDUM -Aug-08 () Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. () Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page

15 PACKAGE MATERIALS INFORMATION -Jul-0 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W (mm) A0 (mm) B0 (mm) K0 (mm) P (mm) W (mm) Pin Quadrant INA0KU/K SOIC D Q Pack Materials-Page

16 PACKAGE MATERIALS INFORMATION -Jul-0 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) INA0KU/K SOIC D Pack Materials-Page

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18 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Texas Instruments: INA0AM INA0BM INA0KP INA0KU INA0KU/K INA0KU/KE INA0KUE INA0KPG