DR. R. V. KRISHNAIAH 2 Asst. Professor, SIETK, Puttur, AP-INDIA. ISSN Volume.05, September-2013, Pages:

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1 ISSN Volume.05, September-2013, Pages: AC DC Converter for Semi-Bridgeless using Phase-Shifted Gating Technique M.K JAYAVELU 1 M.Tech-PE, SIETK, Puttur, AP-INDIA, velu03.mtech@gmail.com DR. R. V. KRISHNAIAH 2 Asst. Professor, SIETK, Puttur, AP-INDIA. Abstract: In this paper, a phase-shifted semi-bridgeless boost power-factor-corrected (PFC) converter is proposed to simplify the current-sensing technique for the semibridgeless PFC converter. The converter features high efficiency at light loads and low ac input lines, which is critical to minimize the charger size, charging time, and amount and cost of electricity drawn from the utility. The converter is applicable for automotive levels I and II but is ideally suited for level-i residential charging applications. A detailed converter description and steady-state operation analysis of this converter is presented. Experimental results of a proto-type boost converter, converting the universal ac input voltage to 400 V dc at 3.4 kw, are given, and the results are compared with an interleaved boost converter to verify the proof of concept and the reported analytical work Keywords: AC DC power converters, boost converter, bridgeless power factor correction (PFC), current sensing, plug-in hybrid electric vehicle (PHEV) charger I. INTRODUCTION PLUG-IN hybrid electric vehicle (PHEV) is a hybrid vehicle with a storage system that can be recharged by connecting a plug to an external electric power source. The charging ac outlet inevitably needs an onboard ac dc charger with power factor correction (PFC) [1]. An onboard 3.3-kW charger could charge a depleted battery pack in PHEVs to 95% charge in about 4 h from a 240-V supply for a 10-kWh battery pack [2]. A variety of circuit topologies and control methods has been developed for PHEV battery chargers. The two-stage approach with cascaded PFC ac dc and dc dc converters is the common architecture of choice for PHEV battery chargers, where the power rating is relatively high, and lithium-ion batteries are Fig.1 Interleaved PFC boost topology. used as the main energy storage system [3]. The singlestage approach is generally only suitable for lead acid batteries due to a large low-frequency ripple in the output current. In the two-stage architecture, the PFC stage rectifies the input ac voltage and transfers it into a regulated intermediate dc-link bus. At the same time, PFC is achieved [4]. A boost-derived PFC topology operated in continuous conduction mode is used in this paper as the main candidate for the front-end ac dc PFC converter for PHEV battery charging. The front-end candidate topologies in the boost-derived class include the following: the interleaved boost converter, the bridgeless boost converter, the dual-boost converter, the semibridgeless boost converter, and the proposed phase-shifted semi-bridgeless (PSSB) boost converter. A. Interleaved PFC The interleaved boost converter is shown in Fig. 1. This topology uses two boost converters in parallel operating 180 out of phase [5] [7]. The input current is the sum of the two inductor currents. Because the inductor ripple currents are out of phase, they tend to cancel each other and reduce the input ripple current caused by the boost switching action. The interleaved boost converter has the advantage of parallel semiconductors. Furthermore, by switching 180 out of phase, it doubles the effective switching frequency and introduces a smaller input current ripple; thus, the input electromagnetic interference (EMI) filter can be smaller than a single PFC boost topology [8] [10]. Finally, this converter features a reduced output capacitor high-frequency ripple. However, as with the 2013 IISRC. All rights reserved.

2 M.K JAYAVELU, DR. R. V. KRISHNAIAH single PFC boost, the most significant drawback of this topology is the very high localized loss and the resultant heat management issue for the input diode bridge rectifiers. Fig.2 Bridgeless PFC boost topology. a result, the common-mode (CM) noise generated by bridgeless PFC is much higher than the conventional boost PFC topology [24]. Another disadvantage of this topology is the floating input line with respect to the PFC stage ground, which makes it impossible to sense the input voltage without a low-frequency transformer or an optical coupler. C. Dual-Boost PFC The dual-boost converter, as shown in Fig. 4, is an alternative adaptation of the bridgeless boost topology [25]. In this topology, the MOSFET gates are decoupled, enabling one of the switches to remain on and operate as a synchronous MOSFET for a half-line cycle. Fig. 5 shows the gating scheme for a dual- Fig.3 Gating scheme for the bridgeless PFC boost topology illustrating the identical gating signals for both MOSFETs. Fig.5 Gating scheme for the dual-boost PFC topology illustrating half-line cycle synchronous rectification. Fig.4 Dual-boost PFC topology. B. Bridgeless PFC The bridgeless boost topology, as shown in Fig. 2, is the second topology considered for this application. The gates of the power train switches are tied together; thus, the gating signals are identical, as shown in Fig. 3. It avoids the need for the rectifier input bridge but maintains the classic boost topology [11] [21]. It is an attractive solution for applications > 1 kw, where power density and efficiency are important. The bridgeless boost converter, which is also known as the dual- boost PFC converter, solves the problem of heat management in the input rectifier diode bridge, but it introduces increased EMI [22] [24]. This is because the amplitude of the noise source applied to the stray capacitor from high-voltage dc bus and power ground is a lot higher in bridgeless PFC; as Fig.6 Semi-bridgeless PFC boost topology. boost PFC topology. The dual-boost topology reduces the gate loss, and at light loads, the conduction loss can be reduced up until the voltage drop across the MOSFET channel RDS (ON) becomes equal to the voltage drop across the MOSFET body diode, at which point, any additional current conducts through the body diode. The light-load efficiency improvement comes at the expense of the cost of an additional driver and increased controller complexity. D. Semi-Bridgeless PFC The semi-bridgeless configuration, as shown in Fig. 6, includes the conventional bridgeless topology with two additional slow diodes, namely, Da and Db that connect the input to the PFC ground. The slow diodes were added to address EMI- related issues [22], [23]. The current does not always return through these diodes; therefore, their

3 AC DC Converter for Semi-Bridgeless using Phase-Shifted Gating Technique associated conduction losses are low. This occurs since the inductors exhibit low impedance at the line frequency; thus, a large portion of the current flows through the MOSFET intrinsic body diodes. The semi-bridgeless configuration also resolves the floating input line problem with respect to the PFC stage ground. The topology change enables input voltage sensing using a string of simple voltage dividers. E. Bridgeless-Derived Topology Current Sensing Three unique current-sensing circuits (Methods 1 3) for the bridgeless PFC topology are shown in Fig.7 to sense the current in the MOSFET and diode paths separately, since the current path does not share the same ground during each half-line cycle [13], [26]. These methods are also applicable to the dual-boost and semibridgeless topologies discussed in Section I. Method 1 is the passive current-sensing method reported in [13], which requires three current-sensing transformers one in series with each switch and a third in the positive dc rail to sense the combined current of the two diodes, and an additional signal transistor with its associated complex control circuitry. As an alternative solution, Method 2 uses a simple, but expensive, Hall effect sensor to directly sense the input current. This solution is not desired for highly costsensitive applications, including PHEV chargers. Method 3 uses a differential-mode amplifier in series with the input. This method is relatively inexpensive. However, due to the high switching frequency and the high output voltage, a high CM voltage leads to problematic noise in the current signal. In addition, since the current-sensing voltage is low to minimize the power loss, the power factor can be degraded by the sensing noise. In the following section, a new PSSB boost PFC converter is proposed to simplify the current-sensing technique in the bridgeless ac dc PFC converters while maintaining all the advantages of the existing solutions. II. PROPOSED PHASE-SHIFTED SEMI- BRIDGELESS CONVERTER The PSSB topology shown in Fig. 8 is proposed as a solution to simplify current sensing in bridgeless PFC boost applications using the current synthesizer sensing method [27]. The inductor current synthesizer technique is used to predict the boost inductor current by sensing the MOSFET current [28]. Fig.7 Three unique current-sensing circuits implemented with the bridgeless PFC boost topology. Fig.8 Proposed PSSB PFC boost topology with a simple current-sensing circuit. These current-sensing transformers increase the cost and size of the control circuitry. Combining three current transformer outputs to reconstruct an input current-sensing signal for a full switching cycle requires additional circuitry, further complicating the control circuit design. Fig.9 Gating scheme for the PSSB PFC topology. The proposed topology power train incorporates the decoupled MOSFET gates, similar to that of the dual boost, and uses two slow diodes (Da and Db), similar to that of the semi-bridgeless boost, to link the ground of the PFC to the input line. The gating signals for the MOSFETs are 180 out of phase, as shown in Fig. 9. The phase-shifted gating enables the usage of the advanced current synthesizing method, which cannot be used in either the bridgeless topology or the dual-boost topology because all controllers available for these topologies require full input current shape sensing. The proposed topology exploits the advantages of the bridge-less and semi-bridgeless boost PFC topologies. In particular, it features reduced EMI, high efficiency at light loads, and low lines, which is critical to minimize the charger size, cost, charging time, and amount and cost of electricity drawn from the utility. The proposed converter steadystate operation is given in the following section.

4 M.K JAYAVELU, DR. R. V. KRISHNAIAH III. CONVERTER STEADY-STATE OPERATION To analyze the circuit operation, the input line cycle is separated into positive and negative half-cycles, as explained in Section III-A and B. In addition, the detailed circuit operation depends on the duty cycle. Positive halfcycle operation is provided for D > 0.5 in Section III-C and D < 0.5 in Section III-D. A. Positive Half-Cycle Operation Referring to Fig. 8, during the positive half-cycle, when the ac input voltage is positive, Q1 turns on and current flows through L1 and Q1 and continues through Q2 and then L2, returning to the line while storing energy in L1 and L2. When Q1 turns off, the energy stored in L1 and L2 is released as current flows through D1, through the load, and returns through the body diode of Q2/partially through Db back to the input. B. Negative Half-Cycle Operation Referring to Fig. 8, during the negative half-cycle, when the ac input voltage is negative, Q2 turns on and current flows through L2 and Q2 and continues through Q1 and then L1, returning to the line while storing energy in L2 and L1. When Q2 turns off, the energy stored in L2 and L1 is released as current flows through D2, through the load, and returns split between the body diode of Q1 and Da back to the input. Fig.12 Interval 4: Q1 off and Q2 on. C. Detailed Positive Half-Cycle Operation and Analysis for D > 0.5 The detailed operation of the proposed converter depends on the duty cycle. During any half-cycle, the converter duty cycle is either greater than 0.5 (when the input voltage is smaller than half of the output voltage) or smaller than 0.5 (when the input voltage is greater than half of the output voltage). The three unique operating interval circuits of the proposed converter are provided in Figs for duty cycles larger than 0.5 during the positive half-cycle input. Waveforms of the proposed converter during positive half-cycle operation with D > 0.5 are shown in Fig. 13. To simplify the analysis, it is assumed that the current splits between the bridge diode, the body diode, and the MOSFET channel equally. The intervals of operation are explained here. Interval 1 [t0 t1]: At t0, Q1/ Q2 are on, as shown in Fig.10.During this interval, the current in series inductances L1 and L2 increases linearly and stores the energy in these inductors. The energy stored in Co provides energy to the load. The return current is split among Db, Dq2, and Q2. Interval 2 [t1 t2]: At t1, Q1 is on, and Q2 is off, as shown in Fig. 11. During this interval, the current in series inductances L1 and L2 continues to increase linearly and store the energy in these inductors. The energy stored in Fig.10 Intervals 1and 3: Q1 and Q2 on. Fig.11 Interval 2: Q1 on, body diode of Q2 conducting.

5 AC DC Converter for Semi-Bridgeless using Phase-Shifted Gating Technique and Db. Fig.14 Intervals 1and 3: Q1 and Q2 off, body diode of Q2 conducting. Fig.15 Interval 2: Q1 on, body diode of Q2 conducting. Fig.13 PSSB boost converter steady-state waveforms for D > 0.5. Co provides the load energy. The return current is split only between Db and Dq2. Interval 3 [t2 t3]: At t2, Q1/Q2 is on again, and interval 1 is repeated, as shown in Fig. 10. During this interval, the current in series inductances L1 and L2 increases linearly and stores the energy in these inductors. The return current is again split among Db, Dq2, and Q2. Interval 4 [t3 t4]: At t3, Q1 is off, and Q2 is on, as shown in Fig. 12. During this interval, the energy stored in L1 and L2 is released to the output through L1, D1, partially Q2, Dq2, L2, and Db. D. Detailed Positive Half-Cycle Operation and Analysis for D < 0.5 The three unique operating interval circuits of the proposed converter are given in Figs for duty cycles less than 0.5 during the positive half-cycle. The waveforms of the proposed converter during these conditions are shown in Fig. 17. The intervals of operation are explained here. Interval 1 [t0 t1]: At t0, Q1/ Q2 are off, as shown in Fig. 14. During this interval, the energy stored in L1 and L2 is released to the output through L1, D1, partially Dq2, L2 Fig.16 Interval 4: Q1 off and Q2 on. Interval 2 [t1 t2]: At t1, Q1 is on, and Q2 is off, as shown in Fig. 15. During this interval, the current in series inductances L1 and L2 continues to increase linearly and store the energy in these inductors. The energy stored in Co provides energy to the load. The return current is split only between Db and Dq2. Interval 3 [t2 t3]: At t2, Q1/Q2 is off again, and interval 1 is repeated, as shown in Fig. 14. During this interval, the current in series inductances L1 and L2 decreases linearly, and the energy in these inductors are released. The energy stored in L1 and L2 is released to the output through L1, D1, partially Dq2, L2, and Db. Interval 4 [t3 t4]: At t3, Q1 is off, and Q2 is on, as shown in Fig. 16. During this interval, the energy stored in L1 and L2 is released to the output through L1, D1, partially Q2, Dq2, L2, and Db.

6 M.K JAYAVELU, DR. R. V. KRISHNAIAH The operation of the converter during the negative input voltage half-cycle is similar to the operation of the converter during the positive input voltage half-cycle. The estimated loss distribution of the semiconductors is provided in Fig. 18 at 70 khz switching frequency, 240 V input, and 3300 W load for benchmark conventional boost and interleaved boost converters and the proposed PSSB boost converter. at 70 khz switching frequency, 240 V input, and 3300 W load at 400 V. IV. EXPERIMENTAL RESULTS A prototype of the proposed PSSB boost PFC converter was built. In addition, prototypes of an interleaved boost converter and a semi-bridgeless boost converter were built to benchmark the proposed converter. The components used in experimental prototypes are provided in Table I. TABLE I SEMICONDUCTOR USED IN EXPERIMENTAL PROTOTYPES Fig.17 PSSB boost converter steady-state waveforms for D < 0.5. Fig. 19 (Top) Control board. (Bottom) Power board. Fig. 18 Comparison of the estimated loss distribution in the semiconductors. Fig.20 Efficiency as a function of output power at Vin = 240 V, Vo =400 V, and 70 khz switching frequency.

7 AC DC Converter for Semi-Bridgeless using Phase-Shifted Gating Technique Fig. 19 shows the proposed phase-shifted bridgeless boost prototype. It consists of a control board and a power board attached to a heat sink with the PFC inductors. The experimental efficiency of the phase-shifted bridgeless boost converter, benchmark interleaved boost converter, and conventional bridgeless boost converter are provided in Fig. 20 for 240 V input and in Fig. 21 for 120 V input at 70 khz switching frequency and 400 V output. The lightload efficiency of the proposed converter is significantly better than that of the benchmark interleaved boost PFC due to the absence of the input rectifier bridge. However, as Fig.23 PSSB measured THD as a function of output power at Vin = 120 and 240 V, Vo = 400 V, and 70 khz switching frequency. Fig.21 Efficiency as a function of output power at Vin = 120 V, Vo =400 V, and 70 khz switching frequency. the load increases, the efficiency drops due to additional heat dissipation in the intrinsic body diodes of the MOSFETs. A family of efficiency curves for the proposed converter versus output power at different line voltages is provided in Fig. 22. It is observed that a peak efficiency of 98.8% is achieved at 265 V input and 1000 W load. To verify the quality of the input current in the proposed converter, the measured input current total harmonic distortion (THD) is provided in Fig. 23. The mains current THD is less than 5% from half load to full load, and it is compliant with IEC (see Fig. 25). Fig.22 Efficiency as a function of output power at Vo = 400 V, 70 khz switching frequency, and input voltages from 90 to 265 V. Fig.24 PSSB measured power factor as a function of output power at Vin =120 and 240 V, Vo = 400 V, and 70 khz switching frequency.

8 M.K JAYAVELU, DR. R. V. KRISHNAIAH A/div. Ch4 = Iin 10 A/div. Fig.25 PSSB measured harmonic orders at Vin = 120 and 240 V, as compared against the EN standard. Fig.28 Proposed PSSB gating signal, inductor current, and sensed MOSFET current for D < 0.5. X-axis: time 5 ms/div. Y -axes: Ch1 = VG1 10 V/div. Ch2 = IQ1 2 V/div. Ch3 = IL1 10 A/div. Fig.26 Proposed PSSB input current, input voltage, and output voltage. X-axis: time 5 ms/div. Y -axes: Ch1 = Vo 100 V/div. Ch2 = Vin 100 V/div.Ch4 = Iin 10 A/div. The PSSB measured power factor is provided in Fig. 24 over the entire load range for 120 and 240 V input. The power factor is greater than 0.99 from half load to full load. The PSSB harmonics are provided and compared with the EN class-d standard in Fig. 25. The proposed converter meets the class-d standard limits for all harmonics. Experimental waveforms from the proposed converter prototype are provided in Figs The input current, input voltage and output voltage are given in Fig. 26. As shown, Fig.29 Proposed PSSB gating signal, inductor current, and sensed MOSFET current for D > 0.5. X-axis: time 5 ms/div. Y -axes: Ch1 = VG1 10 V/div. Ch2 = IQ1 2 V/div. Ch3 = IL1 10 A/div. the input current is in phase with the input voltage and has a sinusoidal shape. Additionally, there is a low-frequency ripple on the output voltage, which is inversely proportional to the value of PFC bus output capacitors. The inductor current, input current, and current sensed in the MOSFET through a current transformer are provided in Fig. 27. It is noted that during the positive half-cycle, the inductor current is the same as the input current. However, during the negative half-cycle, the input current is partially flowing through slow diodes Da and Db. The gating signals, sensed MOSFET current, and inductor current are provided for duty cycles less than 0.5 in Fig. 28 and greater than 0.5 in Fig. 29. These waveform shapes match the theoretical expected waveforms. Fig.27 Proposed PSSB inductor current, input current, and sensed MOSFET current. X-axis: time 5 ms/div. Y -axes: Ch1 = Sensed IQ1 2 V/div. Ch3 = IL1 /IDb 10 CONCLUSION A high-performance PSSB ac dc boost PFC converter topology has been proposed to simplify the currentsensing technique for the semi-bridgeless PFC converter. The converter features high efficiency at light-load and

9 AC DC Converter for Semi-Bridgeless using Phase-Shifted Gating Technique low-line conditions, which is critical to minimize the charger size, cost, charging time, and amount and cost of electricity drawn from the utility. The converter is ideally suited for automotive level-i residential charging applications in North America, where the typical supply is limited to 120 V and 1.44 kva. An analysis and performance characteristics have presented. A prototype converter circuit was built to verify the proof of concept. Theoretical wave forms were presented and compared with the results taken from the prototype. Experimental results demonstrate that the mains input current THD is less than 5% from half load to full load, and the converter is compliant with the IEC class-d standard. The converter power factor was also provided at full load for 120 and 240 V input. The power factor is greater than 0.99 from 50% load to full load. The proposed converter achieves a peak efficiency of 98.8% at 265 V input and 1 kw output power. REFERENCES [1] Y. J. Lee, A. Khaligh, and A. Emadi, Advanced integrated bidirectional AC DC and DC DC converter for plug-in hybrid electric vehicles, IEEE Trans. Veh. Technol., vol. 58, no. 8, pp , Oct [2] K. Morrow, D. Karner, and J. Francfort, Plug-in hybrid electric vehicle charging infrastructure review, U.S. Dept. Energy Veh. Technol. Program, Washington, DC, [3] L. Petersen and M. Andersen, Two-stage power factor corrected power supplies: The low componentstress approach, in Proc. IEEE APEC, 2002, vol. 2, pp [4] B. Singh, B. N. Singh, A. Chandra, K. Al-Haddad, A. Pandey, and D. P. Kothari, A review of single-phase improved power quality AC DC converters, IEEE Trans. Ind. Electron., vol. 50, no. 5, pp ,Oct [5] M. O Loughlin, An interleaved PFC preregulator for high-power converters, in Proc. Texas Instrum. Power Supply Design Semin., 2007, pp [6] Y. Jang and M. M. Jovanovic, Interleaved boost converter with intrinsic voltage-doubler characteristic for universal-line PFC front end, IEEE Trans. Power Electron., vol. 22, no. 4, pp , Jul [7] L. Balogh and R. Redl, Power-factor correction with interleaved boost converters in continuous-inductorcurrent mode, in Proc. IEEE Appl. Power Electron. Conf. Expo., 1993, pp [8] C. Wang, M. Xu, and F. C. Lee, Asymmetrical interleaving strategy for multi-channel PFC, in Proc. IEEE Appl. Power Electron. Conf. Expo.,2008, pp [9] P. Kong, S. Wang, and F. C. Lee, Common-mode EMI study and reduction technique for the interleaved multichannel PFC converter, IEEE Trans. Power Electron., vol. 23, no. 5, pp , Sep [10] C. Wang, M. Xu, F. C. Lee, and B. Lu, EMI study for the interleaved multi-channel PFC, in Proc. IEEE PESC, 2007, pp [11] B. Lu, R. Brown, and M. Soldano, Bridgeless PFC implementation using one cycle control technique, in Proc. IEEE Appl. Power Electron. Conf. Expo., 2005, vol. 2, pp [12] C. Petrea and M. Lucanu, Bridgeless power factor correction converter working at high load variations, in Proc. ISSCS, 2007, vol. 2, pp [13] U. Moriconi, A bridgeless PFC configuration based on L4981 PFC controller, STMicroelectronics, Geneva, Switzerland, STMicroelectron. Appl. Note AN1606, [14] J. M. Hancock, Bridgeless PFC boosts low-line efficiency, Infineon Technol., Milpitas, CA, [15] Y. Jang, M. M. Jovanovic, and D. L. Dillman, Bridgeless PFC boost rectifier with optimized magnetic utilization, in Proc. IEEE Appl. Power Electron. Conf. Expo., 2008, pp [16] Y. Jang and M. M. Jovanovic, A bridgeless PFC boost rectifier with optimized magnetic utilization, IEEE Trans. Power Electron., vol. 24 no. 1, pp , Jan [17] W. Y. Choi, J. M. Kwon, E. H. Kim, J. J. Lee, and B. H. Kwon, Bridgeless boost rectifier with low conduction losses and reduced diode reverse-recovery problems, IEEE Trans. Ind. Electron., vol. 54, no. 2, pp , Apr [18] L. Huber, J. Yungtaek, and M. M. Jovanovic, Performance evaluation of bridgeless PFC boost rectifiers, IEEE Trans. Power Electron., vol. 23, no. 3, pp , May [19] W.-Y. Choi, J.-M. Kwon, and B.-H. Kwon, Bridgeless dual-boost rectifier with reduced diode reverse-recovery problems for power-factor correction, IET Power Electron., vol. 1, no. 2, pp , Jun [20] M. Ramezani and S. M. Madani, New zero-voltageswitching bridgeless P, using an improved auxiliary

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