SMALL SIGNAL MODELING OF DC-DC POWER CONVERTERS BASED ON SEPARATION OF VARIABLES

Transcription

1 SMA SGNA MOENG OF CC POWER CONERTERS BASE ON SEPARATON OF ARABES BY NG POH KEONG (B.S.E.E, University of Kentucky, USA) EPARTMENT OF EECTRCA AN COMPUTER ENGNEERNG A THESS SUBMTTE FOR THE EGREE OF MASTER OF ENGNEERNG NATONA UNERSTY OF SNGAPORE 3

2 ACKNOWEGEMENT woul like to thnk my fmily n prents for giving me the morl support n encourgement to complete my thesis. Mny thnks to my fincee, Joy Ty, who encourge me to give my best. m very thnkful to my thesis min visor, r. Orugnti n covisor r. Y. C ing. Wors re inequte to epress my pprecition n grtitue to r. Orugnti for his guince, ptience, n epertise to my thesis n cemic life. m lso very thnkful to ll my friens in the Center for Power Electronics (999~) in the Ntionl University of Singpore, for proviing me lively stuent life throughout my cemic work in the reserch lbortory.

3 SUMMARY Smll Signl Moeling of CC Converters Bse on Seprtion of ribles Most CC power converters hve negtive feebck system to regulte the output voltge. The performnce of this regultor epens on the esign of the feebck control loop, which is in turn bse on the smll signl AC behvior of the converter. Fining this smll signl behvior woul be the first step tht esign engineer hs to tke. Although the literture mteril on this topic is bunnt, they re usully fr too comple for prcticl use. Even some prcticl methos eeme suitble for esign engineers cn be quite mthemticlly cumbersome especilly if there is new or unfmilir CC power converter. This iscourges esign engineers from using them. n view of these problems, more generl, simpler pproch for moeling CC converters is evelope in this thesis bse on seprtion of vribles metho. The seprtion of vribles metho (SM) is evelope intuitively bse on the ssumption tht converter circuit cn be seprte into two subcircuits. One subcircuit consists of vribles tht respon instntneously fst uner smll signl perturbtions, which is nme s fst ynmic group (FG), while the other subcircuit vribles rect slowly to these perturbtions, which comprises (reltively lrge) ynmicl components. Then these ynmicl components re replce with constnt sources, which result in new circuit clle fst ynmic equivlent circuit (FEC). Thus, the nlysis hs reuce to fining smll signl chrcteristic of the fst subcircuit whose moel prmeters or FM (fst ynmic moel) re constnts. Then smll signl equivlent circuit is constructe by connecting the FM to the lrge ynmicl components tht were once remove. Thus, the frequency responses of the converter cn be i

4 obtine either through circuit simultion or nlyticl pproches. The seprtion of vribles metho is pplie to hrswitche converters (buck, boost, n buckboost converters), softswitche (zerocurrentswitch qusiresonnt buck) converters, n resonnt converters (series resonnt converter with ioe conuction ngle control). Moel preictions re verifie by compring with those obtine from bruteforce SPCE simultion of the ctul circuit or with eisting results from other methos. The propose metho, so fr, is not suitble for converters with ynmic FM coefficients. To ccount for this effect, two moifictions to the seprtion of vribles metho re propose. The first moifiction, nme s seprtion of vribles metho type (SM), employs system ientifiction metho to moel the trnsient response of the fst ynmic moel coefficients. The poles n zeros re etrcte n then multiplie ppropritely to the FM (fst ynmic moel) constnt coefficients, s correction fctors. This results in new (more ccurte) equivlent circuit, which cn be nlyze through circuit simultion or mthemticlly. The secon moifiction or seprtion of vribles metho type (SM) employs smple t pproch to moel the FM ynmics. t is emonstrte tht the SM is esier thn other smplet contemporries. This technique results in nother (more ccurte) circuit moel, which is lso suitble for circuit simultion or mthemticl nlysis. ii

5 TABE OF CONTENTS Summry Tble of Contents Nomencltures ist of Abbrevitions/Acronyms ist of Figures ist of Tbles i iii vi viii i ii Chpter : ntrouction.: Bckgroun.: iterture Review 3.3: The Present Work: Motivtions n Aims 7.4: Project Results in Summry 8.5: Orgniztion of Thesis Chpter : evelopment of Seprtion of ribles Metho.: ntrouction.: Fst ynmic Moel (FM) evelopment.3: Smll Signl Circuit Moel 5.4: Seprtion of ribles Metho (SM) Algorithm 6.5: Summry 9 Chpter 3: Appliction Emples to HrSwitching Converters 3.: ntrouction 3.: Fst ynmic Moel (FM) for Continuous Conuction Moe (CCM) Cses iii

6 3..: Buck Converter Uner CCM: Fining FM by Circuit Perturbtion 3..: Boost Converter: Fining FM by Anlyticl 3 Metho 3..3: BuckBoost Converter: Fining FM by 39 Simultion Metho 3.3: Fst ynmic Moel for iscontinuous Conuction 46 Moe Cses 3.3.: Buck Converter (CM): Fining FM by 47 Anlyticl Approch 3.3.: Boost Converter: : BuckBoost Converter : Note on FMs for CM Cses : Smll Signl Circuit Moel : Obtining Smll Signl Responses : Anlyticl Metho : Simultion Metho 63 Chpter 4: Appliction Emples to SoftSwitching Converters 69 4.: ntrouction 69 4.: Brief Review of ZeroCurrentSwitch 7 QusiResonntCurrent (ZCSQRC) Buck Converter. 4.3 Fst ynmic Equivlent Circuit (FEC) of 7 ZeroCurrentSwitch QusiResonntConverter (ZCSQRC) Buck Converter in Hlf Wve Moe 4.4 Fining FM by Anlyticl Metho Fining FM by Simultion Metho Smll Signl Equivlent Circuit Moel Simultion Results Summry 88 iv

7 Chpter 5: Etension of SM Technique to Resonnt Converter 89 5.: ntrouction 89 5.: Bsic Opertion of Series Resonnt Converter (SRC) 9 5..: Brief Review of Stte Plne Anlysis : C Anlysis : imittion on Smll Signl Anlysis by SM Approch 5.5: SM Approch: ynmicl FM 9 5.6: SM Approch: Resonnt Tnk Fst ynmic 6 Moel (RFM) 5.6.: RFM n FM Coefficients 5.6.: Prcticl Metho to Compute RFM Coefficients : O Symmetry Problem of RFM : Smll Signl Anlysis by SM Approch 3 5.7: erifiction n Comprison of SM Techniques for 37 SRCCA 5.7.: Pspice Simultion for SRCCA : Simultion Results : Summry 43 Chpter 6: Conclusions n Future Work 45 6.: Summry of Work 45 6.: Bsic Seprtion of ribles Metho (SM) : Etension of SM Technique to Resonnt Converters : Overll Summry of SM Methos 5 6.5: Future Work 54 References 55 Appeni A 58 v

8 NOMENCATURES Note tht these symbols my be ccompnie by superscripts or subscripts in some chpters, which re not inicte here. Other rrely use symbols in following chpters re not inclue here. Symbols X Perturbtion of X where X is n rbitrry vrible α ioe Conuction Angle [8] β Switch Conuction Angle [8] C, C o Reltively rge lue Cpcitor Component C r Resonnt Cpcitor Component uty Rtio Control, b,, ioe Component f r C Resonnt Frequency f s Switching Frequency i C nstntneous Current of the Cpcitor C, C o i Cr nstntneous Current of the Resonnt Cpcitor C r i nstntneous Current of the oltge Source i nstntneous Current of the nuctor, o i r nstntneous Current of the Resonnt nuctor r i r(w) i r (t W ) Resonnt nuctor r Current t nstnt W i o nstntneous Current of the Resistor R, R o i rect nstntneous Rectifier Current i nstntneous Current of the oltge Source C Averge Current of the Cpcitor C Cr Averge Current of the Resonnt Cpcitor C r Averge Current of the oltge Source Averge Current of the nuctor (Cn be Component s well) r Averge Current of the Resonnt nuctor r vi

9 o Averge Current of the o Resistor R o rect Averge Rectifier Current Averge Current of the oltge Source, o Reltively rge lue nuctor Component r Resonnt nuctor Component Component Q, Q, Q Switch Component R o o Resistor Component R Switch Rius [8] t time t α ioe Conuction Time [8] t β Switch Conuction Time [8] t M Prticulr nstnt t M ; M rbitrry symbol T s Switching Perio v C nstntneous oltge of the Cpcitor C, C o v Cr nstntneous oltge of the Resonnt Cpcitor C r v nstntneous oltge of the nuctor, o v r nstntneous oltge of the Resonnt nuctor r v r(w) v r (t W ) Resonnt Cpcitor C r oltge t nstnt W v nstntneous oltge C Averge oltge of the Cpcitor C nput oltge Source Component Averge oltge of the nuctor Constnt oltge Source (Cn be Component s well) Z r Chrcteristic mpence of Resonnt Tnk vii

10 ST OF ABBREATONS/ACRONYMS CCM Continuous Conuction Moe CA ioe Conuction Angle CM iscontinuous Conuction Moe FEC Fst ynmic Equivlent Circuit FG Fst ynmic Group FM Fst ynmic Moel AC njecte Absorbe Current [4] PRC Prllel Resonnt Converter RFM Resonnt Tnk Fst ynmic Moel SRC Series Resonnt Converter SSA Stte Spce Averging [] SM Seprtion of ribles Metho SM Seprtion of ribles Metho Type SM Seprtion of ribles Metho Type viii

11 ST OF FGURES Fig..: A Boost Converter 4 Fig..: Fst ynmic Equivlent Circuit (FEC) for the Boost Converter 4 Fig..3: Smll Signl Circuit Moel 6 Fig..4 Seprtion of ribles Metho Algorithm 8 Fig. 3.: Buck Converter in CCM 3 Fig. 3.: FEC for Buck 4 Fig. 3.3: Buck Converter uner CCM: Perturbing nput oltge Converter 4 Fig. 3.4: Buck Converter uner CCM: 5 nuctor oltge for nput oltge Perturbtion. Fig. 3.5: Buck Converter uner CCM: Perturbing Output oltge 7 Fig. 3.6: Buck Converter uner CCM: Perturbing nuctor Current 8 Fig. 3.7: Buck Converter uner CCM: Perturbing uty Rtio 3 Fig. 3.8: Boost Converter in CCM 33 Fig. 3.9: FEC for Boost Converter 33 Fig. 3.: Wveforms of Fst ribles 34 Fig. 3.: BuckBoost Converter 4 Fig. 3.: FEC for BuckBoost Converter 4 Fig. 3.3: BuckBoost Converter: Perturbtion of 4 Fig. 3.4: BuckBoost Converter: Fst ribles Response to Perturbtion 43 Fig. 3.5: FEC for Buck Converter in CM 48 Fig. 3.6: Buck Converter uner CM: nuctor Wveforms 49 Fig. 3.7: Averge Smll Signl Circuit Moel of the Converter uner CCM 57 i

12 Fig. 3.8: Averge Smll Signl Circuit Moel of the Converter uner CM 57 Fig. 3.9: Buck Converter Smll Signl Moel Using FM Pspice igrm 64 Fig. 3.: Smll Signl Frequency Response for Buck Converter uner CCM 65 Fig. 3.: Smll Signl Frequency Response for Boost Converter 67 Fig. 3.: Smll Signl Frequency Response for BuckBoost Converter 67 uner CCM Fig. 4.: ZCS QRC Buck Converter (HlfWve) 7 Fig. 4.: Resonnt nuctor Current (i r ) n Resonnt Cpcitor oltge (v Cr ) 7 Behvior of the ZCSQRC Buck Converter in HlfWve Moe Fig. 4.3: FEC of the ZCS QRC Buck Converter (HlfWve) 7 Fig. 4.4: FEC Pspice Moel for ZCSQRCBuck (HW) Hving Two 79 ifferent nput oltges to Emulte Step Chnge Fig. 4.5: The Perturbe Response of the Averge Current from the 79 Pspice Moel in Fig. 4.4 Fig. 4.6: The Perturbe Response of the Averge oltge from the 8 Pspice Moel in Fig. 4.4 Fig. 4.7: Two Stey Stte Pspice Moels to Emulte Output Current Step 8 Chnge from.63a to.6363a Fig. 4.8: Behvior of Current uner Stey Stte n Perturbe Conitions 8 Fig. 4.9: Behvior of oltge uner Stey Stte n Perturbe Conitions 8 Fig. 4.: Smll Signl Circuit Moel of ZCS QRC Buck HW 84 Fig. 4.: ControltoOutput Frequency Response Curves For the 85 ZCSQRCBuck Hlf Wve Fig. 4.: nputtooutput Frequency Response Curves For 86 ZCSQRCBuck HlfWve Fig. 4.3: Smll Signl AC Moel of ZCSQRCBuck HlfWve Bse 87 on []

13 Fig. 5.: Series Resonnt Converter in HlfBrige Switch Arrngement 9 Fig. 5.: Resonnt nuctor Current of SRC 93 Fig. 5.3: Resonnt Cpcitor oltge of SRC 94 Fig. 5.4: SttePlne Trjectory of SRC uner CCM in Below Resonnt[8] 96 Fig. 5.5: SRCCA: Switching Frequency versus Switch Rius Fig. 5.6: FEC for SRCCA Fig. 5.7: FG for SRCCA 3 Fig. 5.8: Smll Signl Circuit Moel of SRCCA Using SM 6 Fig. 5.9: nputtooutput Frequency Responses of SRCCA vi SM 7 Fig. 5.: ControltoOutput Frequency Responses of SRCCA vi SM 8 Fig. 5.: Smple nuctor Current ynmics Aginst Number of Switching Cycle, ue to: () Perturbe, (b) Perturbe o, n (c) Perturbe α Fig. 5.: First Orer System s Step Response Curve Fig. 5.3: Smll Signl Circuit Moel of the SRCCA with Correcte FM 3 Coefficients Fig. 5.4: nputtooutput Frequency Responses of SRCCA vi SM n 4 SM Fig. 5.5: ControltoOutput Frequency Responses of SRCCA vi SM n 5 SM Fig. 5.6: Resonnt Tnk Behvior with ()iscrete Time nuctor Current 9 (b) iscrete Time Cpcitor oltge Fig. 5.7: nterconnection of FM n RFM with njecte ribles n Eternl Circuit i

14 Fig. 5.8: Response of the resonnt inuctor current fter onehlf perio uner () Perturbe resonnt inuctor current, i r (k) (b) Perturbe resonnt cpcitor voltge, v Cr (k) (c) perturbe input voltge, (k) () perturbe output voltge, o (k) n (e)perturbe control ngle, α(k) Fig. 5.9: Arbitrry Perioic Wveform () O Symmetry (b) Even Symmetry 3 Fig. 5.: Smll Signl Equivlent Circuit Moel for SRCCA using 35 FM n RFM Fig. 5.: PSPCE Reliztion of the Moel in Fig Fig. 5.: PSpice Reliztion of SRC with CA Control 38 Fig. 5.3: nputtooutput Frequency Responses of the SRCCA 4 using SM, SM, n SM Metho Fig. 5.4: ControltoOutput Frequency Response of the SRCCA 4 using SM, SM, n SM Methos Fig. 5.5: nputtooutput Frequency Response of the SRCCA 4 using SM with ifferent Smpling ntervl Fig. 5.6: ControltoOutput Frequency Response of the SRCCA 43 using SM with ifferent Smpling ntervl ii

15 ST OF TABES Tble 3.: esign Prmeters of the BuckBoost Converter 4 Tble 3.: Clcultion of Coefficients 45 Tble 3.3: esign Prmeters of the Buck Converter 64 Tble 3.4: esign Prmeters of the Boost Converter 66 Tble 4.: esign Prmeters for ZCSQRCBuck HlfWve 75 Tble 4.: Perturbtion of nput ribles 75 Tble 5.: esign Prmeters of the Series Resonnt Converter 98 With ioe Conuction Angle Control (SRC CA) Tble 5.: Clcultion of Perturbe Slow ribles 4 Tble 5.3: Perturbtion of ribles by Numericl Computtion 5 Tble 5.4: Comprison of ifferent SM Techniques for SRC CA 4 Tble 6.: Comprison of ifferent Smll Signl Anlysis Methos 5 iii

16 Chpter ntrouction Chpter ntrouction. Bckgroun Smll signl nlysis of power converter is concerne with moeling of the verge, linerize, smll signl AC behvior roun stey stte operting point of the system. The informtion obtine from this investigtion cn lter be use to preict the system trnsfer functions tht re useful in the feebck loop esign. iterture on smll signl nlysis, lso known s AC nlysis, for power converters is very well estblishe. There is neverening list of techniques n methos. To this y, literture on smll signl moeling re still growing. Some re compct n effective such s the sttespce verging (SSA) technique by Milebrook n Cuk []. Others re more mthemticlly intensive such s the work by Cliskn n et l [], Tymerski [3], n Sners n et l [4] tht utilize escribing function theory to estblish the trnsfer function. Besies, they cn be conceptully bstrct too. This sometimes hiners prcticing engineers from pplying these moeling techniques to their power supply esign. This is prticulrly true when frequency responses of new converter topologies re esire but not vilble in literture yet. Becuse power supply esigners hve very short timetomrket prouct esign phse ue to competitive business, these engineers will not hve time to igest the complicte techniques like [], [3], [4]. The use of strightforwr metho like system ientifiction, which trets converter s

17 Chpter ntrouction blck bo cn be mthemticlly bstrct such s [5], [6]. Thus, the metho is suitble, perhps, only for reserchers to eplore. Even wellestblishe clssicl cnonicl smll signl tool such s the sttespceverging (SSA) hs shortcomings. For emple, the compleity of the SSA [] technique increses when the orer of the converter nlyze is increse. t my be note tht the orer of the converter is proportionl to the number of pssive elements, nmely inuctor,, n cpcitor, C. Sometimes, when enhnce filtering effect is require, the forementione lrge pssive components re e such s CC network. Also, in resonnt converter n other softswitche converters, itionl inuctor n cpcitor my be use in orer to chieve softswitching. This in turn increses the orer. Another shortcoming of the sttespceverging technique is tht it is not pplicble to resonnt type of converters ue to the presence of fst vrying stte vribles in the converter. The primry motivtion for this thesis is to present smll signl moel tht is suitble for prcticing engineers. The technique is bse on n intuitive pproch in which the converter is seprte into slow prt n fst prt. The slow prt of the converter consists of components tht rect very slowly to perturbtions. The fst prt of the converter, on the contrry, consists of components tht rect lmost instntneously to perturbtions. The fst prt of the converter is nlyze first n its verge, liner response function is etermine. n crrying out this nlysis, the slow vribles ssocite with the slow prt re trete s C sources. The linerize response function

18 Chpter ntrouction of the fst prt is then couple to the slow prt of the converter to obtin the overll smll signl moel of the converter. Since the technique involves ivision of the converter circuit into slow prt n fst prt, it is given the nme Seprtion of ribles Metho (SM). This technique ws first evelope by r. Rmesh Orugnti [8]. n the present reserch work, the metho is evelope n presente in more inepth mnner. More importntly, the SM hs been pplie to greter rnge of power converter incluing converters in iscontinuousconuctionmoe (CM), qusiresonnt converters n resonnt converters. n prticulr, etension of SM technique to resonnt converters hs le to the generliztion of the metho to ccount for resonnt tnk ynmics lso.. iterture Survey The sttespceverging (SSA) metho propose by [] is wiely known smll signl nlysis tool, which employs verging technique. This moel is epresse by cnonicl stte mtri tht preicts the low frequency response behvior of the converter. Although this technique is simple to use n provies goo insight into the poles n zeros behvior of the converter circuit, it hs severl limittions. First, s mentione erlier, the sttespceverging compleity increses s the orer of the converter is increse. This is ue to the fct tht the orer of the cnonicl mtri is proportionl to the orer of the system. Secon, the metho cn only be pplie to slowly 3

19 Chpter ntrouction vrying stte vribles. Therefore, SSA is not pplicble to converters with fst vrying stte vribles such s qusiresonnt converters or resonnt converters. Thir, the en result of the nlysis is not smll signl circuit moel. A circuit moel is eeme beneficil becuse circuit simultion pproch cn be use to obtin esire trnsfer functions [9]. This is lso very prcticl s it oes not only sve time but vois mthemticl compleities tht usully rise uring smll signl nlysis. Hence it is reltive esier to use by the verge power electronics engineer on given power converter. The sttespceverging is etene to qusiresonntconverters in [7], known s the etension of sttespceverging metho or ESSA. Although one of the limittions of sttespceverging is resolve through this technique, other remining limittions re still unsolve. The implementtion of this metho, for instnce, is still very complicte ue to intensive mthemtics. This is unesirble for prcticing engineers. Furthermore, the ESSA metho cnnot be pplie to resonnt converters. Finlly, the nlysis oes not result in n equivlent circuit form. The pulsewithmoulte (PWM) switch moeling [] technique whose nlysis results in n equivlent circuit moel my seem to offer prcticl moeling tool to prcticing engineers. n this metho, linerize, smll signl, circuit moel (or lrge signl moel) replces the nonliner switch n ioe component t their three terminl points in the hrswitche type or qusiresonnt type converters. Once smll signl liner circuit moel replces these components, frequency responses of the converter cn 4

20 Chpter ntrouction be obtine through circuit simultion of the circuit moel. An nlyticl pproch to obtin trnsfer functions through circuit nlysis is lso possible. Although the ppliction of this metho is quite strightforwr n simple, isvntge is tht the equivlent smll signl moel must be erive nlyticlly through verging wveforms, which is quite teious. Another rwbck of this metho is tht it cnnot be pplie to resonnt type converters. There re vrious moeling techniques [8], however, cpble of performing smll signl nlysis of resonnt converters long with other converters such s [] [6], []. But most of these techniques re mthemticlly intensive. [3] offers quick wy for engineers to etermine resonnt converters trnsfer functions by the formuls presente. However, the nlysis is not generl s the formuls re evelope solely for series n prllel resonnt converters. A more generl pproch to el with resonnt converters is presente in []. The metho employs both continuous n iscrete pproches to evelop smll signl circuit moel. This metho woul pper to hve similr concept to our propose technique but, nevertheless, there re ifferences. The unerlying concept for the metho [] is to tret the stte vribles in the filter tnk s continuous quntities while the stte vribles in the resonnt tnk s iscrete quntities. Here, the uthors [] clime tht the eplicit form of equivlent circuit moel for the resonnt tnk is too complicte for prcticl use; therefore twoport lumpe prmeter equivlent circuit moel is propose, which bsorbs the resonnt tnk vribles. n effect, these resonnt stte vribles o not pper in the resultnt circuit moel. However, to rrive to this lumpe prmeter network, one must work through rigorous mthemticl 5

21 Chpter ntrouction nlysis. This is, of course, not fvore by prcticing engineers. This lumpe prmeter pproch is foun to be unnecessry s there is better wy to implement the moel prmeters, without engging cumbersome mthemtics. This is iscusse in Chpter 5 uner Section Until now, prcticl (which involves less mthemtics), simple, n generl smll signl moeling tool my be offere by the injecte bsorbe current metho [4]. n this metho, the slowly vrying stte vrible (cpcitor voltge) is etrcte from the system. This results in n orer reuction of one, which simplifies the nlysis. The metho then probes the behvior of the converter s input n output currents. By nlyzing these vribles smll signl behvior, the nlysis yiels n equivlent smll signl circuit moel, which cn be use for circuit simultion. n ition, the metho cn be pplie to bro clss of converters such s hrswitche converters [4], [5], qusiresonnt type converters [6], seriesresonntconverter (SRC) [4], n prllelresonntconverters (PRC) [7]. Still, the injecte bsorbe current metho hs some limittions. First, nlysis of high orer system converters my not be simplifie much by just reucing the system orer by one. Secon, the resonnt converters nlyze with this injecte bsorbe current metho, so fr, i not inclue the inner feebck control of the converter. Since the innerfeebck control is inherent to resonnt converters [7], it must be inclue in the moel nlysis otherwise the smll signl moeling of the converter is incomplete. 6

22 Chpter ntrouction.3 The Present Work: Motivtions n Aims. While the injectebsorbecurrent (AC) metho hs mny merits, there re two problems, which were pointe out erlier. Orer reuction by one my offer some relief for low orer converter s control nlysis but this woul not hve substntilly simplify high orer converters control nlysis. Then the effect of resonnt tnk ynmic ue to inner feebck control must be resse otherwise the smll signl moeling is incomplete. n view of these, the seprtionofvribles (SM) technique is evelope n presente in this project report, which hs fetures eeme prcticl n vntges over the injecte bsorbe current metho. The followings re the vntges of the propose SM.. Conceptully simple n esy to use. The propose metho seprtes the slow n fst vribles of converter. This llows orer reuction of severl mgnitues in the nlysis.. Applicble to resonnt converters with the innerfeebck ynmic, besies being pplicble to qusiresonnt converters n hrswitche converters. Also, SM is pplicble to both continuousconuctionmoe (CCM) n iscontinuousconuctionmoe (CM). 7

23 Chpter ntrouction 3. Moel prmeters cn be etermine either nlyticlly or through circuit simultion. The ltter is prticulrly importnt s this llows prcticing engineer to use this technique without much knowlege on mthemticl moeling methos..4 Project Results in Summry n this thesis, the following results re chieve n reporte:. The propose seprtionofvriblesmetho (SM) is evelope bse on intuitive unerstning of the converter ynmics. The bsic metho, ientifie s SM metho, simplifies the nlysis to nlyze the fst prt (nme Fst ynmic Group or FG). This results in the Fst ynmic Moel (FM), which moels the behvior of the circuit. The smll signl moel of the FG to perturbtions is then constructe by merely inserting in the slower responing components n vribles to FM.. The metho is then pplie to buck type, boost type, n buckboost type CC power converter. Both nlyticl n simultion bse pproches to etermine the moel prmeters re iscusse. Also, the seprtion of vribles metho is pplie to both continuous conuction moe (CCM) n iscontinuous conuction moe (CM) opertion of the converters. The liner 8

24 Chpter ntrouction smll signl moels obtine from the seprtion of vribles metho re verifie by compring their frequency responses with those obtine from pplying clssicl sttespce verging pproch. 3. The seprtion of vribles metho is pplie to qusiresonnttype converters. Both nlyticl n circuit simultionbse implementtion of the technique re presente. t is shown here tht the ltter metho cn llow n engineer to etermine the frequency response of qusiresonnt converter without n inepth knowlege of the converter opertion. 4. The seprtion of vribles metho is finlly pplie to resonnt converter, with series resonnt converter (SRC) uner ioe conuction control (CA) operting below resonnt frequency serving s n emple. ue to the presence of resonnt tnk components, the fst ynmic group of the converter oes not respon infinitely fst (s ssume in the seprtion of vribles metho) to perturbtions. Two moifictions (seprtion of vribles metho type or SM n seprtion of vribles metho type or SM ) to SM metho, which im to ccount for the ynmics of the resonnt tnk re propose n evlute. Seprtion of vribles metho type (SM) is simpler while slightly less ccurte thn seprtion of vriblesmetho type (SM), which is more comple. A simultionbse technique is opte in plce of eperimentl verifiction to verify the frequency response results provie by the ppliction of vrious SM 9

25 Chpter ntrouction methos. The intention here is to show the propose nlysis results in ccurte low frequency moel of the converter. t is not to show tht such theoreticl low frequency moel correspons to prcticl converters. Such justifiction hs been provie by mny reserchers erlier. n this technique, Pspice []9], [] moel of the resonnt converter uner ioeconuctionngle (CA) control is evelope. The control ngle is then perturbe by smll mount t vrious frequencies n the corresponing component in the output voltge ws etrcte..5 Orgniztion of Thesis This thesis consists of 6 chpters. Chpter emines the motivtion n im of the reserch project incluing brief literture survey. Chpter looks t the generl ie n concept of the SM technique. n Chpter 3, ppliction emples for hrswitche converters re shown n illustrte with ifferent pproches, ll uner the sme seprtion of vribles metho principle. Furthermore, converters operting in iscontinuous conuction moe conition re lso investigte. Chpter 4 illustrtes the seprtion of vribles metho concept to softswitching converters, nmely qusiresonnt converters. n Chpter 5, seprtion of vribles metho technique is etene to resonnt converters by consiering the resonnt tnk ynmics. Two possible moifictions to the seprtionofvriblesmetho techniques re presente n compre. Finlly Chpter 6 conclues the thesis.

26 Chpter evelopment of Seprtion of ribles Chpter evelopment of Seprtion of ribles Metho. ntrouction The propose Seprtion of ribles Metho (SM) offers simple pproch to obtin the low frequency smll signl moel of power converter. Most power converters cn be viewe s hving two istinct subcircuits. One recting slowly n the other rpily to eternl perturbtions. Typiclly, components tht rect slowly re the lrge pssive components like filter inuctors n filter cpcitors. On the other hn, components such s switches, ioes, resistors, iel trnsformers, etc respon very fst with very little ynmics. Typiclly, in most power converters, these components my be viewe s recting in n infinitely fst mnner. Recognizing tht there re ifferences in terms of response spees, the SM ivies the power circuit into two min subgroups, the slow n the fst subcircuit, n seprtes them. The components in the slow subcircuit re then replce by pproprite constnt voltge/current sources leving only the fst prt of the subcircuit to be nlyze for smll signl moeling purpose. The fst prt of the power converter herefter shll be referre s the Fst ynmic Group, FG.

27 Chpter evelopment of Seprtion of ribles One of the min vntges of the propose metho is the simplicity of the technique n proceures to obtin smll signl trnsfer functions. The metho is minly proceurl without comple mthemtics. Also, only the fst ynmic prt of the converter, which contins little or no ynmics, is nlyze/simulte for the smll signl moel evelopment, which simplifies the metho consierbly. Therefore, the SM shoul be ttrctive for prcticing engineers who re not incline towrs comple mthemticl moeling techniques. The metho cn be use to erive circuit moel for the smll signl behvior irectly. The circuit moel cn be nlyze further to erive trnsfer functions. The objective of this chpter is to introuce the concept n methoology of the propose SM. The orgniztion of this chpter is s follows: Section. eplins the evelopment of the Fst ynmic Moel (FM) of the converter. Section.3 then show how the smll signl circuit moel is obtine. Section.4 outlines the SM lgorithm bse on erlier iscussion to obtin smll signl moel. Section.5 summrizes the evelopments in this chpter.. Fst ynmic Moel (FM) evelopment Strictly speking, the SM seprtes the slow n fst vribles inste of the slow n fst subcircuits. These two groups of vribles re ssume to hve very ifferent frequency responses. As such, from the perspective of slow vribles, the fst

28 Chpter evelopment of Seprtion of ribles vribles hve infinitely fst response behvior. ikewise, from the perspective of the fst vribles, the slow vribles hve infinitely slow response behvior. Therefore the components ssocite with the slow vribles cn be replce by constnt voltge/current sources where vlues re equl to their verge vlues becuse within switching perio, ny slow vrible behves like constnt. Consier boost converter, for emple (See Fig..), in which the inuctor current n the output voltge vribles re consiere s slow vribles n my be replce by constnt sources s escribe erlier. The resulting circuit hs been nme s Fst ynmics Equivlent Circuit (FEC) s shown in Fig... Notice tht the verge inuctor current in Fig.. vries ccoring to the voltge pplie to inuctor. ikewise, the voltge cross the output voltge cpcitor vries ccoring to the current C through it (or current through C n R). Thus the output vribles of the FEC re trete s,, n. Here, is lso inclue in cse the smll signl impence ( / ) of the converter neee to be etermine. By perturbing the slow vribles (,,, n ) the output response of the FEC is etermine by nlyzing the FEC mthemticlly or through simultion. Note tht here n re inclue in the slow vribles s response to n chnges re usully require of the smll signl moel. 3

29 Chpter evelopment of Seprtion of ribles i i i o v Q i C C v C R o Fig..: A Boost Converter i v FG i Q Fig..: Fst ynmic Equivlent Circuit (FEC) for the Boost Converter The rtios between the FEC perturbe output vribles n the perturbe C sources re then obtine. These re /, /, /, /, etc. The mtri forme by these rtios is clle the Fst ynmic Moel (FM), which moels the smll signl response of the FEC. The FM for the boost converter will be in the form given by the following eqution: 4

30 Chpter evelopment of Seprtion of ribles (.) Here to 34 re the moel coefficients etermine by smll signl perturbtion nlysis of the FEC. Note tht FM is reltively esy to etermine becuse the compleity n ynmics of the originl converter is reuce consierbly in FEC through the nonconsiertions of slowly vrying vribles..3 Smll Signl Circuit Moel The FM provies the linerize, verge, smll signl moel of the fst prt (FEC) of the converter. The outputs of the FM re either fst vribles (such s ) tht ffect slow vribles (such s ) or output vribles such s neee for trnsfer function etermintion. The inputs of the FM re either converter inputs (such s, ) or slow vribles such s or. By simply combining the FM n the slow vribles/components, the smll signl circuit moel of the converter my be esily obtine (Fig..3). The interction between the circuit slow vribles n fst vribles re utomticlly tken cre of in this moel. 5

31 Chpter evelopment of Seprtion of ribles c 3 4 C c 3 4 C 3 3 c Fig..3: Smll Signl Circuit Moel Note tht with the evelopment of the liner circuit in Fig..3, the moeling is complete. The circuit in Fig..3 my be simulte in SPCE [9] in orer to obtin the smll signl frequency response of the converter. Alterntively, the circuit in Fig..3 cn be nlyze further to erive the mthemticl trnsfer function of the converter..4 Seprtion of ribles Metho (SM) Algorithm Fig..4 shows the steps involve in etermining the smll signl moel of given converter. n STEP, the power converter s operting point is etermine. This my be one either through nlysis or through circuit simultion. The fst n slow components re lso ientifie. The stey stte vlues of the slow vribles re then etermine. n 6

32 Chpter evelopment of Seprtion of ribles STEP, slow n fst components ssocite with slow n fst vribles re seprte into two subcircuits. Then the FG is ientifie within this step. STEP 3 involves simple proceure. All ientifie slow ynmicl components (the slow subcircuit element) re replce by constnt sources. This new equivlent circuit with constnt sources is clle FEC, s mentione before. Perturbing the constnt sources in STEP 4 llows responses of fst vrible to be mesure for computing FM. The FM foun in step 4 is use in STEP 5 to obtin the complete smll signl FM circuit moel. This is one by reconnecting the FM to its originl slow components s shown in Fig..3. The linerize n verge smll signl circuit moel of STEP 5 my be simulte irectly to obtin the esire smll signl frequency plots. Alterntively, the circuit my be nlyze further to etermine mthemticl epression for the converter trnsfer function. An importnt point to note is tht in STEP, STEP 4 or STEP 6, either mthemticl nlysis or circuit simultion cn be use s esire. This llows prcticing engineer to etermine the smll signl moel of the converter completely through simultion only without ny recourse to comple mthemtics. 7

33 Chpter evelopment of Seprtion of ribles STEP Power Converter Operting t Stey Stte Conition STEP Seprte Slow n Fst Components STEP 3 Replce Slow ynmicl Components with Constnt Sources to Obtin FEC STEP 4 Obtin FM by Perturbing Constnt Sources of the Slow ribles STEP 5 Obtin SM 3 Smll Signl Circuit Moel FEC Fst ynmics Equivlent Circuit STEP 6 Obtin Trnsfer Function(s) FM Fst ynmics Moel 3 SM Seprtion of ribles Metho Fig..4 Seprtion of ribles Metho Algorithm 8

34 Chpter evelopment of Seprtion of ribles.5 Summry This chpter hs outline bsic SM proceure to evelop n verge smll signl moel of power converter bse on seprtion of the circuit into slow n fst ynmicl prt. This bsic metho is intuitive in its pproch n simple to use compre to other conventionl methos. n the net two chpters (Chpter 3 n 4), the bsic SM technique is pplie to severl converters n operting conitions to estblish the vliity of the propose metho. n Chpter 5, the metho is etene to resonnt converters, where the fst ynmics vribles re not fully fst. 9

35 Chpter 3 Appliction Emples to HrSwitche Converters Chpter 3 Appliction Emples to HrSwitche Converters 3. ntrouction The objective of this chpter is to show the pplicbility of the propose SM to moeling some of the most common hrswitche converters, which re the buck, boost, n buckboost converters in both continuous conuction moe (CCM) n iscontinuous conuction moe (CM) opertions. These converters re the bsic hrswitche topologies tht cn be etene to vrious isolte power supply topologies such s flybck, forwr, n pushpull. A secon objective of this chpter is to show tht the SM proceure cn be pplie either through simultion or nlyticlly. Such fleibility llows converter s fst ynmic moel (FM) n trnsfer functions to be obtine either wy epening on the engineer s preference. Section 3. evelops the FM introuce in Chpter for buck, boost, n buckboost converters when operting uner continuous conuction moe (CCM). The moel prmeters re obtine nlyticlly in the cse of buck n boost converters. n the cse of the buckboost converter, the moel prmeters re obtine through OrC Pspice

36 Chpter 3 Appliction Emples to HrSwitche Converters [] simultion to illustrte the fesibility of obtining the coefficients through simultion. Section 3.3 evelops the fst ynmic moel for the sme converter uner iscontinuous conuction moe opertion. Section 3.4 first evelops the linerize, verge smll signl circuit moel for the converters uner iscussion. n Section 3.5, the smll signl performnces of the converters re then obtine first through mthemticl nlysis n then through simultion of the smll signl circuit moe. These results re compre with those obtine from clssicl stte spce verging techniques []. Finlly, Section 3.6 summrizes the chpter. 3. Fst ynmic Moel (FM) in Continuous Conuction Moe (CCM) Cses n the net severl subsections, the evelopment of the FM in few hrswitche converters re eplore. ifferent pproches for obtining the fst ynmic moel coefficients re consiere n presente. These illustrte the verstility of the propose seprtion of vribles metho. n subsection 3.., buck converter uner continuous conuction moe opertion is consiere. The technique use in this subsection relies on intuition n knowlege of the converter opertion. Such pproch is likely to be esy for eperience esigners to use. On the other hn, n nlyticl pproch to obtin the fst ynmic moel is opte in subsection 3.. for boost converter operting uner continuous conuction moe. n subsection 3..3, circuit simultion pproch is presente to compute buckboost converter s fst ynmic

37 Chpter 3 Appliction Emples to HrSwitche Converters moel prmeters. The lst mentione pproch neither requires much intuition with regr to circuit opertion nor oes it require mthemticl skills. This pproch tens to mechnize the evelopment of the smll signl moel n my be fvore by prcticing engineers. Once converter s FM (fst ynmic moel) is obtine, it cn be use for further nlysis to obtin the smll signl circuit moel of the converter n to obtin smll signl responses, s will be iscusse in Section Buck Converter uner CCM: Fining FM by Circuit Perturbtion This section illustrtes how buck converter s FM cn be obtine using bsic knowlege of the converter opertion. Fig. 3. epicts buck converter circuit, which is ssume to be operting in stey stte uner CCM (continuous conuction moe) conition. The inuctor current i n cpcitor voltge v C in Fig. 3. re the instntneous vlues. The slow vribles for this converter re the inuctor current i, cpcitor voltge v C, input voltge, n uty rtio. For the low frequency (verge) moel, these slow vribles cn be pproimte by their verge vlues tken over switching perio. The components n C tht re ssocite with the slow vribles cn be replce by their verge vlues. n other wors, is replce by constnt current source n C is replce by constnt voltge source. Here, the output

38 Chpter 3 Appliction Emples to HrSwitche Converters lo R o is lumpe together with the cpcitor C s single voltge source,. The cpcitor C is ssume to be very lrge so tht its voltge is ripple free n constnt. Furthermore, s cn be seen, the voltge cross the lo R o n the cpcitor C re the sme. This justifies the output circuit R o n C be lumpe together n replce by C voltge source. Although R o cn be seprte from C n be inclue in the fst ynmic prt of the converter, it offers no vntge s it oes not simplify the nlysis. The resultnt fst ynmic equivlent circuit (FEC) for the buck converter uner continuous conuction moe (CCM) is shown in Fig. 3.. Here, fter verge over cycle,,,, n re the slow vrible inputs to the FEC while the fst vrible responses of the FEC re,, n. Hence, in orer to etermine the fst ynmic moel (FM) of the converter, the verge, smll signl rtios of the output n input vribles of the fst ynmic equivlent circuit must be obtine. This is obtine by the perturbing smll mount one slow vrible t time, while holing ll other slow vribles constnt, n obtining the resultnt perturbtions (verge over switching cycle) of the fst vribles in the FEC. i Q i o v C R o i C v C o Fig. 3.: Buck Converter in CCM 3

39 Chpter 3 Appliction Emples to HrSwitche Converters FG Q Fig. 3.: FEC for Buck Converter nput oltge Perturbtion i Q i i Fig. 3.3: Buck Converter uner CCM: Perturbing nput oltge Here, the input voltge,, is perturbe by smll C vlue. The other slow vribles,, n re kept constnt. The perturbtion in cuses ll fst vribles to chnge by smll mount from their stey stte vlues. This is inicte in Fig

40 Chpter 3 Appliction Emples to HrSwitche Converters by the ition of superscript i sign to the vrible nme. Since there is no ynmicl component in the FG (fst ynmic group), ll fst vribles respon instntneously. Of course, it must be borne in min tht the fst vrible outputs of FEC (fst ynmic equivlent circuit) re verge vribles. By inspecting Fig. 3.3, it cn be seen tht the verge input current epens on the verge inuctor current n the uty rtio. Becuse these n i not chnge uring the perturbtion, the input current remins the sme. By unerstning the circuit perturbtion, the bove observtion is written s Eq. (3.). By similr resoning, the inuctor current is foun to be the sme s. Since ws not perturbe, will not chnge s well. This observtion is written s Eq. (3.). (3.) i (3.) i v (t) ( ) t T T Fig. 3.4: Buck Converter uner CCM: nuctor oltge for nput oltge Perturbtion. 5

41 Chpter 3 Appliction Emples to HrSwitche Converters Net, the chnge in verge inuctor voltge is obtine for perturbtion (See Fig. 3.4). The wveform in tht figure shows clerly tht when the input voltge is perturbe, the verge inuctor voltge is lso ffecte. The reltionship between the input n output chnges cn be erive from consiertion of the inuctor s voltsecon blnce. The verge stey stte inuctor voltge is given by, ( ) T ( ) T T (3.3) Perturbing by results in, i ( ) ( ) (3.4) efining i, i i ( ) ( ) (3.5) Thus, (3.6) i Eq. (3.6) gives the response i of the FEC (fst ynmic equivlent circuit) to smll signl perturbtion in. Note tht the reltionship is constnt since the FEC hs no ynmicl components. 6

42 Chpter 3 Appliction Emples to HrSwitche Converters Output oltge Perturbtion ii Q ii ii Fig. 3.5: Buck Converter uner CCM: Perturbing Output oltge Figure 3.5 shows the fst ynmic equivlent circuit of the buck converter circuit with its voltge source being perturbe by. From the circuit, one cn esily euce tht this perturbtion will not chnge n. The only chnge occurs in the inuctor voltge. Thus, (3.7) ii (3.8) ii 7

43 Chpter 3 Appliction Emples to HrSwitche Converters To etermine the perturbe verge inuctor voltge, is substitute for in Eq. (3.3), ( ) ( )( ) ii (3.9) Retining only the first orer perturbtion terms of Eq. (3.9), (3.) ii Here, the superscript ii refers to the effect ue to perturbtion of. nuctor Current Perturbtion iii Q iii iii Fig. 3.6: Buck Converter uner CCM: Perturbing nuctor Current 8

44 Chpter 3 Appliction Emples to HrSwitche Converters The itionl prllel current source in Fig. 3.6 cretes smll chnge to. This results in chnges to n vribles. n orer to obtin the perturbtion coefficients, consier the C reltionship between input current n inuctor current. (3.) Perturbing in Eq. (3.), iii iii ( ) (3.) Retining only the first orer perturbtion terms, (3.3) iii Since, the perturbe is, (3.4) iii From Fig. 3.4, the inuctor current cn be seen to hve no influence on the inuctor voltge. Thus, (3.5) iii Here, the superscript iii refers to the effect ue to perturbtion of. 9

45 Chpter 3 Appliction Emples to HrSwitche Converters utyrtio Perturbtion i Q i i Fig. 3.7: Buck Converter uner CCM: Perturbing uty Rtio Figure 3.7 shows the FEC (fst ynmic equivlent circuit) with uty rtio being perturbe by. Eq. (3.) inictes tht the input current is ffecte by the perturbtion in. By substituting term into this eqution, iv (3.6) Since, which is constnt source, perturbing hs no effect on. Thus, (3.7) iv Net, Fig. 3.4 shows tht the verge inuctor voltge epens on. Substituting into Eq. (3.3), ( )( ) ( ) iv (3.8) 3

46 Chpter 3 Appliction Emples to HrSwitche Converters Retining only the first orer perturbtion terms, iv (3.9) Here, the superscript iv refers to the effect ue to perturbtion of. Fst ynmic Moel (FM) Coefficients Using the superposition principle, Eqs. (3.), (3.7), (3.3), n (3.6) cn be e together, i ii iii iv (3.) Similrly, from Eqs. (3.), (3.8), (3.4), n (3.7), i ii iii iv (3.) ikewise, from Eqs. (3.6), (3.), (3.5), n (3.9), i ii iii iv (3.) 3

47 Chpter 3 Appliction Emples to HrSwitche Converters Combining Eqs. (3.) (3.), the fst ynmic moel (FM) cn be written s, (3.3) Eq. (3.3) escribes the ynmic behvior of the fst subcircuit (FEC) of the buck converter. This moel hs four slow vrible inputs,,, n, n three fst vrible outputs,, n. Ecept for the constnt input, ech output hs complementry input n the inputoutput pir reltes to n eternl component. Thus, the response is pire up with n together relte to the input smll signl voltge source. Similrly, n re couple to the lumpe R o n C output circuit, n n re couple to the inuctor. 3.. Boost Converter: Fining FM by Anlyticl Metho n the previous emple, the FM (fst ynmic moel) coefficients re erive irectly from circuit lrgely bse on intuition. n this emple, the FM prmeters re erive nlyticlly. 3

48 Chpter 3 Appliction Emples to HrSwitche Converters i i o v Q i C C v C R o Fig. 3.8: Boost Converter in CCM A boost converter, which is ssume to be operting in stey stte uner CCM is shown in Fig The inuctor n cpcitor C re slow components becuse their ssocite current n voltge vribles re reltively slow. The low frequency pproimtion is gin me here so tht ll slow vribles behve s constnts uring switching perio. Other slow vribles re the input voltge n uty rtio. Replcing the slow components by sources s before, we obtin the FEC (fst ynmic equivlent circuit) for the boost converter (Fig. 3.9). Here, the vlue,, n represent the verge stey stte vlues of these vribles. i v FG Q Fig. 3.9: FEC for Boost Converter 33

49 Chpter 3 Appliction Emples to HrSwitche Converters n this nlyticl pproch, ll C reltionships between the input n the output vribles re etermine first. The output vribles re, n. Of these, equls. By inspecting the reltime wveforms (See Fig. 3.) of the fst vribles nmely i ( i ) n v, one cn etermine the C reltionship between the output vribles,, n the input vribles,,, n. i (t) t v (t) t ( ) T T Fig. 3.: Wveforms of Fst ribles 34

50 Chpter 3 Appliction Emples to HrSwitche Converters Averging the instntneous current i in Fig. 3. over switching perio, T T T [ ] T T T i ( t) t T T ( T T ) T t ( ) (3.4) Agin from Fig. 3., the verge inuctor voltge my be obtine s follows, T T T T v ( t) t T ( ) { T ( )( T T )} ( )( ) t T T t (3.5) Rewriting the bove results, (3.6) ( ) (3.7) ( ) ( ) (3.8) 35

51 Chpter 3 Appliction Emples to HrSwitche Converters 36 n generl, the output vribles re epenent on the input vribles s follows. ( ) f,,, (3.9) ( ) f,,, (3.3) ( ) f,,, 3 (3.3) Smll signl input current, From Eq. (3.9), Tylor series epnsion of st orer is performe. f f f f (3.3) Since f, (3.33) Thus, (3.34)

52 Chpter 3 Appliction Emples to HrSwitche Converters 37 Smll signl lumpe output circuit current, From Eq. (3.3), in similr mnner s before n thus, f f f f (3.35) From Eqs. (3.3) n (3.7), ) ( f (3.36) ) ( f (3.37) f ) ( (3.38) f ) ( (3.39)

53 Chpter 3 Appliction Emples to HrSwitche Converters 38 Hence, from Eqs. (3.35) to (3.39), (3.4) Smll signl inuctor voltge, ikewise, from Eq. (3.3), f f f f (3.4) From Eqs. (3.3) n (3.8), ( ) 3 f (3.4) ( ) ( ) f 3 (3.43) ( ) 3 f (3.44) ( ) f 3 (3.45)

54 Chpter 3 Appliction Emples to HrSwitche Converters 39 Thus, from Eqs. (3.4) to (3.45), ( ) (3.46) We cn now combine Eqs. (3.34), (3.4), n (3.46) to form the FM for the boost converter uner CCM. ( ) ( ) (3.47) 3..3 BuckBoost Converter: Fining FM by Simultion Metho n section 3.., the buck converter s FM (fst ynmic moel) is erive using intuition regring the converter opertion. Section 3.. took n nlyticl pproch to obtin the FM of boost converter. n this section, the fst ynmic moel of buckboost converter (see Fig. 3.) will be obtine through circuit simultion. The converter is ssume to be operting uner CCM (continuous conuction moe). One of the strengths of the SM (seprtion of vribles metho) technique lies in tht the metho llows n engineer to obtin the moel prmeters by circuit simultion only, thus voiing the nee for mthemticl nlysis. n other wors, prcticing engineers without

55 Chpter 3 Appliction Emples to HrSwitche Converters etile theoreticl knowlege of the converter opertion cn still fin the esire trnsfer function by simulting the ctul circuit esign. Another vntge, this pproch llows us to incorporte the effects of prsitic elements into the smll signl moel with reltive ese. The following eplins how this is one. Since this metho is bse on ctul simultion of the FEC (fst ynmic equivlent circuit) of the power converter, the specifictions of the converter must be known. For this purpose, the following esign specifictions re ssume (See Tble 3.). i Q o v i i C C v C R o Fig. 3.: BuckBoost Converter i FG Q i v 4

56 Chpter 3 Appliction Emples to HrSwitche Converters Fig. 3.: FEC for BuckBoost Converter Tble 3.: esign Prmeters of the BuckBoost Converter nput oltge: Output oltge: o 5 Filter nuctor: mh Filter Cpcitor: C µf o Resistor: R o 5Ω Switching Frequency: f s 3kHz uty Rtio: o /( o ).454 Output Current: o o /R o.3a nuctor Current: o /().353A The fst ynmic equivlent circuit for the buckboost converter is obtine s before n is shown in Fig. 3.. The input vribles re ientifie s,, n wheres the output vribles re, n. The form of fst ynmic moel is shown s in Eq. (3.48) (3.48) The coefficients,, etc cn be foun by tking the rtio between n input vrible n n output vrible. Perturbtion in Output rible mn (3.49) Perturbtion in nput rible Where mn is the coefficient corresponing to m th row n n th column. 4