AT120/AT125 Micro-Power Voltage Detector, Delay Circuit Built-In

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1 FEATURES DESCRIPTION Highly Accuracy:±2% Low Power Consumption:1.0µA(TYP.) at =2.0V Detect Voltage Range:1.2V ~ 5V in 50mV increments Operating Voltage Range:1V ~ 6V Detect Voltage Temperature Characteristics: ±100ppm/ c Built-In Delay Circuit Output configuration:n-channel open drain or CMOS APPLICATIONS Microprocessor Reset Circuitry Memory Battery Back-up Circuits Power-on Reset Circuits Power Failure Detection System Battery Life and Charge Voltage Monitors Delay Circuitry Portable / Battery-Power Equipment The AT120/AT125 series are highly accurate and ultra low power consumption voltage detectors. It offers internally fixed threshold levels with 50mV per step range from 1.2V to 5V. A delay circuit is built-in to each detector. Low power consumption makes the AT120/AT125 ideal for use in portable equipment. The AT120 is available in SOT-23, SOT-25, SOT-343, SOT-89 and TO-92 packages. And AT125 is available in SOT-23 package type. Both CMOS and N-channel open drain output configuration are available. Since the delay circuit is built-in, peripherals are unnecessary and high density mounting is possible. ORDER INFORMATION PIN CONFIGURATIONS (TOP VIEW) AT 120 XX-X.X KD R Shipping: IAT R: Tape & Reel Circuit Type T: Tube KD: SOT-23 CA: CMOS, none delay KE: SOT-25 CD: CMOS, 160ms~400ms KM4: SOT-343 built-in delay KG: SOT-89 NA: N-ch open drain, none delay TD: TO-92 NC: N-ch open drain, 50ms~200ms Detect Voltage: built-in delay 1.2V~5V in 50mV increments 1

2 ORDER INFORMATION PIN CONFIGURATIONS (TOP VIEW) IAT Circuit Type AT 125 XX-X.X KD R Shipping: R: Tape & Reel T: Tube CA: CMOS, none delay CD: CMOS, 160ms~400ms built-in delay NA: N-ch open drain, none delay NC: N-ch open drain, 50ms~200ms built-in delay KD: SOT-23 Detect Voltage: 1.2V~5V in 50mV increments PIN DESCRIPTIONS Pin Name Pin Description Supply Voltage Input V SS Ground V OUT Output (Rest V OUT ) NC No Connection TYPICAL APPLICATION CIRCUITS R 100kΩ V OUT V OUT V SS V SS CMOS output N-channel open drain output 2

3 BLOCK DIAGRAM (1) CMOS Output (2) N-ch Open Drain Output V OUT Delay Circuit V OUT Delay Circuit Vref Vref V SS V SS ABSOLUTE MAXIMUM RATINGS (Note 1) Parameter Symbol Max Value Unit Input Voltage 7 V Output Current I OUT 50 ma Output Voltage CMOS V SS -0.3 to +0.3 V V OUT N-ch open drain V SS -0.3 to 6 V Operating Junction Temperature Rang T J 150 C Storage Temperature Range T STG -65 to +150 C Lead Temperature (Soldering 5 sec) T LEAD 260 C SOT Power Dissipation SOT P T A =25 C SOT-343 P D 250 mw (Note 2) SOT TO SOT Thermal Resistance SOT Junction to Ambient SOT-343 Θ JA 400 C/W (Note2) SOT TO SOT Thermal Resistance SOT-25 Θ JC Junction to Ambient SOT C/W ESD Rating (Human Body Model)(Note 3) V ESD 2K V 3

4 RECOMMENDED OPERATING CONDITIONS (Note 4) Parameter Symbol Operation Conditions Unit Supply Voltage, 1 to 6 V Operating Junction Temperature Range T J -40 to +125 C Operating Ambient Temperature Range T OPA -40 to +85 C Note 1: Stresses listed as the above Absolute Maximum Ratings may cause permanent damage to the device. These are for stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. Note 2: Thermal Resistance is specified with the component mounted on a low effective thermal conductivity test board in free air at T A =25 C. Note 3: Devices are ESD sensitive. Handling precaution recommended. Note 4: The device is not guaranteed to function outside its operating conditions. ELECTRICAL CHARACTERISTICS T A =25 C, unless otherwise specified. Parameter Symbol Test Conditions Test Circuit Min Typ Max Unit Detect Voltage V DF 1 V DF X0.98 V DF (Note 5) V DF X1.02 V Hysteresis Range (Note 6) V HYS 1 V DF V DF V DF X0.05 X0.02 X0.08 V = 1.5V = 2.0V Supply Current I SS = 3.0V µa = 4.0V = 5.0V Operating Voltage V DF = 1.2V to 5.0V V N-ch V DS =0.5V =1.0V =2.0V =3.0V Output Current I OUT =4.0V ma =5.0V P-ch V DS = 2.1V = 6.0V (with CMOS output)

5 ELECTRICAL CHARACTERISTICS (CONTINUED) T A =25 C, unless otherwise specified. Detect voltage Temperature Parameter Symbol Test Conditions Characteristics Transient Delay Time AT120NC Series AT120CD Series (V DR V OUT inversion) VDF TOPR x VDF Note 5: V DF : Established detect voltage value. Note 6: V HYS = V DR - V DF, V DR = Release Voltage. MEASURING CIRCUITS Test Circuit -40 C T OPA 85 C ± 100 T DLY Changes from 0.6V to 6V 5 Circuit 1 Circuit 2 Min Typ Max Unit ppm/ C ms Circuit 3 Circuit 4 Circuit 5 Note: Not necessary with CMOS output products. 5

6 TYPICAL OPERATING CHARACTERISTICS 6

7 APPLICATION INFORMATION OPERATION CMOS output 1. As an early state, the input voltage pin is applied sufficiently high voltage to the release voltage. While the input pin voltage ( ) starts dropping to reach the detect voltage (V DF ) ( > V DF ), the output voltage (V OUT ) keeps the High level (= ). Note that high impedance exists at V OUT with the N-channel open drain configuration. If the pin is pulled up, V OUT will be equal to the pull up voltage. 2. When falls below V DF, V OUT will be equal to the ground voltage (V SS ) level (detect state). Note that this also applies to N-channel open drain configurations. 3. When falls to a level below that of the minimum operating voltage (V MIN ) output will become unstable. 4. When rises above the V SS level (excepting levels lower than minimum operating voltage), V OUT will be equal to V SS until reaches the V DR level. 5. Although will rise to a level higher than V DR, V OUT maintains ground voltage level via the delay circuit. 6. Following transient delay time, will be output at V OUT. Note that high impedance exists with the N-channel open drain configuration and that voltage will be dependent on pull up. 7. The difference between V DR and V DF represents the hysteresis range. Notes: 1. Propagation delay time (T DLY ) represents the time it takes for to appear at V OUT once the said voltage has exceeded the V DR level. Timing Chart (Output Active Low ) 7

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11 PACKAGE OUTLINE DIMENSIONS Note : Information provided by IAT is believed to be accurate and reliable. However, we cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in an IAT product; nor for any infringement of patents or other rights of third parties that may result from its use. We reserve the right to change the circuitry and specifications without notice. Life Support Policy: IAT does not authorize any IAT product for use in life support devices and/or systems. Life support devices or systems are devices or systems which, (I) are intended for surgical implant into the body or (II) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. Typical numbers are at 25 C and represent the most likely norm. 11