High Performance Mixed Signal Circuits Enabled by the Direct Monolithic Heterogeneous Integration of InP HBT and Si CMOS on a Silicon Substrate
|
|
- Suzan Phelps
- 5 years ago
- Views:
Transcription
1 High Performance Mixed Signal Circuits Enabled by the Direct Monolithic Heterogeneous Integration of InP HBT and Si CMOS on a Silicon Substrate The MIT Faculty has made this article openly available. Please share how this access benefits you. Your story matters. Citation Kazior, T. E., J. R. LaRoche, M. Urteaga, J. Bergman, M. J. Choe, K. J. Lee, T. Seong, et al. High Performance Mixed Signal Circuits Enabled by the Direct Monolithic Heterogeneous Integration of InP HBT and Si CMOS on a Silicon Substrate. In 2010 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS), Monterey, CA, USA, 3-6 October 2010, 1-4. Institute of Electrical and Electronics Engineers, Copyright 2010 IEEE. As Published Publisher Version Institute of Electrical and Electronics Engineers Final published version Accessed Sun Nov 11 05:54:40 EST 2018 Citable Link Terms of Use Detailed Terms Article is made available in accordance with the publisher's policy and may be subject to US copyright law. Please refer to the publisher's site for terms of use.
2 High Performance Mixed Signal Circuits Enabled by the Direct Monolithic Heterogeneous Integration of InP HBT and Si CMOS on a Silicon Substrate T. E. Kazior, J. R. LaRoche Raytheon Integrate Defense Systems Andover, MA, USA tkazior@raytheon.com D. Lubyshev, J. M. Fastenau, W. K. Liu IQE Inc. Bethlehem, Pennsylvania, USA M. T. Bulsara, E. A. Fitzgerald Department of Materials Science and Engineering Massachusetts Institute of Technology Cambridge, Massachusetts, USA M. Urteaga, J. Bergman, M. J. Choe, K. J. Lee, T. Seong, M. Seo, A. Yen Teledyne Scientific Company Thousand Oaks, California, USA D. Smith, D. Clark, R. Thompson Raytheon Systems Limited Glenrothes, Fife, United Kingdom C. Drazek, E. Guiot SOITEC Bernin, France Abstract In this work we present recent results on the direct heterogeneous integration of InP HBTs and Si CMOS on a silicon template wafer or SOLES (Silicon On Lattice Engineered Substrate). InP HBTs whose performance are comparable to HBTs on the native InP substrates have been repeatedly achieved. 100% heterogeneous interconnect yield has been achieved on daisy chain test structures with CMOS-InP HBT spacing (interconnect length) as small as 2.5um. In DARPA COSMOS Phase 1 we designed and fabricated a differential amplifier that met the program Go/NoGo metrics with first pass design success. As the COSMOS Phase 2 demonstration vehicle we designed and fabricated a low power dissipation, high resolution, 500MHz bandwidth digital-to-analog converter (DAC). Keywords- CMOS integrated circuits, Heterojunction bipolar transistors, Indium Phosphide, Monolithic integrated circuits, Silicon I. INTRODUCTION As silicon technology is scaled to shorter dimensions and higher frequency operation, silicon integrated circuits (ICs) are beginning to be used in applications traditionally served by III- V compound semiconductors (e.g., microwave/millimeterwave amplifiers, high-frequency mixed signal ICs and data converters). However, while silicon-based ICs clearly provide more cost-effective solutions and increased integration density, they exhibit significant performance limitations when compared to III-V based ICs. Because of the superior transport properties of III-V materials, III-V devices offer higher gain, efficiency, bandwidth and dynamic range/linearity, and lower noise characteristics and RF loss at relaxed geometries then silicon based devices. As a result the future of integrated circuits will include the integration of high performance III-V electronic and/or optoelectronic devices with standard Si CMOS. While traditional hybrid approaches, such as wire bonded or flip chip multi-chip assemblies (see Fig. 1, left), may provide short term solutions, the variability, losses and size of the interconnects and the limitation in the placement of III-V devices relative to CMOS transistors limit the performance, utility, size, and cost of these approaches. A more attractive approach is the direct integration of Si CMOS and III-V devices on a common silicon substrate (COmpound Semiconductor Material On Silicon - COSMOS) (Fig. 1, right). In this way circuit performance can be optimized by the strategic placement of high performance III-V devices adjacent to Si CMOS transistors and cells, and the devices and subcircuits can be interconnected using standard semiconductor on-wafer interconnect processes. TFN Si CMOS TFN III-V TFN Multilayer Substrate Today s Hybrid Technology ( chip and wire or flip chip with thin film networks or TFNs) Revolutionary Developments Enable System on a Chip Si multilayer interconnect Si CMOS III-V Si CMOS Si Substrate III-V CMOS Integration III-V devices embedded in a Si wafer using III-V templates and standard Si multilayer interconnects and processing Figure 1. Traditional hybrid assembly (left) and direct monolithic integration of III-V devices and silicon CMOS (right). This work is supported by the DARPA COSMOS Program (Contract Number N C-0629 monitored by Dr. Harry Dietrich) /10/$ IEEE
3 In this paper recent progress on the direct heterogeneous integration of InP HBTs and Si CMOS on a silicon substrate are presented. The process is analogous to the SiGe BiCMOS and is essentially a III-V BiCMOS process. As the COSMOS Phase 1 demonstration vehicle, a high-speed, low-powerdissipation differential amplifier, which serves as the basic building block for high-performance mixed-signal circuits such as ADCs and DACs, was designed and fabricated. In COSMOS Phase 2, the technology is being used to design and fabricate a low power dissipation (1.6W), high resolution (13 bit, > 78 db spur free dynamic range (SFDR)), 500MHz bandwidth digital-to-analog converter (DAC). II. RESULTS AND DISCUSSION Our direct integration approach is based on a unique engineered silicon substrate which is similar to a standard SOI wafer. The SOLES (Silicon-on-Lattice Engineered Substrate), invented at MIT [1,2] and manufactured by SOITEC using their Smart-Cut TM Process [3,4], contains a buried III-V template layer that enables the direct growth of high quality III-V epitaxial material in windows directly on the silicon substrate (Fig. 2). At present the buried III-V template layer is Ge, although the substrate fabrication process is compatible with GaAs or InP template layers as well. SOLES have been successfully scaled to 200mm diameter wafers and are compatible with and can be readily inserted into a standard silicon CMOS foundry. Si nmos Si pmos comparable to HBTs grown directly on native InP substrates [6]. Figure 4 shows the small signal parameters of a 0.5 x 5 um 2 emitter HBT grown in a 15 x 15 um 2 window on a SOLES substrate. Gain (beta), f t and f max of 40, > 200GHz and > 200GHz, respectively, are achieved. HBT CMOS HBT CMOS Figure 3. SEM Image of InP HBT adjacent to Si CMOS on SOLES f t = 224 GHz f max = 219 GHz A E = 0.5x5 μm 2 I C = 7.8 ma V CE = 1.5V 5μm III-V device Compound Semiconductor (CS) Template Layer layer Silicon Figure 2. Left: Schematic Cross Section of COSMOS technology showing silicon CMOS and III-V transistors on a silicon template wafers (SOLES) While our main efforts have focused on the fabrication of InP HBTs on SOLES, the approach is equally applicable to other III-V electronic (FETs, HEMTs) and opto-electronic (photodiodes, VSCLS) devices. The process flow is similar to a SiGe BiCMOS process flow: 1) Si CMOS device fabrication; 2) HBT epitaxial growth and device fabrication; 3) multilayer interconnect fabrication. In our approach, after the completion of CMOS device fabrication, windows are lithography defined and etched into the SOLES wafer to reveal the III-V template layer. Since the III-V growth windows are defined as part of the CMOS fabrication process, the III-V epitaxial material can be grown selectively and arbitrarily across the substrate as required for the particular circuit or applications. Figure 3 shows an example of a SEM image of a completed InP HBT in close proximity to a CMOS transistor prior to interconnect formation. A detailed report on the growth of high quality InP HBT epitaxial material in windows on SOLES has been previously published [5]. The electrical performance of InP HBTs fabricated on SOLES is SOLES wafer Figure 4. Measured small signal RF characteristics of a 0.5x5 um 2 InP-HBT on SOLES substrate To facilitate the interconnecting of the III-V devices and CMOS transistors, the thickness of the III-V epitaxial layers and depth of the windows are optimized such that the III-V devices and CMOS transistors are planar. With this truly planar approach, 100% heterogeneous interconnect yield has been achieved on daisy chain test structures with CMOS-InP HBT spacing (interconnect length) as small as 2.5um (Fig. 5). 7.6um 4.5um < 2.5µm HBT Coll Metal CMOS Metal Figure 5. Optical and SEM image of a heterogeneous interconnect test structure containing 360 interconnects Initial circuit demonstrations were based on 1.2um CMOS and 2um emitter InP HBTs on 100mm diameter SOLES wafers. To facilitate circuit design, a design kit (consisting of CMOS, HBT and Interconnect models, design rules, DRC and LVS) was created and used to design the differential amplifier circuit shown in Figure 6 (COSMOS Phase 1 demonstration circuit). In addition to the core differential amplifier, the
4 Core Diff Amp Output Buffer pmos InP HBT nmos pmos version of the DAC has recently been designed and is being fabricated. The new DAC design contains both on-chip static and dynamic calibration circuitry in the same footprint as the 1.2um CMOS version of the DAC. DAC Error Measurement Calibration DAC Clock Driver circuit contains a bias circuit and all HBT output buffer. (The role of the output buffer is to attenuate the output of the core differential amplifier to facilitate the characterization of the differential amplifier.) Because of our truly monolithically integrated, planar approach we were able to include multiple differential amplifier design variants within a reticle on a wafer, effectively creating a design optimization design of experiments (DOE) within the reticle. 4-port S-parameter measurements were made to determine the low frequency amplifier gain and unity-gain bandwidth of the differential amplifier. The differential amplifier core was biased at a Vss= 6V and Iss=14mA (Pdiss=84mW). Typical differential amplifiers exhibited a peak low frequency gain of 550V/V, a unity-gain frequency of 20 GHz, a voltage swing of 7.5V and a measured slew rate a measured slew rate of 1.25x104 V-usec From the DC-gain measurement, the DC-gain*unity gain bandwidth product is measured to be 1.1x104 V/V GHz. The differential amplifiers exceeded the DARPA COSMOS Phase 1 performance metrics with first pass design success. Differential amplifiers step and repeated across a 100mm diameter SOLES wafer showed very good yield and uniformity highlighting the manufacturability of our approach. Details on the differential amplifier have been previously reported [7, 8]. DAC Core Logic for Calibration Figure 7. Layout of a compact, low power dissipation (1.6W), high resolution (13 bit, > 78 db spur free dynamic range (SFDR)), 500MHz bandwidth digital-to-analog converter (DAC) designed using COSMOS technology. The DAC contains on chip calibration circuitry and consists of > 1100 InP HBTs and >14,000 silicon NMOS and PMOS transistors. Total chip area is < 12mm2. The DAC is the DARPA COSMOS Phase 2 demonstration circuit. InP HBT Figure 6. Optical image of core differential amplifer with output buffer and bias circuit. As the COSMOS Phase 2 demonstration vehicle, we designed a low power dissipation (1.6W), high resolution (13 bit, > 78 db spur free dynamic range (SFDR)), 500MHz bandwidth digital-to-analog converter (DAC) (Fig. 7). The DAC uses a return to zero (RZ), current steering (CurrentSource-Switch or CSS) architecture and contains on-chip static calibration circuitry. The simulated performance of the DAC is shown in Figure 8. The DAC uses 1.2 um CMOS and contains over 14,000 silicon CMOS transistors heterogeneously integrated with over 1100 InP HBTs. The DAC is currently being fabricated. More details on the DAC design and performance will be presented in a later work. With the successful scaling of SOLES to 200mm diameter wafers, we have scaled our monolithic integration approach to more cutting edge CMOS technology and the design kit has been updated to include 180nm CMOS. A 180 nm CMOS 1st Nyquist 2nd Nyquist Figure 8. Simulated performance of the DAC shown in Fig. 7 clocked at 1.35GHz. Performance at both 1st and 2nd Nyquist are shown. III. SUMMARY In this work we presented an overview of the Raytheon approach to the direct monolithic integration of III-V devices (InP HBTs) and Si CMOS on a common silicon substrate
5 (SOLES). The COSMOS Phase 2 DAC is a building block for other types of high speed, high dynamic range, low power dissipation converter circuits including Analog Digital Converters (ADCs) and Direct Digital Synthesizers (DDSs). The next step is to integrate these mixed signal converter circuits with RF transistors (HEMTs and HBTs) to enable single chip Digital Transceivers and Dynamically Reconfigurable Circuits as well as compact circuit elements for Low Cost Panel Arrays. ACKNOWLEDGMENT The authors would also like to thank Drs. Mark Rosker and Sanjay Raman of DARPA. REFERENCES [1] C. L. Dohrman, K. Chilukuri, D. M. Isaacson, M. L. Lee, E.A Fitzgerald, Fabrication of silicon on lattice-engineered substrate (SOLES) as a platform for monolithic integration of CMOS and optoelectronic devices Materials Science and Engineering B, 135, pp , 2006 [2] K. Chilukuri, M. J. Mori, C. L. Dohrman and, E. A. Fitzgerald, Monolithic CMOS-compatible AlGaInP visibile LED arrays on silicon on lattice-engineered substrates (SOLES) Semicond. Sci. Tech. 22, pp 29-34, 2007 [3] C. Maleville and C. Mazuré, Smart Cut technology: From 300 mm ultrathin SOI production to advanced engineered substrates. Solid State Electron. 48, pp , 2004 [4] Smart-Cut is a registered trademark of Soitec. [5] W. K. Liu, D. Lubyshev, J. M. Fastenau, Y. Wu, M. T. Bulsara, E. A. Fitzgerald, M. Urteaga, W. Ha, J. Bergman, B. Brar, W. E. Hoke, J. R. LaRoche, K. J. Herrick, T. E. Kazior, D. Clark, D. Smith, R. F. Thompson, C. Drazek, and N. Daval, Monolithic Integration of InP-based Transistors on Si substrates using MBE Journal of Crystal Growth Volume 311, Issue 7:, pp , 2009 [6] W. Ha, M. Urteaga, J. Bergman, B. Brar, W. K. Liu, D. Lubyshev, J. M. Fastenau, Y. Wu, M. T. Bulsara, E. A. Fitzgerald, W. E. Hoke, J. R. LaRoche, K. J. Herrick, T. E. Kazior, D. Clark, D. Smith, R. F. Thompson, C. Drazek, and N. Daval, Small-area InP DHBTs grown on patterned lattice-engineered silicon substrates 66 th Device Research Conference, Santa Barbara, CA, Jun 23 25, 2008 (IV.B-9). [7] T.E. Kazior, J.R. LaRoche, D. Lubyshev, J. M. Fastenau, W. K. Liu, M. Urteaga, W. Ha, J. Bergman, M. J. Choe, M. T. Bulsara, E. A. Fitzgeral4, D. Smith, D. Clark, R. Thompson, C. Drazek, N. Daval, L. Benaissa and E. Augendre, A high performance differential amplifier through the direct monolithic integration of InP HBTs and Si CMOS on silicon substrates, Microwave Symposium Digest, MTT '09. IEEE MTT-S International Microwave Symposium. pp , June 2009 [8] T.E. Kazior, J.R. LaRoche, D. Lubyshev, J. M. Fastenau, W. K. Liu, M. Urteaga, W. Ha, J. Bergman, M. J. Choe, M. T. Bulsara, E. A. Fitzgerald, D. Smith, D. Clark, R. Thompson, C. Drazek, N. Daval, L. Benaissa and E. Augendre, Progress and challenges in the direct monolithic integration of III V devices and Si CMOS on silicon substrates, IPRM '09. IEEE International Conference on Indium Phosphide and Related Materials Digest: pp , May 2009
A high performance differential amplifier through the direct monolithic integration of InP HBTs and Si CMOS on silicon substrates
A high performance differential amplifier through the direct monolithic integration of InP HBTs and Si CMOS on silicon substrates The MIT Faculty has made this article openly available. Please share how
More informationProgress and challenges in the direct monolithic integration of III-V devices and Si CMOS on silicon substrates
Progress and challenges in the direct monolithic integration of III-V devices and Si CMOS on silicon substrates The MIT Faculty has made this article openly available. Please share how this access benefits
More informationOn-Wafer Integration of Nitrides and Si Devices: Bringing the Power of Polarization to Si
On-Wafer Integration of Nitrides and Si Devices: Bringing the Power of Polarization to Si The MIT Faculty has made this article openly available. Please share how this access benefits you. Your story matters.
More informationWafer Scale Integration of III-Vs (GaN) with Si CMOS for RF Applications
Wafer Scale Integration of III-Vs (GaN) with Si CMOS for RF Applications Some of this data was developed pursuant to Contracts Number N00014-13-C-0231 with the US Government. The US Government s rights
More informationOn-wafer seamless integration of GaN and Si (100) electronics
On-wafer seamless integration of GaN and Si (100) electronics The MIT Faculty has made this article openly available. Please share how this access benefits you. Your story matters. Citation As Published
More informationWafer-scale 3D integration of silicon-on-insulator RF amplifiers
Wafer-scale integration of silicon-on-insulator RF amplifiers The MIT Faculty has made this article openly available. Please share how this access benefits you. Your story matters. Citation As Published
More informationWafer-scale 3D integration of InGaAs image sensors with Si readout circuits
Wafer-scale 3D integration of InGaAs image sensors with Si readout circuits The MIT Faculty has made this article openly available. Please share how this access benefits you. Your story matters. Citation
More informationInnovative ultra-broadband ubiquitous Wireless communications through terahertz transceivers ibrow
Project Overview Innovative ultra-broadband ubiquitous Wireless communications through terahertz transceivers ibrow Mar-2017 Presentation outline Project key facts Motivation Project objectives Project
More information30% PAE W-band InP Power Amplifiers using Sub-quarter-wavelength Baluns for Series-connected Power-combining
2013 IEEE Compound Semiconductor IC Symposium, October 13-15, Monterey, C 30% PAE W-band InP Power Amplifiers using Sub-quarter-wavelength Baluns for Series-connected Power-combining 1 H.C. Park, 1 S.
More informationTU3B-1. An 81 GHz, 470 mw, 1.1 mm 2 InP HBT Power Amplifier with 4:1 Series Power Combining using Sub-quarter-wavelength Baluns
TU3B-1 Student Paper Finalist An 81 GHz, 470 mw, 1.1 mm 2 InP HBT Power Amplifier with 4:1 Series Power Combining using Sub-quarter-wavelength Baluns H. Park 1, S. Daneshgar 1, J. C. Rode 1, Z. Griffith
More informationIndium Phosphide and Related Materials Selectively implanted subcollector DHBTs
Indium Phosphide and Related Materials - 2006 Selectively implanted subcollector DHBTs Navin Parthasarathy, Z. Griffith, C. Kadow, U. Singisetti, and M.J.W. Rodwell Dept. of Electrical and Computer Engineering,
More informationA Miniaturized Multi-Channel TR Module Design Based on Silicon Substrate
Progress In Electromagnetics Research Letters, Vol. 74, 117 123, 2018 A Miniaturized Multi-Channel TR Module Design Based on Silicon Substrate Jun Zhou 1, 2, *, Jiapeng Yang 1, Donglei Zhao 1, and Dongsheng
More informationA 3-Stage Shunt-Feedback Op-Amp having 19.2dB Gain, 54.1dBm OIP3 (2GHz), and 252 OIP3/P DC Ratio
International Microwave Symposium 2011 Chart 1 A 3-Stage Shunt-Feedback Op-Amp having 19.2dB Gain, 54.1dBm OIP3 (2GHz), and 252 OIP3/P DC Ratio Zach Griffith, M. Urteaga, R. Pierson, P. Rowell, M. Rodwell,
More informationProject Overview. Innovative ultra-broadband ubiquitous Wireless communications through terahertz transceivers ibrow
Project Overview Innovative ultra-broadband ubiquitous Wireless communications through terahertz transceivers ibrow Presentation outline Key facts Consortium Motivation Project objective Project description
More informationA Bandgap Voltage Reference Circuit Design In 0.18um Cmos Process
A Bandgap Voltage Reference Circuit Design In 0.18um Cmos Process It consists of a threshold voltage extractor circuit and a proportional to The behavior of the circuit is analytically described, a design
More informationLecture: Integration of silicon photonics with electronics. Prepared by Jean-Marc FEDELI CEA-LETI
Lecture: Integration of silicon photonics with electronics Prepared by Jean-Marc FEDELI CEA-LETI Context The goal is to give optical functionalities to electronics integrated circuit (EIC) The objectives
More informationHigh-Frequency Transistors High-Frequency ICs. Technologies & Applications
High-Frequency Transistors High-Frequency ICs Technologies & Applications Mark Rodwell University of California, Santa Barbara rodwell@ece.ucsb.edu 805-893-3244, 805-893-2362 fax Report Documentation Page
More informationISSCC 2006 / SESSION 17 / RFID AND RF DIRECTIONS / 17.4
17.4 A 6GHz CMOS VCO Using On-Chip Resonator with Embedded Artificial Dielectric for Size, Loss and Noise Reduction Daquan Huang, William Hant, Ning-Yi Wang, Tai W. Ku, Qun Gu, Raymond Wong, Mau-Chung
More informationDesign of THz Signal Generation Circuits Using 65nm CMOS Technologies
Design of THz Signal Generation Circuits Using 65nm CMOS Technologies Hyeong-Jin Kim, Wonseok Choe, and Jinho Jeong Department of Electronics Engineering, Sogang University E-mail: jjeong@sogang.ac.kr
More informationQuantum-effect Resonant Tunneling Device Technology for Practical Ultra Low-power High-speed Applications
Quantum-effect Resonant Tunneling Device Technology for Practical Ultra Low-power High-speed Applications SEMATECH Symposium October 23 rd, 2012 Prof. Kyounghoon Yang High Speed Nanoelectronics Laboratory
More informationSATURNE Microsystems Based on Wide Band Gap Materials for Future Space Transmitting Ultra Wideband Receiving Systems
SATURNE Microsystems Based on Wide Band Gap Materials for Future Space Transmitting Ultra Wideband Receiving Systems A. ZIAEI THALES Research & Technology Research & Technology www.saturne-project.com
More informationFull H-band Waveguide-to-Coupled Microstrip Transition Using Dipole Antenna with Directors
IEICE Electronics Express, Vol.* No.*,*-* Full H-band Waveguide-to-Coupled Microstrip Transition Using Dipole Antenna with Directors Wonseok Choe, Jungsik Kim, and Jinho Jeong a) Department of Electronic
More informationHow material engineering contributes to delivering innovation in the hyper connected world
How material engineering contributes to delivering innovation in the hyper connected world Paul BOUDRE, Soitec CEO Leti Innovation Days - July 2018 Grenoble, France We live in a world of data In perpetual
More information4.1.2 InAs nanowire circuits fabricated by field-assisted selfassembly on a host substrate
22 Annual Report 2010 - Solid-State Electronics Department 4.1.2 InAs nanowire circuits fabricated by field-assisted selfassembly on a host substrate Student Scientist in collaboration with R. Richter
More informationProduct Catalog. Semiconductor Intellectual Property & Technology Licensing Program
Product Catalog Semiconductor Intellectual Property & Technology Licensing Program MANUFACTURING PROCESS TECHNOLOGY OVERVIEW 90 nm 130 nm 0.18 µm 0.25 µm 0.35 µm >0.40 µm Logic CMOS SOI CMOS SOI CMOS SOI
More informationInP AND GaAs COMPONENTS FOR 40 Gbps APPLICATIONS
InP AND GaAs COMPONENTS FOR 40 Gbps APPLICATIONS M. Siddiqui, G. Chao, A. Oki, A. Gutierrez-Aitken, B. Allen, A. Chau, W. Beall, M. D Amore, B. Oyama, D. Hall, R Lai, and D. Streit Velocium, a TRW Company
More informationIEEE JOURNAL OF SELECTED TOPICS IN QUANTUM ELECTRONICS 2010 Silicon Photonic Circuits: On-CMOS Integration, Fiber Optical Coupling, and Packaging
IEEE JOURNAL OF SELECTED TOPICS IN QUANTUM ELECTRONICS 2010 Silicon Photonic Circuits: On-CMOS Integration, Fiber Optical Coupling, and Packaging Christophe Kopp, St ephane Bernab e, Badhise Ben Bakir,
More informationCMOS Digital Integrated Circuits Lec 2 Fabrication of MOSFETs
CMOS Digital Integrated Circuits Lec 2 Fabrication of MOSFETs 1 CMOS Digital Integrated Circuits 3 rd Edition Categories of Materials Materials can be categorized into three main groups regarding their
More information65-GHz Receiver in SiGe BiCMOS Using Monolithic Inductors and Transformers
65-GHz Receiver in SiGe BiCMOS Using Monolithic Inductors and Transformers Michael Gordon, Terry Yao, Sorin P. Voinigescu University of Toronto March 10 2006, UBC, Vancouver Outline Motivation mm-wave
More informationIntegration of Optoelectronic and RF Devices for Applications in Optical Interconnect and Wireless Communication
Integration of Optoelectronic and RF Devices for Applications in Optical Interconnect and Wireless Communication Zhaoran (Rena) Huang Assistant Professor Department of Electrical, Computer and System Engineering
More informationSi Photonics Technology Platform for High Speed Optical Interconnect. Peter De Dobbelaere 9/17/2012
Si Photonics Technology Platform for High Speed Optical Interconnect Peter De Dobbelaere 9/17/2012 ECOC 2012 - Luxtera Proprietary www.luxtera.com Overview Luxtera: Introduction Silicon Photonics: Introduction
More informationHigh Voltage Operational Amplifiers in SOI Technology
High Voltage Operational Amplifiers in SOI Technology Kishore Penmetsa, Kenneth V. Noren, Herbert L. Hess and Kevin M. Buck Department of Electrical Engineering, University of Idaho Abstract This paper
More informationRF Integrated Circuits
Introduction and Motivation RF Integrated Circuits The recent explosion in the radio frequency (RF) and wireless market has caught the semiconductor industry by surprise. The increasing demand for affordable
More informationUpdates on THz Amplifiers and Transceiver Architecture
Updates on THz Amplifiers and Transceiver Architecture Sanggeun Jeon, Young-Chai Ko, Moonil Kim, Jae-Sung Rieh, Jun Heo, Sangheon Pack, and Chulhee Kang School of Electrical Engineering Korea University
More information5G Systems and Packaging Opportunities
5G Systems and Packaging Opportunities Rick Sturdivant, Ph.D. Founder and Chief Technology Officer MPT, Inc. (www.mptcorp.com), ricksturdivant@gmail.com Abstract 5G systems are being developed to meet
More informationTechnology Overview. MM-Wave SiGe IC Design
Sheet Code RFi0606 Technology Overview MM-Wave SiGe IC Design Increasing consumer demand for high data-rate wireless applications has resulted in development activity to exploit the mm-wave frequency range
More informationFrequency Limits of Bipolar Integrated Circuits
IEEE MTT-S Symposium, June 13, 2006 Frequency Limits of Bipolar Integrated Circuits Mark Rodwell University of California, Santa Barbara Collaborators Z. Griffith, E. Lind, V. Paidi, N. Parthasarathy,
More informationSOI technology platforms for 5G: Opportunities of collaboration
SOI technology platforms for 5G: Opportunities of collaboration Dr. Ionut RADU Director, R&D SOITEC MOS AK workshop, Silicon Valley December 6th, 2017 Sourcing value from substrate Robert E. White ISBN-13:
More informationSingle-stage G-band HBT Amplifier with 6.3 db Gain at 175 GHz
Single-stage G-band HBT Amplifier with 6.3 db Gain at 175 GHz M. Urteaga, D. Scott, T. Mathew, S. Krishnan, Y. Wei, M.J.W. Rodwell Department of Electrical and Computer Engineering, University of California,
More information1 FUNDAMENTAL CONCEPTS What is Noise Coupling 1
Contents 1 FUNDAMENTAL CONCEPTS 1 1.1 What is Noise Coupling 1 1.2 Resistance 3 1.2.1 Resistivity and Resistance 3 1.2.2 Wire Resistance 4 1.2.3 Sheet Resistance 5 1.2.4 Skin Effect 6 1.2.5 Resistance
More information100+ GHz Transistor Electronics: Present and Projected Capabilities
21 IEEE International Topical Meeting on Microwave Photonics, October 5-6, 21, Montreal 1+ GHz Transistor Electronics: Present and Projected Capabilities Mark Rodwell University of California, Santa Barbara
More informationIndex. Cambridge University Press Silicon Photonics Design Lukas Chrostowski and Michael Hochberg. Index.
absorption, 69 active tuning, 234 alignment, 394 396 apodization, 164 applications, 7 automated optical probe station, 389 397 avalanche detector, 268 back reflection, 164 band structures, 30 bandwidth
More informationMicrowave Office Application Note
Microwave Office Application Note INTRODUCTION Wireless system components, including gallium arsenide (GaAs) pseudomorphic high-electron-mobility transistor (phemt) frequency doublers, quadruplers, and
More informationTransmission-Line-Based, Shared-Media On-Chip. Interconnects for Multi-Core Processors
Design for MOSIS Educational Program (Research) Transmission-Line-Based, Shared-Media On-Chip Interconnects for Multi-Core Processors Prepared by: Professor Hui Wu, Jianyun Hu, Berkehan Ciftcioglu, Jie
More informationCalifornia Eastern Laboratories
California Eastern Laboratories 750MHz Power Doubler and Push-Pull CATV Hybrid Modules Using Gallium Arsenide D. McNamara*, Y. Fukasawa**, Y. Wakabayashi**, Y. Shirakawa**, Y. Kakuta** *California Eastern
More information22. VLSI in Communications
22. VLSI in Communications State-of-the-art RF Design, Communications and DSP Algorithms Design VLSI Design Isolated goals results in: - higher implementation costs - long transition time between system
More informationA 24 GHz integrated SiGe BiCMOS vital signs detection radar front-end
Downloaded from orbit.dtu.dk on: Apr 28, 2018 A 24 GHz integrated SiGe BiCMOS vital signs detection radar front-end Jensen, Brian Sveistrup; Johansen, Tom Keinicke; Zhurbenko, Vitaliy Published in: 2013
More informationSilicon-on-Sapphire Technology: A Competitive Alternative for RF Systems
71 Silicon-on-Sapphire Technology: A Competitive Alternative for RF Systems Isaac Lagnado and Paul R. de la Houssaye SSC San Diego S. J. Koester, R. Hammond, J. O. Chu, J. A. Ott, P. M. Mooney, L. Perraud,
More informationA 16-GHz Ultra-High-Speed Si SiGe HBT Comparator
1584 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO. 9, SEPTEMBER 2003 A 16-GHz Ultra-High-Speed Si SiGe HBT Comparator Jonathan C. Jensen, Student Member, IEEE, and Lawrence E. Larson, Fellow, IEEE
More informationTransistor was first invented by William.B.Shockley, Walter Brattain and John Bardeen of Bell Labratories. In 1961, first IC was introduced.
Unit 1 Basic MOS Technology Transistor was first invented by William.B.Shockley, Walter Brattain and John Bardeen of Bell Labratories. In 1961, first IC was introduced. Levels of Integration:- i) SSI:-
More informationLecture 1, Introduction and Background
EE 338L CMOS Analog Integrated Circuit Design Lecture 1, Introduction and Background With the advances of VLSI (very large scale integration) technology, digital signal processing is proliferating and
More informationon-chip Design for LAr Front-end Readout
Silicon-on on-sapphire (SOS) Technology and the Link-on on-chip Design for LAr Front-end Readout Ping Gui, Jingbo Ye, Ryszard Stroynowski Department of Electrical Engineering Physics Department Southern
More informationPackaged mm-wave GaN, GaAs and Si ICs for 5G and automotive radar
Packaged mm-wave GaN, GaAs and Si ICs for 5G and automotive radar Eric Leclerc UMS 1 st Nov 2018 Outline Why heterogenous integration? About UMS Technology portfolio Design tooling: Cadence / GoldenGate
More informationA 30-GS/sec Track and Hold Amplifier in 0.13-µm CMOS Technology Shahriar Shahramian Sorin P. Voinigescu Anthony Chan Carusone
A 30-GS/sec Track and Hold Amplifier in 0.13-µm CMOS Technology Shahriar Shahramian Sorin P. Voinigescu Anthony Chan Carusone Department of Electrical & Computer Eng. University of Toronto Canada Introduction
More informationCommercial Viability of a Merged HBT-FET (BiFET) Technology for GaAs Power Amplifiers
Commercial Viability of a Merged HT-FET (ifet) Technology for GaAs Power Amplifiers Ravi Ramanathan, Mike Sun, Peter J. Zampardi, Andre G. Metzger, Vincent Ho, Cejun Wei, Peter Tran, Hongxiao Shao, Nick
More informationAn Inductor-Based 52-GHz 0.18 µm SiGe HBT Cascode LNA with 22 db Gain
An Inductor-Based 52-GHz 0.18 µm SiGe HBT Cascode LNA with 22 db Gain Michael Gordon, Sorin P. Voinigescu University of Toronto Toronto, Ontario, Canada ESSCIRC 2004, Leuven, Belgium Outline Motivation
More informationInGaP HBT MMIC Development
InGaP HBT MMIC Development Andy Dearn, Liam Devlin; Plextek Ltd, Wing Yau, Owen Wu; Global Communication Semiconductors, Inc. Abstract InGaP HBT is being increasingly adopted as the technology of choice
More informationA 14-bit 2.5 GS/s DAC based on Multi-Clock Synchronization. Hegang Hou*, Zongmin Wang, Ying Kong, Xinmang Peng, Haitao Guan, Jinhao Wang, Yan Ren
Joint International Mechanical, Electronic and Information Technology Conference (JIMET 2015) A 14-bit 2.5 GS/s based on Multi-Clock Synchronization Hegang Hou*, Zongmin Wang, Ying Kong, Xinmang Peng,
More informationActive Technology for Communication Circuits
EECS 242: Active Technology for Communication Circuits UC Berkeley EECS 242 Copyright Prof. Ali M Niknejad Outline Comparison of technology choices for communication circuits Si npn, Si NMOS, SiGe HBT,
More informationATV 2011: Computer Engineering
ATV 2011: Technology Trends in Computer Engineering Professor Per Larsson-Edefors ATV 2011, L1, Per Larsson-Edefors Page 1 Solid-State Devices www.cse.chalmers.se/~perla/ugrad/ SemTech/Lectures_2000.pdf
More informationRECENT advances in the transistor technologies such as Si
440 IEEE TRANSACTIONS ON TERAHERTZ SCIENCE AND TECHNOLOGY, VOL. 7, NO. 4, JULY 2017 Submillimeter-Wave Waveguide-to-Microstrip Transitions for Wide Circuits/Wafers Jungsik Kim, Wonseok Choe, and Jinho
More information3D Integration Using Wafer-Level Packaging
3D Integration Using Wafer-Level Packaging July 21, 2008 Patty Chang-Chien MMIC Array Receivers & Spectrographs Workshop Pasadena, CA Agenda Wafer-Level Packaging Technology Overview IRAD development on
More informationMicrowave Office Application Note
Microwave Office Application Note INTRODUCTION Wireless system components, including gallium arsenide (GaAs) pseudomorphic high-electron-mobility transistor (phemt) frequency doublers, quadruplers, and
More informationOptical Phase-Locking and Wavelength Synthesis
2014 IEEE Compound Semiconductor Integrated Circuits Symposium, October 21-23, La Jolla, CA. Optical Phase-Locking and Wavelength Synthesis M.J.W. Rodwell, H.C. Park, M. Piels, M. Lu, A. Sivananthan, E.
More informationDesign of low phase noise InGaP/GaAs HBT-based differential Colpitts VCOs for interference cancellation system
Indian Journal of Engineering & Materials Sciences Vol. 17, February 2010, pp. 34-38 Design of low phase noise InGaP/GaAs HBT-based differential Colpitts VCOs for interference cancellation system Bhanu
More informationDevelopment of Low Cost Millimeter Wave MMIC
INFORMATION & COMMUNICATIONS Development of Low Cost Millimeter Wave MMIC Koji TSUKASHIMA*, Miki KUBOTA, Osamu BABA, Hideki TANGO, Atsushi YONAMINE, Tsuneo TOKUMITSU and Yuichi HASEGAWA This paper describes
More informationA 4 GSample/s 8-bit ADC in. Ken Poulton, Robert Neff, Art Muto, Wei Liu, Andrew Burstein*, Mehrdad Heshami* Agilent Laboratories Palo Alto, California
A 4 GSample/s 8-bit ADC in 0.35 µm CMOS Ken Poulton, Robert Neff, Art Muto, Wei Liu, Andrew Burstein*, Mehrdad Heshami* Agilent Laboratories Palo Alto, California 1 Outline Background Chip Architecture
More informationA 77 GHz mhemt MMIC Chip Set for Automotive Radar Systems
A 77 GHz mhemt MMIC Chip Set for Automotive Radar Systems Dong Min Kang, Ju Yeon Hong, Jae Yeob Shim, Jin-Hee Lee, Hyung-Sup Yoon, and Kyung Ho Lee A monolithic microwave integrated circuit (MMIC) chip
More informationCharacteristics of InP HEMT Harmonic Optoelectronic Mixers and Their Application to 60GHz Radio-on-Fiber Systems
. TU6D-1 Characteristics of Harmonic Optoelectronic Mixers and Their Application to 6GHz Radio-on-Fiber Systems Chang-Soon Choi 1, Hyo-Soon Kang 1, Dae-Hyun Kim 2, Kwang-Seok Seo 2 and Woo-Young Choi 1
More informationLow Thermal Resistance Flip-Chip Bonding of 850nm 2-D VCSEL Arrays Capable of 10 Gbit/s/ch Operation
Low Thermal Resistance Flip-Chip Bonding of 85nm -D VCSEL Arrays Capable of 1 Gbit/s/ch Operation Hendrik Roscher In 3, our well established technology of flip-chip mounted -D 85 nm backside-emitting VCSEL
More informationA Method for Yield and Scaling Characterization of FET Structures in an InGaP/GaAs Merged HBT-FET (BiFET) Technology
A Method for Yield and Scaling Characterization of FET Structures in an InGaP/GaAs Merged HBT-FET (BiFET) Technology Andre G. Metzger, Jiang Li, Jiro Yota, Mike Sun, Ravi Ramanathan, Cristian Cismaru Skyworks
More informationElectronic-Photonic ICs for Low Cost and Scalable Datacenter Solutions
Electronic-Photonic ICs for Low Cost and Scalable Datacenter Solutions Christoph Theiss, Director Packaging Christoph.Theiss@sicoya.com 1 SEMICON Europe 2016, October 27 2016 Sicoya Overview Spin-off from
More informationNEXT GENERATION SILICON PHOTONICS FOR COMPUTING AND COMMUNICATION PHILIPPE ABSIL
NEXT GENERATION SILICON PHOTONICS FOR COMPUTING AND COMMUNICATION PHILIPPE ABSIL OUTLINE Introduction Platform Overview Device Library Overview What s Next? Conclusion OUTLINE Introduction Platform Overview
More informationRF3375 GENERAL PURPOSE AMPLIFIER
Basestation Applications Broadband, Low-Noise Gain Blocks IF or RF Buffer Amplifiers Driver Stage for Power Amplifiers Final PA for Low-Power Applications High Reliability Applications RF3375General Purpose
More informationDESIGN AND PERFORMANCE VERIFICATION OF CURRENT CONVEYOR BASED PIPELINE A/D CONVERTER USING 180 NM TECHNOLOGY
DESIGN AND PERFORMANCE VERIFICATION OF CURRENT CONVEYOR BASED PIPELINE A/D CONVERTER USING 180 NM TECHNOLOGY Neha Bakawale Departmentof Electronics & Instrumentation Engineering, Shri G. S. Institute of
More informationGallium nitride (GaN)
80 Technology focus: GaN power electronics Vertical, CMOS and dual-gate approaches to gallium nitride power electronics US research company HRL Laboratories has published a number of papers concerning
More informationSynthesis of Optimal On-Chip Baluns
Synthesis of Optimal On-Chip Baluns Sharad Kapur, David E. Long and Robert C. Frye Integrand Software, Inc. Berkeley Heights, New Jersey Yu-Chia Chen, Ming-Hsiang Cho, Huai-Wen Chang, Jun-Hong Ou and Bigchoug
More informationMMA RECEIVERS: HFET AMPLIFIERS
MMA Project Book, Chapter 5 Section 4 MMA RECEIVERS: HFET AMPLIFIERS Marian Pospieszalski Ed Wollack John Webber Last revised 1999-04-09 Revision History: 1998-09-28: Added chapter number to section numbers.
More informationANALYSIS AND DESIGN OF ANALOG INTEGRATED CIRCUITS
ANALYSIS AND DESIGN OF ANALOG INTEGRATED CIRCUITS Fourth Edition PAUL R. GRAY University of California, Berkeley PAUL J. HURST University of California, Davis STEPHEN H. LEWIS University of California,
More informationMTO Technology Programs Progress. Frank Stroili Technical Director, RF/Mixed signal
MTO Technology Programs Progress Frank Stroili Technical Director, RF/Mixed signal 603-885-7487 frank.stroili@baesystems.com 1 Report Documentation Page Form Approved OMB No. 0704-0188 Public reporting
More informationThe Monolithic Radio Frequency Array & the Coming Revolution of Convergence
DARPATech, DARPA s 25 th Systems and Technology Symposium August 7, 2007 Anaheim, California Teleprompter Script for Dr. Mark Rosker, Program Manager, Microsystems Technology Office The Monolithic Radio
More informationEnvisioning the Future of Optoelectronic Interconnects:
Envisioning the Future of Optoelectronic Interconnects: The Production Economics of InP and Si Platforms for 100G Ethernet LAN Transceivers Shan Liu Dr. Erica Fuchs Prof. Randolph Kirchain MIT Microphotonics
More informationThe Past, Present, and Future of Silicon Photonics
The Past, Present, and Future of Silicon Photonics Myung-Jae Lee High-Speed Circuits & Systems Lab. Dept. of Electrical and Electronic Engineering Yonsei University Outline Introduction A glance at history
More informationITRS: RF and Analog/Mixed- Signal Technologies for Wireless Communications. Nick Krajewski CMPE /16/2005
ITRS: RF and Analog/Mixed- Signal Technologies for Wireless Communications Nick Krajewski CMPE 640 11/16/2005 Introduction 4 Working Groups within Wireless Analog and Mixed Signal (0.8 10 GHz) (Covered
More informationImprovement of Output Impedance Modulation Effect of High Speed DAC
nternational Conference on Artificial ntelligence and Engineering Applications (AEA 2016) mprovement of Output mpedance Modulation Effect of High Speed DAC Dongmei Zhu a, Xiaodan Zhou b, Jun Liu c, Luncai
More informationFully integrated CMOS transmitter design considerations
Semiconductor Technology Fully integrated CMOS transmitter design considerations Traditionally, multiple IC chips are needed to build transmitters (Tx) used in wireless communications. The difficulty with
More informationMatched wideband low-noise amplifiers for radio astronomy
REVIEW OF SCIENTIFIC INSTRUMENTS 80, 044702 2009 Matched wideband low-noise amplifiers for radio astronomy S. Weinreb, J. Bardin, H. Mani, and G. Jones Department of Electrical Engineering, California
More informationCHAPTER 2 POLARIZATION SPLITTER- ROTATOR BASED ON A DOUBLE- ETCHED DIRECTIONAL COUPLER
CHAPTER 2 POLARIZATION SPLITTER- ROTATOR BASED ON A DOUBLE- ETCHED DIRECTIONAL COUPLER As we discussed in chapter 1, silicon photonics has received much attention in the last decade. The main reason is
More informationMillimeter-wave CMOS Transceiver Techniques for Automotive Radar Systems
Millimeter-wave CMOS Transceiver Techniques for Automotive Radar Systems Yoichi Kawano Hiroshi Matsumura Ikuo Soga Yohei Yagishita Recently, advanced driver assistance systems (ADAS) with the keyword of
More informationRF2334. Typical Applications. Final PA for Low Power Applications Broadband Test Equipment
RF233 AMPLIFIER Typical Applications Broadband, Low Noise Gain Blocks IF or RF Buffer Amplifiers Driver Stage for Power Amplifiers Final PA for Low Power Applications Broadband Test Equipment Product Description
More informationProject: IEEE P Working Group for Wireless Personal Area Networks N
Slide 1 Project: IEEE P802.15 Working Group for Wireless Personal Area Networks N (WPANs( WPANs) Title: [RF Devices for Millimeter-Wave Applications ] Date Submitted: [10 November 2003] Source: [Kenichi
More informationMore specifically, I would like to talk about Gallium Nitride and related wide bandgap compound semiconductors.
Good morning everyone, I am Edgar Martinez, Program Manager for the Microsystems Technology Office. Today, it is my pleasure to dedicate the next few minutes talking to you about transformations in future
More informationCAD oriented study of Polyimide interface layer on Silicon substrate for RF applications
CAD oriented study of Polyimide interface layer on Silicon substrate for RF applications Kamaljeet Singh & K Nagachenchaiah Semiconductor Laboratory (SCL), SAS Nagar, Near Chandigarh, India-160071 kamaljs@sclchd.co.in,
More informationSimulation of High Resistivity (CMOS) Pixels
Simulation of High Resistivity (CMOS) Pixels Stefan Lauxtermann, Kadri Vural Sensor Creations Inc. AIDA-2020 CMOS Simulation Workshop May 13 th 2016 OUTLINE 1. Definition of High Resistivity Pixel Also
More informationLecture Wrap up. December 13, 2005
6.012 Microelectronic Devices and Circuits Fall 2005 Lecture 26 1 Lecture 26 6.012 Wrap up December 13, 2005 Contents: 1. 6.012 wrap up Announcements: Final exam TA review session: December 16, 7:30 9:30
More informationTHE RAPID growth of wireless communication using, for
472 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 53, NO. 2, FEBRUARY 2005 Millimeter-Wave CMOS Circuit Design Hisao Shigematsu, Member, IEEE, Tatsuya Hirose, Forrest Brewer, and Mark Rodwell,
More informationFoundries, MMICs, systems. Rüdiger Follmann
Foundries, MMICs, systems Rüdiger Follmann Content MMIC foundries Designs and trends Examples 2 Foundries and MMICs Feb-09 IMST GmbH - All rights reserved MMIC foundries Foundries IMST is a UMS certified
More informationFully integrated UHF RFID mobile reader with power amplifiers using System-in-Package (SiP)
Fully integrated UHF RFID mobile reader with power amplifiers using System-in-Package (SiP) Hyemin Yang 1, Jongmoon Kim 2, Franklin Bien 3, and Jongsoo Lee 1a) 1 School of Information and Communications,
More informationAdvances in Microwave & Millimeterwave Integrated Circuits
الراديو - جامعة Advances in Microwave & Millimeterwave Integrated Circuits الهندسة آلية عين شمس ١٥ مارس ٢٠٠٧-١٣ Amin K. Ezzeddine AMCOM Communications, Inc. 22300 Comsat Drive Clarksburg, Maryland 20871,
More informationDesign of a Folded Cascode Operational Amplifier in a 1.2 Micron Silicon-Carbide CMOS Process
University of Arkansas, Fayetteville ScholarWorks@UARK Electrical Engineering Undergraduate Honors Theses Electrical Engineering 5-2017 Design of a Folded Cascode Operational Amplifier in a 1.2 Micron
More information