Voltage Unbalance Compensation with Smart Three-phase Loads

Transcription

1 Voltage Unbalance Compensation with Smart Three-phase Loads Philip J. Douglass Danish Energy Association Vodroffsvej 59 9 Frederiksberg C Denmark pdo@danskenergi.dk Ionut Trintis and Stig Munk-Nielsen Department of Energy Technology Aalborg University Pontoppidanstræde 922 Aalborg Denmark itr@et.aau.dk and smn@et.aau.dk Abstract This paper describes the design, proof-of-concept simulations and laboratory test of an algorithm for controlling active front-end rectifiers to reduce voltage unbalance. Using inputs of RMS voltage, the rectifier controller allocates load unevenly on its 3 phases to compensate for voltage unbalance originating in the power supply network. Two variants of the algorithm are tested: first, using phase-neutral (P-N) voltage as input, second, using phase-phase (P-P) voltage. The control algorithm is described, and evaluated in simulations and laboratory tests. Two metrics for quantifying voltage unbalance are evaluated: one metric based on the maximum deviation of RMS P-N voltage from the average voltage and one metric based on negative sequence voltage. The tests show that controlling P-N voltage can in most cases eliminate the deviations of P-N voltage from the average voltage, but it does not reduce the negative sequence voltage. The controller that uses the P-P voltage as input eliminates the negative sequence voltage, and reduces P- N voltage deviations from the average to approximately half of their initial value. Current unbalance is reduced when the voltage unbalance is caused by asymmetrical loads, but it is increased in a scenario with unbalanced voltage sources. These results suggest that the optimal algorithm to reduce system unbalance depends on which system parameter is most important: RMS P-N voltage unbalance, negative sequence voltage, or current unbalance. I. INTRODUCTION Ideal three-phase power systems have identical voltage magnitudes, and exactly2 phase angle offsets, but practical power systems always show some degree of unbalance. In low voltage (LV) power distribution systems, voltage unbalance increases losses and reduces capacity to transfer energy. The reduction of transfer capacity can be caused by any one of three constraints: RMS voltage constraints, limits on the magnitude of negative sequence voltage, or ampacity constraints on the most loaded phase. Commonly in distribution systems, the most pressing constraint is RMS voltage, followed by ampacity constraints. Some of the unbalance observed in LV distribution systems is propagated from the transmission system, but much of the unbalance originates in the LV system itself from single-phase loads and single-phase distributed generators. Compensating for voltage unbalance close to its source is desirable to minimize the number of nodes affected. The composition of load affects the system s sensitivity to voltage unbalance []. When induction motors are exposed to voltage unbalance they draw significant negative sequence currents, and experience vibrations and overheating. For the system, the negative sequence current drawn by motors has the beneficial effect of reducing the voltage unbalance seen at other nodes in the power network. Constant power loads, such as many power electronic loads, can worsen voltage unbalance by drawing unbalanced currents that exacerbate voltage unbalance. Power system operators can compensate for voltage unbalance by installing active filters [2], but these devices have significant capital and operating costs, and commercially available products are not suited for LV power distribution systems. This paper describes a novel method for controlling small three-phase power electronic loads to act as active shunt filters to reduce a system s voltage unbalance. The controller uses only locally available measurements of RMS phase voltage; no external communication is required, nor phase angles measurements, nor upstream current measurements. The algorithm is designed to be implemented in an active front-end (AFE) rectifier, such as those found in variable speed drives. Variable speed drives are equipped with AFE rectifiers to achieve a high power factor, and they are increasingly common in heating, ventilation and air conditioning systems. The proposed algorithm can be implemented in a AFE with minor changes to the embedded control software, however if it is required to carry unbalanced current at full load, a cost will be incurred to overdimension the AFE. A prototype implementing the proposed algorithm has been built using offthe-shelf components and tested in a laboratory test bench. Previous work on controlling AFE rectifiers in unbalanced conditions has concentrated on controlling the rectifier to draw balanced current when given unbalanced voltages [3]. The proposed algorithm described in this paper intentionally draws unbalanced currents, with the goal of reducing the voltage unbalance in the system as a whole. In [4] a genetic algorithm is applied to search for optimal setpoints to reduce voltage unbalance using an active filter combined with a noncritical load. The proposed algorithm is different because it uses a computationally inexpensive proportional-integral (PI) control law, and can deliver power to critical loads. In [5], a PI controller for reducing voltage unbalance was

2 simulated in a voltage source inverter. The proposed algorithm differentiates between phase-phase (P-P) and phase-neutral (P- N) voltage, and applies the controller to power electronic loads instead of generators. Other related work [6] showed how autonomous loads can modulate their active power to reduce voltage variation over time in balanced power systems. Instead of shifting load in time, the proposed algorithm shifts load between phases of an unbalanced power system. The underlying heuristic is similar to [6]: low voltage is associated with high load, and reducing active power draw on the phase with lowest voltage, and increasing active power draw on the phase with the highest voltage will reduce the voltage unbalance. The remainder of this paper is organized as follows: First, metrics for quantifying voltage unbalance are defined, and the topology of the AFE rectifier is presented. Then, the algorithm is explained step by step, followed by simulation results showing the performance of the algorithm under a variety of scenarios. Section V describes the prototype hardware design and laboratory tests, and finally conclusions are drawn. II. MEASURING AND MITIGATING UNBALANCE IN LOW VOLTAGE POWER SYSTEMS Alternative metrics for quantifying system unbalance have been proposed in power quality standards [7]. The metric called voltage unbalance factor (VUF) is based on the ratio of negative sequence voltage (U 2 ) to positive sequence voltage (U ): VUF = U 2 U % () In the absence of zero sequence voltage, the VUF can be found using only RMS P-P voltage as input, with the formula [7]: 3 6β VUF = % (2) + 3 6β β = V AB 4 + V BC 4 + V AC 4 ( V AB 2 + V BC 2 + V AC 2 ) 2 (3) In Europe, distribution system operators are required to limit the VUF to 2 % [8]. An alternative definition of voltage unbalance, the phase voltage unbalance rate (PVUR) from [9] measures deviations of RMS P-N voltage magnitude from the average voltage: max. RMS P-N voltage deviation from ave. PVUR = % average RMS P-N voltage (4) For this paper, the phase current unbalance rate (PCUR) is also defined, which is defined like the PVUR, substituting current for voltage. A key difference between the VUF and PVUR is that the VUF is based on P-P voltages and accounts for variations in phase angles, while the PVUR is based on P-N voltages and only considers voltage magnitude. In LV distribution feeders Load C dc + V dc - A B C PWM Current Controller i a i b i c Weight A Weight B Weight C Passive LCL Filter v a (t) v b (t) v c (t) Unbalance Compensating Controller 4V Unbalanced Grid Figure : Schematic diagram of AFE rectifier with unbalance compensating controller feeding inputs to PWM current controller. whose capacity is limited by the allowable RMS P-N voltage (in Europe,.9 pu -. pu), the best measure of voltage unbalance is the PVUR []. When system planners analyze a power distribution system to ensure that P-N voltages are acceptable, the PVUR must be added to the voltage variation expected under ideal balanced conditions. In feeders with high penetration of single-phase (or two-phase) PV inverters, this extra voltage variation can be up to 5.5 % []. The algorithm described in the following section has been implemented in an AFE rectifier, whose schematic is shown in Fig.. The unbalance compensating controller output is 3 setpoints (Weight A, Weight B, Weight C ). A current controller has been developed [2] to use these setpoints to control the MOSFET switches using pulse width modulation. The voltage controller regulates the average DC-link voltage (V DC ), while drawing unbalanced currents. III. VOLTAGE UNBALANCE COMPENSATING LOAD CONTROL ALGORITHM The voltage unbalance compensating load controller (hereafter referred to as the controller) uses a simple PI control law to allocate load between the 3 phases. The input to the controller are the 3 RMS P-N or P-P voltages, the outputs are relative load weightings for each phase (Weight A, Weight B, Weight C ). In this section the P-N variant of the controller is described first, then the P-P variant of the controller is described. The P-N variant of the controller is shown in a flow chart in Fig. 2, and explained below: First, the controller is initialized (step ). In step 2, the RMS P-N voltage of the 3 phases (U A, U B, U C ) are found, and in step 3 the average voltage for all phases (U AVE ) is found. The normalized voltage for phases A and B (U A, U B ) is then found by dividing the P-N voltage by the average voltage, and then subtracting this quantity from the nominal value of (step 3a). The normalized voltage for phase C (U C ) is derived from phases A and B to ensure the sum of the normalized voltages is always 3. In step 4, the normalized voltages, which represent the error input to the proposed controller, are integrated using a simple forward Euler integrator with a gain ki. The final

3 () Initialize Integrators k A = k B = k C = (2) Measure Phase-Neutral RMS U [U A, U B, U C ] (3) Find average U U AVE = (U A +U B +U C ) 3 (3a) Normalize Unbalance U A = - U A U AVE U B = - U B U AVE U C = 3 - U A - U B (4) Integrate Unbalance k A = k A + U A ki k B = k B + U B ki k C = k C + U C ki (5) Redistribute Phase Weighting Weight A = k A + U A kp Weight B = k B + U B kp Weight C = k C + U C kp Figure 2: Flowchart of unbalance compensating algorithm. phase weighting found in step 5 is the sum of the integral component, and a proportional component. The proportional component is found by multiplying the normalized voltage by a proportional gain factor (kp). The loop iterates when the current controller acts on the phase weight setpoints. The current controller modifies the phase current, and these new current flows lead to new voltage values. New RMS voltage values are calculated for each full AC cycle, and algorithm loops around to step 2 every 2 ms. The P-P variant of the controller is similar, except U A,U B, U C are substituted with U A U AB = U A U B U B U BC = U B U C U C U CA = U C U A (5a) (5b) (5c) The weighting of phase A therefore depends on U AB, and so on. IV. SIMULATION MODEL AND RESULTS This section presents the results of the simulated load controller in the simple 2-bus network shown in Fig.3. The simulated network contains a grounded voltage source, a 4- wire line, an unbalanced passive load and a AFE rectifier running the control algorithm. The passive load is modeled Voltage Source Source Bus 4 4 Z Load Bus 4 I grid 3 Unbalanced Load Smart 3-phase Load I load Figure 3: Two bus test system. The line has 4 conductors: 3- phases and neutral. The unbalanced load also has 4 conductors, while the smart load only has 3 phases, and no neutral connection. as a constant impedance load, and the smart load consumes a constant DC current. Phases ABC of the line are symmetrical, and the neutral conductor is considered ideal, with zero impedance. An ideal neutral conductor simplifies the system by keeping the neutral-ground voltage at zero. Considering that the converter is only connected to 3-phases, it does not contribute current to the neutral conductor, and therefore the scope of this analysis excludes consideration of the neutral current, as well as neutral-ground voltage. The controller is simulated in a number of scenarios that are characterized by different configurations of the voltage source (i.e. balancedunbalanced), cable impedance Z (complex variables are indicated by bold text), and size of the smart load. The scenarios are simulated with both the P-N and P- P variants of the controller. The scenarios were evaluated by finding the VUF and PVUR at the load bus, and the PCUR across the cable that connects the voltage source to the load bus. In scenarios where the voltage source is unbalanced, only the voltage magnitude of the 3 phases differs; the simulated voltage source did not support changes to the phase angle offsets. The simulation tool PLECS [3] is used to simulate the system. PLECS simulates the system using a piecewise-linear model during semiconductor switching and a continuous-time model between switching events. The controller is implemented in PLECS using C code which was later downloaded to the AFE rectifier prototypes with minimal modification. One difference between the simulated rectifier and the prototype is the switching frequency of the PWM current controller. The prototype uses silicon carbide MOSFETs that can switch at 5 khz, while simulation was run using a 5 khz switching frequency for faster execution time. The impedance of the LCL filter was adapted in the simulation to get similar harmonic distortion as the prototypes. The controller in the simulation does not place any limits on the capacity of the smart load to carry unbalanced power; all power may be carried by one phase if desired, though the smart load only consumes active power, no active power is injected on any phase. The simulation is initialized in a steady-state, with the unbalance controller disabled. At time, the unbalance controller is enabled, and the simulation is run thereafter for 2 seconds ( cycles). The system parameters shown in Table I are the default

4 Property TABLE I: Default Parameter Values Value Voltage source U A = U B = U C pu = 23 V Load Impedance Z A (Nominal Power) Z B (Nominal Power) Z C (Nominal Power) DC Load Current (Nominal Power) Line Impedance Proportional Gain 3 + j54 Ω (4 kw) 53 + j28 Ω (. kw) 32 + j544 Ω (.4 kw) 8 A (6.7 kw) Z A = Z B = Z C.67 + j.57 Ω Z N Ω kp 3 AV - Integral Gain ki 6 AV - s - TABLE II: Simulation Results (all values in %) Initial Final (after 2 s) Scenario PVUR VUF PCUR PVUR VUF PCUR P-N Controller Base Shorter Line Shortest Line A Load A Load Low src. ub High src. ub P-P Controller Base Shorter Line Shortest Line A Load A Load Low src. ub High src. ub parameters used in all scenarios unless otherwise specified. These parameter values were chosen to reflect the network state observed at the end of a typical Danish LV feeder. A summary of all simulation scenarios is shown in Table II, each scenario is described in detail in the rest of this section. A. Unbalanced Passive Load In this scenario, the voltage unbalance is caused by the voltage drop in the line from unbalanced current feeding the passive load. Initially, when the smart load draws balanced current, the VUF is.8 %, the PVUR.36 % and the PCUR in I grid is 59 %. After the algorithm runs for 2 seconds, the RMS P-N voltages are almost identical, see Fig. 4, and the VUF is reduced to. %. The grid current PCUR unbalance is reduced to 34 %, it is not reduced further because the zero sequence current is not affected by the 3-phase AFE rectifier. B. Unbalanced Voltage Source In these scenarios, voltage unbalance at the load bus is caused by both the unbalanced passive load, and an unbalance from the voltage source. Two scenarios with unbalanced voltage source are tested: low source unbalance, and high RMS Phase Neutral Voltage in V Phase A Phase B Phase C Mean ABC Figure 4: Simulated RMS P-N voltage at load bus in scenario with unbalanced passive load. TABLE III: Unbalanced voltage source scenario parameters Property Low source unbalance Value U A.4 pu = 24 V Voltage source U B.5 pu = 242 V U C.3 pu = 238 V High source unbalance Voltage source U A U B U C.3 pu = 236 V.3 pu = 236 V.6 pu = 243 V source unbalance, see Table III for phase voltage magnitude values. Fig. 5.a shows that the controller with P-N voltage input is able to reduce PVUR, such that the PVUR approaches within 2 seconds. However, in the scenarios with unbalanced voltage sources, the PCUR does not monotonically decrease, as shown in Fig. 6. In the scenario with low source unbalance, the PCUR actually increases to be above the initial value. These simulations show that when the voltage unbalance is caused by an unbalanced voltage source, improving voltage unbalance may result in worsening the current unbalance. C. Varying Line Impedance These scenarios show the effect of different line impedances on the voltage unbalance. The default line impedance approximates a 3 m underground cable with two segments: first, 2 m of cable with a conductor cross-section of 5 mm 2, plus m of 5 mm 2 cable. This impedance is close to the upper limit of cables in use in LV distribution systems, therefore the controller is evaluated with two lower line impedance values, referred to as shorter line (Z ABC =.83 + j.28 Ω) and shortest line (Z ABC =.42 + j.4 Ω).

5 PVUR relative to initial value Base Shorter line Shortest line 4 A load 6 A load low src. unbal. high src. unbal. PCUR for Grid Current rel. to init. value (a) Simulated PVUR with P-N voltage response normalized to Figure 6: PCUR normalized to show the change relative to the initial unbalance. Legend is found in Fig. 5. VUF relative to initial value (b) Simulated VUF with P-N voltage response normalized to Figure 5: Normalized PVUR and VUF in simulations of the P-N controller variant. In general, lower line impedance caused the initial voltage unbalance to decrease (note that this is not apparent from Fig. 5 because the values are normalized to allow easier comparison across scenarios). The PI controller responded to a lower level of unbalance by more slowly reallocating load to the least loaded phase. In all cases the PVUR is decreased, but the PVUR decreases faster in the base case. In all scenarios, when the simulations are run for a longer time period, the voltage unbalance approaches zero. D. Varying DC Load Size These scenarios show the effect of the variations in the size of the DC load on the system performance. Scenarios were constructed where a larger (6 A) and a smaller DC (4 A) load are compared to the default load (8 A). There were small differences in the initial unbalance, but when the controller is activated, there are large differences in the PVUR of the response, shown in the aggregated results in Fig. 5.a. The larger load causes the voltage unbalance to decline faster than smaller load. This behavior is expected because the controller output is a relative phase weighting, and in the larger load, the current controller maps the relative weighting to more amperes of current. In the scenario with the smallest (4 A) load, phase A carries almost no current which shows that the controller is saturated, and the PVUR will not converge to zero in this case. E. Phase-to-Phase Voltage Control Section II introduced two metrics for voltage unbalance, PVUR and VUF. The analysis of the unbalance reducing controller with P-N inputs measured performance using PVUR, because that metric is also based on P-N voltage. In some situations, system operators may be more concerned with reducing the P-P voltage unbalance, in which case the VUF is the most appropriate performance metric. Fig. 5.b shows the VUF for all of the previously described scenarios that used P-N voltage as input to the controller; the VUF is normalized, so the initial VUF is. This figure shows that in the first iterations of the controller, the VUF is reduced, but before the VUF is completely removed, the VUF increases again. In Fig. 7.b, the relative change in VUF is shown for all scenarios using the P-P voltage as input to the controller. Using the P-P voltage as input results in monotonically decreasing

6 values of VUF, converging over time to zero. Fig. 7.a shows the PVUR for all scenarios with P-P voltage input. This result shows that the P-P variant of the controller decreases the PVUR by about half, but in no cases is the PVUR removed entirely. Thus a clear trade-off between removing the P-P voltage unbalance (as measured by VUF) and the P-N voltage unbalance (measured by PVUR) is revealed. The inputs to the proposed controller can be chosen to remove either the P-N unbalance or the P-P unbalance, but only the P-P variant of the controller reliably improves both P-N unbalance and P-P unbalance. V. LABORATORY TEST RESULTS The network shown in Fig. 3 was recreated in the laboratory, with a Chroma 65 Programmable AC Source emulating both the voltage source and line. Balanced voltage at p.u. was generated, and the emulated line had impedance Z ABC =.5 + j.75 Ω. The unbalanced passive load was created by two resistors connected from phase A (4 Ω) and phase B (8 Ω) to neutral. The DC load consumed 2.2 A (.9 kw), and the controller gains are: kp = 4 AV -, ki = 4 AV - s -. Both the P-N and P-P variants of the controller were tested. Voltage measurements are gathered by logging values within the prototype. Like in the PLECS simulations (in particular Fig. 4), the P-N controller eliminates the voltage unbalance, as shown in Fig. 8. The voltages converge over a longer time period than the simulation because of the lower controller gain values. The lab tests also confirm the relative advantages of the two controller variants. Fig. 9 shows that the P-N controller reduces the PVUR to zero, while the P-P controller reduces the PVUR by around 5 %. When measuring voltage unbalance with VUF, the P-N controller performs better initially, reaching a minimum after 6.5 s, but later as the PVUR declines, the VUF increases to a level only slightly lower that the initial unbalance. The P-P controller steadily improves both the VUF and PVUR, but only the VUF converges to zero. Both controllers show poorly damped oscillations in the voltage unbalance from around 2 s and afterwards. This indicates that the controller gains may benefit from tuning. VI. CONCLUSION AND FUTURE WORK This paper presented a novel control algorithm that allows 3-phase AFE rectifiers to reduce voltage unbalance. The algorithm is simple to implement, and operates autonomously, using only locally available RMS phase voltage as inputs. It outputs phase power weights to a PWM current controller. Two variants of the algorithm were described: one variant optimized to reduce deviations in RMS P-N voltage, and the other optimized to reduce negative sequence voltage. The simulations and laboratory experiments presented in this paper have shown that a trade-off exists when optimizing the controller: the variant of the controller using P-N voltage as input is effective at reducing deviations in RMS P-N voltage, but gives little improvement in the negative sequence voltage. The other variant of the controller, which uses P-P voltage as PVUR relative to initial value (a) Simulated PVUR with P-P voltage response normalized to VUF relative to initial value Base Shorter line Shortest line 4 A load 6 A load low src. unbal. high src. unbal (b) Simulated VUF with P-P voltage response normalized to Figure 7: Normalized PVUR and VUF in simulations of the P-P controller variant. input, can always reduce the negative sequence voltage, but is much less effective at reducing RMS P-N voltage deviations. Both controllers risk increasing the current unbalance of the system when exposed to an unbalanced voltage source. In future work, the prototype AFE rectifiers will be tested in a field trial in operating residential feeders. This field trial will test if the assumptions reflected in the design, and the simplifications reflected in the simulations and laboratory tests presented here accurately represent real field conditions.

7 RMS Phase Neutral Voltage in V Phase A Phase B Phase C Mean ABC VUF in % P N controller P P controller Figure 8: RMS P-N voltage at load bus in laboratory test with unbalanced passive load. The controller is activated at time Figure : VUF during laboratory test of controller with P-N and P-P inputs. PVUR in % P N controller P P controller Figure 9: PVUR during laboratory test of controller with P-N and P-P inputs. ACKNOWLEDGMENT This work has been funded in part by the ForskEl project REFERENCES [] Paranavithana, P.; Perera, S.; Koch, R., An improved methodology for determining MV to LV voltage unbalance transfer coefficient, Harmonics and Quality of Power, 28. ICHQP 28. 3th International Conference on, vol., no., pp.,6, Sept Oct. 28. [2] Singh, B.; Al-Haddad, K.; Chandra, A., A review of active filters for power quality improvement, Industrial Electronics, IEEE Transactions on, vol.46, no.5, pp.96-97, Oct 999. [3] Kim, H.S.; Mok, H.S.; Choe, G.H.; Hyun, D. -S; Choe, S.Y., Design of current controller for 3-phase PWM converter with unbalanced input voltage, Power Electronics Specialists Conference, 998. PESC 98 Record. 29th Annual IEEE, vol., no., pp.53,59 vol., 7-22 May 998. [4] Shuo Yan; Siew-Chong Tan; Chi-Kwan Lee; Chaudhuri, B.; Hui, S.Y.R., Electric Springs for Reducing Power Imbalance in Three-Phase Power Systems, in Power Electronics, IEEE Transactions on, vol.3, no.7, pp , July 25 [5] Lazar, R.D.; Constantin, A., Voltage Balancing in LV Residential Networks by Means of Three Phase PV Inverters, EUPVSEC conference, Frankfurt, Germany, September 24th - 28th 22. [6] Douglass, P.J.; Garcia-Valle, R.; Ostergaard, J.; Tudora, O.C., Voltage- Sensitive Load Controllers for Voltage Regulation and Increased Load Factor in Distribution Systems, Smart Grid, IEEE Transactions on, vol.5, no.5, pp , Sept. 24. [7] IEEE Recommended Practice for Monitoring Electric Power Quality, in IEEE Std (Revision of IEEE Std ), June [8] CENELEC, EN 56, Voltage characteristics of electricity supplied by public distribution systems, 2. [9] IEEE Standard Test Procedure for Polyphase Induction Motors and Generators, in IEEE Std 2-24 (Revision of IEEE Std 2-996), 24. [] Garcia Bajo, C.; Hashemi, S.; Kjsar, S.B.; Guangya Yang; Østergaard, J., Voltage unbalance mitigation in LV networks using three-phase PV systems, in Industrial Technology (ICIT), 25 IEEE International Conference on, pp , 7-9 March 25. [] Danish Energy Association, RA 579B- Voltage variations in.4 kvnetworks with solar cells., 23 [in Danish]. [2] Trintis, I.; Douglass, P.; Maheshwari, R.; Munk-Nielsen, S., SiC heat pump converters with support for voltage unbalance in distribution grids, EPE 25. European Conference on Power Electronics and Application, paper 635, 8- Sept. 25. [3] Alimeling, J.H.; Hammer, W.P., PLECS-piece-wise linear electrical circuit simulation for Simulink, in Power Electronics and Drive Systems, 999. PEDS 99. Proceedings of the IEEE 999 International Conference on, vol., no., pp vol., 999