Design of a 0.7~3.8GHz Wideband. Power Amplifier in 0.18-µm CMOS Process. Zhiyuan Li, Xiangning Fan

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1 Applied Mechanics and Materials Online: ISSN: , Vol. 364, pp doi: / Trans Tech Publications, Switzerland Design of a 0.7~3.8GHz Wideband Power Amplifier in 0.18-µm CMOS Process Zhiyuan Li, Xiangning Fan Institute of RF- & OE-ICs Southeast University, No.2 Sipailou Nanjing , China Keywords: broadband power amplifier, CMOS, lossy matching network, low Q multistage impedance matching network. Abstract. The design of a 0.7~3.8GHz CMOS power amplifier(pa) for multi-band applications in TSMC 0.18-µm CMOS technology is presented. The PA proposed in this paper uses lossy matching network and low Q multistage impedance matching network to improve wideband. To achieve maximum linearity, this PA operates in the Class-A regime. The post-layout simulation results show that the power amplifier achieves 21.9dB of power gain, 22.3dBm of 1dB compression power output at 2GHz. The power adder efficiency(pae) at gain compression point is 17.8% at 2GHz. I. Introduction With the development of wireless communication technology, the modern wireless communication mode and standards emerge in endlessly. Integrating a variety of communication mode on just one mobile device is an important trend. And a lot of new communication systems, that work in broadband frequency ranges appeared. However, most power amplifiers (PA) are traditionally designed for narrow-band operation. So wireless devices needs lots of power amplifier modules to cover a number of wireless applications. To increase integration density and reduce cost, one can use a broadband PA to replace these narrow-band PAs. Now, most of RF PA is implemented in GaAs technology because of its superior device performance. However, CMOS process which has the merit of high level integration becomes a choice of technology for the solution. Due to the recent improvement on RF performances of the CMOS technology, multi-function RF transceivers, including base-band and IF blocks, could be integrated in a single-chip[1]. In this work, a GHz CMOS power amplifier is designed. Lossy matching network and low Q multistage impedance matching network are used to arrive at the broadband. II. Broadband matching network A. Lossy matching network The basic principle of lossy matching network is introducing resistance element in the matching network. In low frequency, resistance absorbs energy, and in high frequency, the resistance has little influence, so that the gain of low frequency and high frequency are equal. Lossy matching network can make balance of gain, bandwidth, reflection coefficient and compromise. Farther more, it can greartly improve the stability of the amplifier. Lossy matching network is used in many cases because it is easy to be designed, and it can reduce the area and price of chips.[2] Fig.1 gives two examples of lossy matching network. All rights reserved. No part of contents of this paper may be reproduced or transmitted in any form or by any means without the written permission of Trans Tech Publications, (ID: , Pennsylvania State University, University Park, USA-06/03/16,12:13:56)

2 430 Mechanical Automation and Materials Engineering Fig.1 Lossy matching network B. Low Q multistage impedance matching network[3] This method includes 4 steps: 1). Determine the port model of the matching network. Perform a series of load-pull simulation over the desired frequency band and a set of optimum impedances will be obtained. The conjugate of these optimum impedances are just the exact port impedance. Choose the average of all conjugated value as the port impedance if they changed little. If they changed a lot, then a simple R-L-C model can be synthesized to approximately model the variation of all conjugated impedances. This R-L-C model can be used as the port model. Another port is the load impedance whose resistance is usually 50Ω. 2). Calculate the maximum Q value of the matching network. Q = f f BW (1) max L H / 3). Draw the port model, load impedance, and constant Q contour in smith chart. Match the port model and load impedance inside the constant Q contour at central frequency as show in Fig. 2. 4). Adjust the value of all components in the matching network to get a better performance. Fig. 3 shows the matching network designed with this method. Fig.2 Low Q multistage impedance matching on Simth chart Fig 3 Low Q multistage impedance matching network III. Circuit The power amplifier employs a two-stage configuration, driver and output stage, as shown in Fig.4. The matching networks are placed at the input, output, or between the stages. Both driver stage and output stage are biased as a Class-A amplifier to get maximum linearity. Design is started from the output stage, to get around 23dBm output power with 3.3V supply voltage at the output stage.

3 Applied Mechanics and Materials Vol Common-source amplifier structure is used to provide highest voltage swing in the output stage. The designed transistor size of M3 is 2048/0.35(µm/µm). The output matching network is realized by low Q multistage impedance matching network. Load-pull shows that the optimum load impedance changes a little with frequency, and the output matching network can transform load impedance close to Ropt over the whole frequency band. Though it is not equal to Ropt strictly, the impedance after transformation could guarantee desired output power. Following the design of output stage, driver stage is then designed. In the design of the driver stage, it is aimed at getting enough voltage to the input of the output stage. Cascode configuration is used for better input-output isolation and high gain. The designed transistor sizes of M1 and M2 are both 768/0.18(µm/µm). The voltage supply of driver stage is 1.8V. The input matching network and matching network between stages are both realized by lossy matching network. It ensures the stability of the circuit and expands the bandwidth. All components outside of the dotted line frame in Fig.4 are placed off-chip, including RF chokes, output matching network and 4 inductances. Finally, differential circuit is used to improve the output power and reduce the effect of source degeneration inductance which introduced by bond wire. Fig.4 Two-stage differential power amplifier circuit IV. Layout and simulation results Fig.5 shows the layout of the PA that designed in TSMC0.18µm CMOS process technology, and the chip size is mm 2. The transistor of the output stage carries a dc current of 114mA, plus the RF current. Therefore, the drain and source contacts must be enlarged in order to be able to handle these large currents. The output device must be as close to the pad as possible. The circuit is simulated in Cadence SpectreRF[4]. The post-simulated S-parameter is shown in Fig. 6. The input return loss and output return loss are both better than 5dB. Fig.6 shows the variation of power gain with respect to frequency. The average power gain is about 20dB from 0.7 to 3.8GHz. The simulated OP 1dB is shown in Fig. 7. The simulated PAE at 1dB compression point is shown in Fig. 8.

4 432 Mechanical Automation and Materials Engineering S21 S11 S22 10 Y(dB) Fig. 5 Power amplifier layout Frequency(MHz) Fig.6 S-Parameter Response OP1dB(dBm) PAE(%) Frequency(MHz) Fig.7 Output 1dB compression point Frequency(MHz) Fig.8 PAE at 1dB compression point The simulated performance of this power amplifier is summarized and compared in Table I. Table I Summary and comparison of PA performances Ref [5] [6] [7] [8] This work Proc. (µm)(cmos) Freq. (GHz) S11(dB) <-10 <-10* <-5 <-5 <-5 S22(dB) <-5 <-10* <-7 <-5 <-5 Avg. Gain(dB) 20* 11* 10* 8.5* 20* Avg. OP 1dB (dbm) 7* 8* 5* 5* 18* Avg. PAE (%)(@OP 1dB ) 9* 6.8* 12* 14.4* 13.5* Supply voltage(v) ,3.3 *Estimated values V. Conclusion This work presents a broadband power amplifier operating from 0.7GHz to 3.8GHz. Lossy matching network and low Q multistage impedance matching network are used to improve wideband. The layout simulation results show that the average OP 1dB achieves more than 18dBm and the average PAE at OP 1dB achieves more than 13.5% from 0.7 GHz-3.8 GHz. The average

5 Applied Mechanics and Materials Vol small signal gain is about 20dB. The layout size is mm 2. Because of the broadband characteristics and 26dBm maximum output power, this PA can be adopted in multi-mode wireless communication systems. Acknowledgments This work is supported by the State Key Development Program for Basic Research of China(973 Program)(Grant No.2010CB327404). References [1]. Sajay Jose, Hyung-Jin Lee and Dong Ha, A Low-power CMOS Power Amplifier for Ultra wideband (UWB) Applications, in International symposium on Circuits and Systems, 2005 IEEE, vol. 5,May 2005, pp [2]. Andrei Grebennikov, RF and Microwave Power Amplifier Design[M], publishing house of electronics industry, pp [3]. Li Wenyuan, Wang Hai, A GHz Broadband Power Amplifier, Communication Technology (ICCT), 2011 IEEE 13th International Conference on, pp [4]. Cadence PA Design Using SpectreRF, Product Version 6.0 November [5]. Xiaopeng Sun, Fengyi Huang, et al, A 0.7-6GHz Broadband CMOS Power Amplifier for Multi-Band Applications Microwave and Millimeter Wave Technology (ICMMT), Volume: 1, Page(s): 1 4,2012 [6]. C. Lu, et al., A CMOS power amplifier for full-band UWB transmitters, IEEE RFIC Symp. Dig., pp , June [7]. S.A.Z Murad, R.K Pokharel, H. Kanaya and K.Yoshida, A GHz CMOS UWB PA for group 1~3 MB-OFDM application using current reused and shunt-shunt feedback, The 2009 International Conference on Wireless Communication and Signal Processing, pp 1-4. [8]. H.-W. Chung, C.-Y. Hsu, C.-Y Yang, K.-F. Wei, and H.-R. Chuang, A 6-10-GHz CMOS Power Amplifier with an Inter-stage Wideband Impedance Transformer For UWB Transmitters, Proceedings of the 38th European Microwave Conference, pp

6 Mechanical Automation and Materials Engineering / Design of a 0.7~3.8GHz Wideband Power Amplifier in 0.18-μm CMOS Process /