DUE TO THE increased awareness of the many undesirable

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1 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 13, NO. 1, JANUARY A Novel Method for Elimination of Line-Current Harmonics in Single-Stage PFC Switching Regulators Martin H. L. Chow, K. W. Siu, Chi K. Tse, Senior Member, IEEE, and Yim-Shu Lee Abstract This paper studies a particular single-stage power-factor-correction (PFC) switching regulator employing a discontinuous-conduction-mode (DCM) boost-input cell and a continuous-current-mode (CCM) forward output cell. Although this single-stage PFC regulator can provide a reasonably high power factor when its PFC stage is operating in discontinuous mode, substantial reduction in line-current harmonics is possible by applying a suitable frequency-modulation scheme. This paper derives a frequency-modulation scheme and proposes a practical implementation using a simple translinear analog circuit. A quantitative analysis on the total harmonics distortion (THD) of the line current when the circuit is subject to a limited range of frequency variation is presented along with some considerations for practical design. Experimental data obtained from a prototype confirms the effectiveness of the proposed frequency-modulation scheme. The proposed analog translinear circuit allows custom integrated circuit (IC) implementation, making it a viable low-cost solution to the elimination of line-current harmonics in switching regulators. Index Terms Control, power factor correction, switch-mode power supplies. I. INTRODUCTION DUE TO THE increased awareness of the many undesirable consequences of harmonic distortions in line currents drawn by switch-mode power supplies (SMPS s), high power factor and low line-current harmonic distortion are expected to be mandatory requirements for SMPS s in coming years. A common approach to satisfy these requirements is to incorporate an additional power-factor-correction (PFC) stage preceding the normal switching converter stage. In this approach, the switching converter maintains a regulated output voltage while the preceding PFC stage ensures a high-input power factor. As such, the combined circuit usually has a lower efficiency and is less cost effective, especially for low-power applications, due to the use of two separate power stages. Recently, Redl et al. [1] proposed a family of topologies for single-stage power-factor-corrected power supplies, which amalgamates a PFC cell with a switching regulator cell to form a single power stage. This family of single-stage PFC power supplies naturally achieves high power factor by employing a Manuscript received August 23, 1996; revised February 7, This work was supported by the Research Grants Council of the University Grants Committee, Hong Kong Polytechnic University. Recommended by Associate Editor, F. D. Tan. The authors are with the Department of Electronic Engineering, Hong Kong Polytechnic University, Hong Kong. Publisher Item Identifier S (98) discontinuous-conduction-mode (DCM) boost cell. This simple boost cell is followed by a second switching cell, e.g., a forward cell, which provides regulated output voltage. An important feature that distinguishes this family of circuits is the sharing of one active switch, or one set of active switches, by the otherwise two separate stages. The general control strategy of the aforementioned circuits involves a simple constant-frequency duty-cycle modulation scheme, which mainly provides output regulation, with the power factor maintained reasonably high by virtue of DCM operation of the boost PFC cell. It is apparent that while these circuits are simple, they have limited performance in terms of PFC. Further performance improvements will be necessary if regulatory bodies impose more stringent restrictions on harmonic distortion in the future. In this paper, we discuss a particular type of the single-stage power-factor-corrected power supplies proposed by Redl et al. [1] in which a DCM boost cell and continuous-current-mode (CCM) forward cell are used. We will derive an appropriate model for the single-stage PFC power supply under investigation, based on which we will develop a novel frequencymodulation scheme for achieving unity power factor, i.e., a harmonic-free line current [2]. We will also study the performance of the frequency-modulation scheme when a limited range of switching frequency excursion is permitted. Analytical as well as experimental results will be presented. In constructing the experimental circuit, we implement the control algorithm with a translinear circuit, which provides the necessary analog computation [4]. Although our experimental circuit employs discrete components, the translinear circuit can be readily implemented in custom IC. Thus, the whole control circuit for the proposed single-stage PFC regulator can be integrated in a single integrated circuit (IC) chip, making it a very practical and low-cost alternative for the design of unity-power-factor power supplies for low-power applications. II. PRINCIPLE OF THE SINGLE-STAGE PFC REGULATOR UNDER STUDY The simplified schematic of a single-stage PFC regulator, comprising of a cascade connection of a boost cell and forward cell, is shown in Fig. 1. The two constituent cells share the same switch Nodes and serve as both the output terminals of the boost cell and the input terminals of the /98$ IEEE

2 76 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 13, NO. 1, JANUARY 1998 Fig. 1. A single-stage PFC regulator using boost-input cell. forward cell. The presence of diode prevents the primary current of transformer from circulating through diode The charging current of capacitor is a rectified sinusoid, which causes a ripple voltage to appear on the output voltage of the boost cell. The amplitude of the ripple voltage would depend on the value of and the input current of the forward cell. With a sufficiently large, the ripple voltage can be kept to a small value compared to the dc component of As a compulsory requirement of any PFC power supply, a storage element is needed to buffer the difference between the instantaneous input power (square of sine) and the instantaneous output power (constant value). In this particular case, capacitor serves the purpose, presenting itself as the load for the boost cell and as the source for the forward cell. In this particular single-stage PFC regulator, the duty cycle of switch is used to regulate output voltage via a voltage feedback loop. Under this condition, it can be shown that the shape of the averaged input current of the boost cell is not an ideal rectified sinusoid. In the following section, we shall establish the averaged model for the single-stage PFC regulator, which will be used to analyze the performance in respect of harmonic distortion, power factor, and voltage stress. Analysis based on the averaged model also leads to a novel frequency-modulation scheme, which can achieve unity power factor, as will be discussed in Section IV. One important feature is worth mentioning here. In its originally proposed form [1], this family of circuits operates both cells in DCM, preventing the voltage stress of the storage capacitor from fluctuating with the load current. However, this will require a more complicated control when frequency modulation is applied to improve power factor since varying the frequency will have effects on the output regulation of the DCM switching cell. Hence, we propose to operate the forward cell in CCM such that output regulation is unaffected by frequency variation. As a result, frequency modulation is used exclusively for achieving unity power factor, while duty-cycle modulation is used for output-voltage regulation. III. DERIVATION OF AVERAGED MODEL FOR THE SINGLE-STAGE PFC REGULATOR In the following discussion, it is assumed that the boost cell is operating in discontinuous mode, whereas the forward cell is Fig. 2. Waveforms of ii and id : in continuous mode. The waveforms of input current of the boost cell and charging current of are shown in Fig. 2, where denotes the switching period, denotes the ontime of switch, and denotes the on time of diode For the boost cell operating in discontinuous mode, we have To avoid confusion, throughout the sequel, overbar denotes averaged values over one switching cycle. By inspection of the waveform shown in Fig. 2, the averaged input current is given by The averaged charging current of Furthermore, with the forward cell operating in continuous mode, the averaged voltage driving the output filter is equal to, and the averaged current discharging is Thus, a complete averaged model [3] for the single-stage PFC regulator can be obtained as shown in Fig. 3. To facilitate steady-state analysis, the following conditions will be assumed whose validity can be readily verified. 1) is essentially a dc voltage by virtue of being sufficiently large. We shall denote this voltage by in the analysis that follows. 2) The output voltage is well regulated, which implies that the duty cycle of switch is constant because is approximately a dc voltage. is (1) (2) (3) (4)

3 CHOW et al.: ELIMINATION OF HARMONICS IN PFC SWITCHING REGULATORS 77 Fig. 3. Averaged behavior model of the single-stage PFC regulator. Fig. 5. Block diagram of a single-stage PFC regulator with a feedforward frequency control scheme. where is the maximum switching period of switch, then the averaged input current as given by (3) becomes (6) Fig. 4. Averaged input current i i waveform with ^v i =V c =0:75: For off-line operation, the input voltage is a rectified sinusoid, where is the angular frequency of the mains. If, then the averaged input current becomes a pure rectified sinusoid, which is the condition for unitypower-factor operation. This requirement necessitates a very large, relative to the mains peak voltage It is apparent that operating the single-stage PFC regulator with a large imposes unfavorably high stress to the devices, while operating with a small results in harmonic distortion and high peakcurrent stress. In Fig. 4, the waveform of the averaged input current, with, is shown, and the dotted curve is a pure rectified sinusoid having the same rms value. IV. PROPOSED METHOD TO ACHIEVE UNITY POWER FACTOR A. Theory For the single-stage PFC regulator shown in Fig. 1, output regulation is achieved by duty-cycle control using voltage feedback. In order to perfectly satisfy the requirement of unity power factor, an additional control parameter must be established. Clearly, a proportional relationship between the averaged input current and the input voltage, i.e., the condition for unity power factor, can be achieved by modulating the switching period Specifically, if the switching period is adjusted according to (5) Consequently, the extra control equation required is (5), which represents a continuous adjustment of the switching frequency according to and, i.e., a feedforward control. The block diagram of a single-stage PFC regulator with such a feedforward frequency control scheme is shown in Fig. 5. In order to arrive at a viable scheme that can be applied to practical systems, the following should be borne in mind. 1) The circuit required to implement the frequency control scheme should be simple enough to allow either a custom IC realization or a circuit implementation involving a relatively few discrete components. 2) The required amount of frequency deviation for a given must not be exceedingly large to complicate magnetic design and electromagnetic interference (EMI) considerations. We shall develop in the next section a simple analog translinear circuit to perform the required computation of the switching frequency. B. Implementation of the Frequency Control Using an Analog Translinear Circuit Referring to Fig. 6, the dashed block is the oscillator circuit of a pulse-width-modulation (PWM) controller chip in which a current mirror provides a current to charge up capacitor The value of is usually adjusted with an external resistor. When the capacitor voltage is equal to a threshold voltage, say, switch turns on and capacitor is discharged. Immediately after the discharge, switch turns off and capacitor is charged up by current again. The circuit oscillates with a constant period determined by the duration

4 78 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 13, NO. 1, JANUARY 1998 Based on the translinear circuit principle [4] (12) or (13) Hence, putting we have and (14) Fig. 6. Translinear circuit for the frequency control. of the charging interval. Specifically If current is controlled according to then the condition of (5) is satisfied with The diagram shown in Fig. 6, excluding the dashed block, is a translinear circuit, which consists of a product-quotient circuit and five current mirrors. All transistors used are identical and have a high current gain such that their base currents are negligible compared to their collector currents. Furthermore, if two transistors have the same voltage, then their collector currents are equal in magnitude. Referring to Fig. 6, and are connected as a current mirror to provide with a collector current of, where (7) (8) (9) (10) In addition, and are connected as a current mirror to provide with a collector current of Similarly, and, and, and and are connected as current mirrors to provide with a collector current of The product-quotient circuit is constructed with and in such a way that (11) which exactly realizes (8). Finally, the required frequency control of (5) can be realized easily by mirroring to the charging current in the PWM block, as shown Fig. 6. In practical implementation, the product-quotient and current mirror circuits can be fabricated as part of a PWM controller chip, and the required voltage rating of the controller is not affected by high values of and since the corresponding inputs to the controller are clamped at Also, the accuracy of the translinear circuit does not depend on the values of the resistances, but rather on the degree of matching between the transistors used. This matching requirement can be easily satisfied with currently available integrated circuit techniques. V. PERFORMANCE ANALYSIS Before we begin to evaluate the performance of the proposed frequency-modulation scheme, we note that unity power factor is possible if an unlimited range of frequency variation is allowed. Thus, it is important, for practical reasons, to study the performance of the control scheme when a limited range of frequency excursion is permitted. Also, unlike the original Redl et al. scheme, which operates both cells in DCM and therefore has the internal capacitor voltage stress independent of the load current, our proposed circuit exhibits variation of the capacitor-voltage stress. Therefore, it is necessary to consider the magnitude of this voltage stress under different operating conditions as presented below. A. Calculation of Power Factor Referring to the averaged behavior model of the single-stage PFC regulator shown in Fig. 3, the averaged input current is given by Putting, (15) becomes (15) (16) Under steady-state operation, can be considered as a dc voltage. Hence, for the purpose of maintaining a regulated

5 CHOW et al.: ELIMINATION OF HARMONICS IN PFC SWITCHING REGULATORS 79 output voltage, the duty cycle can be assumed constant. The rms value of the averaged input current is (17) where has been substituted by for algebraic brevity. The input power is (18) (19) (20) The primary objective of employing switching frequency control to a single-stage PFC regulator is to obtain a unity power factor. However, the amount of frequency deviation required by the proposed control can be unacceptably large. More precisely, from (24), and letting, the maximum switching frequency required is (25) Thus, we observe that minimizing would unfavorably call for a large range of operating frequency if unity power factor is to be maintained. Such a large frequency excursion may drive the boost PFC cell into continuous-mode operation, preventing the single-stage PFC regulator from achieving high power factor. Hence, in practice, it is sensible to impose an upper limit on the switching frequency of the single-stage PFC regulator. A simple way to do this is to introduce a saturation function such that within a half-mains cycle Hence, the power factor of the single-stage PFC regulator is p.f. (21) if otherwise (26) (22) where is the maximum acceptable frequency and is related to the critical instants and by the following: (27) We shall study two cases separately for being constant and for being varied according to the proposed feedforward control scheme. 1) Constant Frequency Operation: When, i.e., constant frequency, the single-stage PFC regulator operates with nonunity power factor. From (22), the power factor is Thus, in a half-mains cycle, the switching frequency for is clamped at, which is the same value given by (24) at or For convenience, we introduce a new quantity, which is defined as (28) p.f. (23) or (29) The curve of power factor versus based on (23), as labeled Const. Freq. in Fig. 8, clearly confirms that at the expense of high voltage stress, the single-stage PFC regulator can achieve high power factor inherently. 2) Feedforward Frequency Control: Since the input voltage is a rectified sinusoid, i.e.,, where is the angular frequency of the mains, the feedforward frequency control given by (5) can be rewritten as (24) Clearly, for a given, determines the extent to which input-current waveform departs from the ideal rectified sinusoid. Fig. 7 illustrates the case where Here, distortion near the peak of the waveform is apparent. In addition, if (30) then the averaged input-current waveform is an ideal rectified sinusoid and unity power factor can be achieved.

6 80 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 13, NO. 1, JANUARY 1998 Fig. 7. Waveform of averaged input current i i with limited frequency deviation. Fig. 9. THD versus ^v i =V c with different F r : B. Calculation of THD In general, the total harmonics distortion (THD) can be found as THD p.f. (32) where is the phase angle between the line voltage and line current. In the case of the single-stage PFC regulator, Fig. 9 shows plots of THD versus with different values of Fig. 8. Power factor versus ^v i =V c with different values of F r : For a given, is determined from (29), and the expression for the power factor is given in (31) at the bottom of the page, where and the involving definite integrals are functions of, the corresponding closed-form expressions given in the Appendix. Fig. 8 shows plots of power factor versus corresponding to different values of It is clear that for a given, the single-stage PFC regulator, with the proposed frequency-modulation control scheme, can achieve higher power factor. VI. DESIGN CONSIDERATIONS The capacitor voltage is an important design parameter for the single-stage PFC regulator. Referring to the averaged model of the single-stage PFC regulator in Fig. 3, and are constant in the steady state. Furthermore, and Then, the capacitor voltage can be determined by equating the average values between the output current of the boost cell and the input current of the forward cell within a half cycle of the ac mains (33) p.f. (31)

7 CHOW et al.: ELIMINATION OF HARMONICS IN PFC SWITCHING REGULATORS 81 operation, it can be shown that [6] (38) where is the effective load resistance of the boost cell. Since the input resistance of the forward cell is,we have Hence, the choice of is given by (39) In the steady state, the condition stated in (1) imposes an upper limit on, which is given by Fig. 10. versus ^v i =V c with different values of F r : Letting and substituting for, the steadystate equation for can be obtained as (34) Using a similar approach as in Section V-B2, the steady-state equation for under the proposed frequency control can be written as where is determined from (29) and is defined by (35) (36) Here, the definite integral is again a function of (see Appendix). Fig. 10 shows plots of versus with different values of It is clear that for a given set of component values and switching frequency, the single-stage PFC regulator can operate with a lower voltage stress [5] by employing the proposed frequency-modulation scheme. The value of is chosen such that the forward cell operates in CCM. This condition is given by (37) where On the other hand, the choice of is to ensure that the boost cell operates in DCM. For a DCM (40) Hence, the value of should be initially chosen for a fullload condition, with close to its upper limit. In addition, Fig. 10 provides a means to estimate the voltage-stress variation under various loading conditions. VII. EXPERIMENTAL DEMONSTRATION A simple circuit prototype for the complete single-stage PFC regulator has been built for demonstration purposes. The circuit parameters are as follows: H H F F and The switching period has been chosen to ensure that the circuit operates in the expected mode, i.e., in DCM and in CCM. The output is regulated at 25 V with a full-load current of 2 A using a current-mode PWM chip UC3844. The translinear circuit for frequency control is constructed with transistor arrays CA3096E. The prototype is tested under full-load condition, and the line-current waveforms have been recorded for performance comparison in terms of power factor and THD. The line voltage is 110 V. A. Constant Frequency Operation Our purpose in this section is to show that the circuit can operate with higher power factor and low line-current harmonic distortion at the expense of higher voltage stress. 1) For s the measured capacitor voltage is 235 V, which corresponds to Fig. 11 shows the filtered line-current waveform, which has a THD of 15.6%, and the measured power factor is ) With s the measured capacitor voltage becomes 282 V, which corresponds to The measured power factor is increased to Fig. 12 shows the filtered line-current waveform, which has a THD of 10.8%, which is less than that of the previous case. B. Feedforward Frequency Control Our purpose in this section is to show that the prototype can operate with practically unity power factor by employing the proposed frequency-modulation scheme. In addition, we

8 82 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 13, NO. 1, JANUARY 1998 Fig. 11. Filtered line-current waveform with constant frequency, ^v i =V c =0:66, p.f. = 0.984, and THD = 15.6%. Fig. 13. Filtered line-current waveform with frequency control, F r =3;^v i =V c =0:66, p.f. = 0.995, and THD = 2.7%. Fig. 12. Filtered line-current waveform with constant frequency, ^v i =V c =0:55, p.f. = 0.991, and THD = 10.8%. Fig. 14. Filtered line-current waveform with frequency control, F r =2;^v i =V c =0:66, p.f. = 0.990, and THD = 11.3%. will examine the performance degradation due to a limited frequency deviation. 1) The maximum switching period is adjusted to 14.4 s such that the measured capacitor voltage is 235 V. Having no limitation on the frequency excursion, the switching period is varied from 4.8 to 14.4 s according to proposed frequency-modulation scheme. Fig. 13 shows the filtered line-current waveform, which is practically harmonic free. The measured power factor is The results are in line with the values shown in the curves, corresponding to, in Figs. 8 and 9. 2) In order to provide a limited frequency excursion, the maximum value of the input voltage of the translinear circuit shown in Fig. 6 is clamped to half of the capacitor voltage such that Then, the maximum switching period is adjusted to 11.6 s such that the measured capacitor voltage is 235 V. The switching period varies from 5.8 to 11.6 s according to the proposed frequency-modulation scheme. Fig. 14 shows the filtered line-current waveform, which has a THD of 11.3% and a power factor of Comparing with Fig. 11, it is clear that the proposed frequencymodulation scheme can reduce distortion in the line current, even though the frequency excursion is very limited. VIII. CONCLUSION The single-stage PFC regulator can provide a reasonably high power factor if its PFC stage is operating under discontinuous mode. The line-current harmonic distortion could be reduced at the expense of a high voltage stress. However, harmonic-free line current, i.e., unity power factor, can be achieved by an appropriate frequency-modulation scheme. In order to simplify the design of the feedback control associated with output regulation, we operate the forward cell in continuous mode, immunizing it against the effect of frequency variation, thus allowing both unity power factor and output regulation to be achieved independently by frequency modulation and duty-cycle modulation. This paper derives a frequency-modulation scheme with a practical implementation based on the translinear circuit principle. A quantitative analysis on the THD of the line current with respect to the

9 CHOW et al.: ELIMINATION OF HARMONICS IN PFC SWITCHING REGULATORS 83 allowable range of frequency variation is also presented. The experimental data obtained from a prototype confirms the effectiveness of the proposed frequency-modulation scheme. Finally, we should reiterate that the proposed analog circuit implementation allows custom IC realization and hence provides a viable low-cost solution to the design of harmonic-free single-stage PFC power supplies for low-power applications. APPENDIX The closed-form expressions for the two definite integrals used in Section V-A2 are Martin H. L. Chow received the B.Sc. degree (Eng.) from the University of Hong Kong, Hong Kong, in 1980 and the M.Sc. degree from the University of Surrey, Guildford, U.K., in He worked in shortwave radio design with Philips, Hong Kong, and in switch-mode power supplies design with Thomson, Singapore. In 1985, he started his teaching career at Hong Kong Polytechnic University, where he is currently a Senior Lecturer in the Department of Electronic Engineering. K. W. Siu received the B.Eng. degree (Hons.) in electronic engineering from the Hong Kong Polytechnic University, Hong Kong, in He is currently working toward the Ph.D. degree in power electronics at the same university. His research interests include PFC circuits for ac dc converters and computer-aided design of switching power supplies. where is used to denote Chi K. Tse (M 90 SM 97) received the B.Eng. degree with first-class honors and the Ph.D. degree, both from the University of Melbourne, Melbourne, Australia, in 1987 and 1991, respectively. He worked in software design with an Australian database company for several years and has spent a short period of time with Astec International Limited, Hong Kong, as a Senior Engineer. He is presently an Assistant Professor at Hong Kong Polytechnic University, where his research interests are in power electronics and chaotic dynamics. He also serves as a Consultant to local manufacturers on electromagnetic compatibility design. Dr. Tse was awarded the L.R. East Prize from the Institution of Engineers, Australia, in In 1993, he initiated the first Hong Kong IEEE Workshop on switch-mode power supplies. In 1995, he was General Chairman of the workshop. He was Technical Program Chairman of the 1994 Symposium on Power Electronics Circuits and Publication Chairman of the 1995 IEEE Region Ten International Conference. He is a Chartered Professional Engineer in Australia. REFERENCES [1] R. Redl, L. Balogh, and N. O. Sokal, A new family of singlestage isolated power-factor-correctors with fast regulation of the output voltage, in IEEE PESC Rec., 1994, pp [2] Y. S. Lee and K. W. Siu, Single-switch fast-response switching regulators with unity power factor, in Proc. APEC 96, San Jose, CA, pp [3] R. D. Middlebrook and S. Ćuk, A general unified approach to modeling switching-converter power stages, in IEEE PESC Rec., 1976, pp [4] C. Toumazou, F. J. Fidgey, and D. G. Haigh, Analogue IC Design: The Current-Mode Approach. London: Peregrinus, 1990, ch. 2. [5] M. M. Jovanović, D. M. C. Tsang, and F. C. Lee, Reduction of voltage stress in integrated high-frequency rectifier-regulators by variablefrequency control, in Proc. APEC 94, Orlando, FL, pp [6] R. P. Severn and G. E. Bloom, Modern DC/DC Switchmode Power Converter Circuits. New York: Van Nostrand Reinhold, 1985, ch. 3. Yim-Shu Lee received the M.Sc. degree from the University of Southampton, Southampton, U.K., and the Ph.D. degree from the University of Hong Kong, Hong Kong, in 1974 and 1988, respectively. He is presently a Professor in the Department of Electronic Engineering, Hong Kong Polytechnic University, where he has been affiliated since December Prior to joining the university, he worked with Cable and Wireless, Rediffusion Television, and the General Post Office, all in Hong Kong. His current research interests include the design of switch-mode power supplies and computer-aided design of analog circuits. He is the author of the book Computer-Aided Design and Analysis of Switch Mode Power Supplies (New York: Marcel Dekker, 1993). Dr. Lee is a Fellow of both the Institution of Electrical Engineers, U.K., and the Hong Kong Institution of Engineers.